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GET /api/1.2/patches/2224431/?format=api
{ "id": 2224431, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224431/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260417120951.3454249-2-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417120951.3454249-2-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-17T12:09:45", "name": "[v3,1/7] mach-snapdragon: Add generic SMEM cache infrastructure", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "702a58512235b8a6a17170e3344e1fcb376bbf93", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/1.2/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260417120951.3454249-2-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 500319, "url": "http://patchwork.ozlabs.org/api/1.2/series/500319/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500319", "date": "2026-04-17T12:09:44", "name": "Add FIT multi-DTB selection for Qualcomm platforms", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500319/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224431/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224431/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=IlpkJnzP;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=hTQxNksZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"IlpkJnzP\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"hTQxNksZ\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxtyB0rzsz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 22:10:58 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 2093A8422D;\n\tFri, 17 Apr 2026 14:10:55 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 18A018425F; Fri, 17 Apr 2026 14:10:54 +0200 (CEST)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1061A83B99\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 14:10:50 +0200 (CEST)", "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63H8OaSu1981934\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 12:10:49 GMT", "from mail-pf1-f200.google.com (mail-pf1-f200.google.com\n [209.85.210.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dk52jk8mr-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 12:10:48 +0000 (GMT)", "by mail-pf1-f200.google.com with SMTP id\n d2e1a72fcca58-82f74f0e3c6so485790b3a.0\n for <u-boot@lists.denx.de>; Fri, 17 Apr 2026 05:10:48 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, aswin.murugan@oss.qualcomm.com,\n sughosh.ganu@arm.com, ilias.apalodimas@linaro.org, gchan9527@gmail.com,\n mchitale@ventanamicro.com, maximmosk4@gmail.com, jonas@kwiboo.se,\n marek.vasut@mailbox.org, quentin.schulz@cherry.de, peng.fan@nxp.com,\n sajattack@postmarketos.org, balaji.selvanathan@oss.qualcomm.com,\n wolfgang.wallner@at.abb.com, e@freeshell.de, yangshiji66@outlook.com,\n jan.kiszka@siemens.com, funderscore@postmarketos.org, hs@nabladev.com,\n kory.maincent@bootlin.com, jj251510319013@gmail.com,\n carlos.lopezr4096@gmail.com, u-boot-qcom@groups.io, u-boot@lists.denx.de", "Subject": "[PATCH v3 1/7] mach-snapdragon: Add generic SMEM cache infrastructure", "Date": "Fri, 17 Apr 2026 17:39:45 +0530", "Message-Id": "<20260417120951.3454249-2-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417120951.3454249-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260417120951.3454249-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 cv=buR8wkai c=1 sm=1 tr=0 ts=69e22348 cx=c_pps\n a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8\n a=EUspDBNiAAAA:8 a=682dY7r96GbnsSvmTqwA:9 a=z-cDqrtxhNcyntRm:21\n a=zc0IvFSfCIW2DFIPzwfm:22", "X-Proofpoint-GUID": "6njLer37ayVwLm88EmuPO4hcW0jlHlUc", "X-Proofpoint-ORIG-GUID": "6njLer37ayVwLm88EmuPO4hcW0jlHlUc", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE3MDEyMiBTYWx0ZWRfX5982XLXtLNDL\n v47wDC6xPM1SbGY0LVy6dGYEX/0vdxgXZVFZc4bNsGVuo+Zcxgsy9s5kSvvxYFA0zvLYbAIkM4x\n xZ5RqDhRgM78RawWllFnTzQSvctCIN1z8u6EVLd/6ygdZvCoqe+b7YPXBsgIUYa2DpDrqrvsD5s\n 6uZ95wlOhA1iXqzEQcwkpiXjDz4Ex4VaNrMCBfeEe+RE/wPkHOkZR4evlBP9jAusOMyE1DNQFey\n ktZe3vLjjkevjMEZEefT7x/ikeWOz3tG/hlFaDwT4Y3fLKbFYwc0OyoeqSbBdDLnBwtJNs0Z6m2\n 38lnoh12QpY6mV7sYFICYeJwZ//A4HoLQWWaeJFRF5rPVcPqDeVBRL17qXnzuafUZcqIKtgvJWj\n 4ycq9azQWDvKGa04ypgcDD/iwO9LqgK7j4QU8tugZK9vbMxi0CSZuvgL2jM8GfrocamVDVi5Qs/\n NgdW+p+/2RACywJgf6A==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-17_01,2026-04-17_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0\n priorityscore=1501 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170122", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add cached access functions for commonly used SMEM data to reduce\nredundant SMEM lookups across the boot process.\n\nThis patch introduces three generic caching functions:\n- qcom_get_smem_device(): Cached SMEM device access\n- qcom_get_socinfo(): Cached socinfo structure access\n- qcom_get_ram_partitions(): Cached RAM partition table access\n\nThe implementation includes new header files for data structures:\n- include/soc/qcom/socinfo.h: Added socinfo header from Linux [1]\n Provides socinfo structure definitions for SoC identification\n and hardware parameters\n- arch/arm/mach-snapdragon/rampart.h: Provides RAM partition table\n structures for memory layout information\n\nThe caching mechanism initializes SMEM data on first access and\nreturns cached pointers on subsequent calls, avoiding expensive\nSMEM lookups during boot. This infrastructure is designed to be\nreusable by other Qualcomm-specific features that require hardware\ninformation from SMEM.\n\nThe functions provide a clean API for accessing:\n- SoC information (chip ID, version, platform details)\n- RAM partition layout for memory size calculations\n- Hardware parameters needed for device-specific configurations\n\n[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/soc/qcom/socinfo.h?id=7dcc1dfaa3d1cd3aafed2beb7086ed34fdb22303\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\nChanges in v3:\n1. Addressed the review comments\n---\n arch/arm/mach-snapdragon/board.c | 95 +++++++++++\n arch/arm/mach-snapdragon/qcom-priv.h | 24 +++\n arch/arm/mach-snapdragon/rampart.h | 225 +++++++++++++++++++++++++++\n include/soc/qcom/socinfo.h | 114 ++++++++++++++\n 4 files changed, 458 insertions(+)\n create mode 100644 arch/arm/mach-snapdragon/rampart.h\n create mode 100644 include/soc/qcom/socinfo.h", "diff": "diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\nindex 5fb3240acc5..6edb61b5b36 100644\n--- a/arch/arm/mach-snapdragon/board.c\n+++ b/arch/arm/mach-snapdragon/board.c\n@@ -16,6 +16,7 @@\n #include <asm/system.h>\n #include <dm/device.h>\n #include <dm/pinctrl.h>\n+#include <dm/uclass.h>\n #include <dm/uclass-internal.h>\n #include <dm/read.h>\n #include <power/regulator.h>\n@@ -30,6 +31,7 @@\n #include <malloc.h>\n #include <fdt_support.h>\n #include <usb.h>\n+#include <smem.h>\n #include <sort.h>\n #include <time.h>\n \n@@ -39,6 +41,16 @@ DECLARE_GLOBAL_DATA_PTR;\n \n enum qcom_boot_source qcom_boot_source __section(\".data\") = 0;\n \n+/**\n+ * struct smem_cache - Cached SMEM device and data pointers\n+ * @soc_info: Pointer to the SoC info structure\n+ * @ram_part: Pointer to the RAM partition table\n+ */\n+static struct {\n+\tstruct socinfo *soc_info;\n+\tstruct usable_ram_partition_table *ram_part;\n+} smem_cache;\n+\n static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };\n \n struct mm_region *mem_map = rbx_mem_map;\n@@ -749,3 +761,86 @@ void enable_caches(void)\n \t}\n \tdcache_enable();\n }\n+\n+/**\n+ * qcom_get_smem_device() - Get cached SMEM device\n+ *\n+ * This function provides cached access to the SMEM device.\n+ * On first call, it initializes the SMEM device.\n+ * Subsequent calls return the cached pointer.\n+ *\n+ * Return: Pointer to SMEM device on success, NULL on failure\n+ */\n+struct udevice *qcom_get_smem_device(void)\n+{\n+\tstruct udevice *dev;\n+\n+\tif (uclass_first_device_err(UCLASS_SMEM, &dev)) {\n+\t\tlog_err(\"Failed to get SMEM device\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn dev;\n+}\n+\n+/**\n+ * qcom_get_socinfo() - Get cached socinfo from SMEM\n+ *\n+ * This function provides cached access to the socinfo structure from SMEM.\n+ * On first call, it initializes the SMEM device and retrieves the socinfo.\n+ * Subsequent calls return the cached pointer.\n+ *\n+ * Return: Pointer to socinfo structure on success, NULL on failure\n+ */\n+struct socinfo *qcom_get_socinfo(void)\n+{\n+\tsize_t size;\n+\tstruct udevice *dev;\n+\n+\tif (smem_cache.soc_info)\n+\t\treturn smem_cache.soc_info;\n+\n+\tdev = qcom_get_smem_device();\n+\tif (!dev)\n+\t\treturn NULL;\n+\n+\tsmem_cache.soc_info = smem_get(dev, 0, SMEM_HW_SW_BUILD_ID, &size);\n+\tif (!smem_cache.soc_info) {\n+\t\tlog_err(\"Failed to get socinfo from SMEM\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn smem_cache.soc_info;\n+}\n+\n+/**\n+ * qcom_get_ram_partitions() - Get cached RAM partition table from SMEM\n+ *\n+ * This function provides cached access to the RAM partition table from SMEM.\n+ * On first call, it retrieves the partition table from SMEM.\n+ * Subsequent calls return the cached pointer.\n+ *\n+ * Return: Pointer to RAM partition table on success, NULL on failure\n+ */\n+struct usable_ram_partition_table *qcom_get_ram_partitions(void)\n+{\n+\tsize_t size;\n+\tstruct udevice *dev;\n+\n+\tif (smem_cache.ram_part)\n+\t\treturn smem_cache.ram_part;\n+\n+\tdev = qcom_get_smem_device();\n+\tif (!dev)\n+\t\treturn NULL;\n+\n+\tsmem_cache.ram_part = smem_get(dev, 0,\n+\t\t\t\t SMEM_USABLE_RAM_PARTITION_TABLE,\n+\t\t\t\t &size);\n+\tif (!smem_cache.ram_part) {\n+\t\tlog_err(\"Failed to get RAM partition table from SMEM\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn smem_cache.ram_part;\n+}\ndiff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h\nindex b8bf574e8bb..ae426c9512d 100644\n--- a/arch/arm/mach-snapdragon/qcom-priv.h\n+++ b/arch/arm/mach-snapdragon/qcom-priv.h\n@@ -3,6 +3,9 @@\n #ifndef __QCOM_PRIV_H__\n #define __QCOM_PRIV_H__\n \n+#include <soc/qcom/socinfo.h>\n+#include \"rampart.h\"\n+\n /**\n * enum qcom_boot_source - Track where we got loaded from.\n * Used for capsule update logic.\n@@ -17,6 +20,27 @@ enum qcom_boot_source {\n \n extern enum qcom_boot_source qcom_boot_source;\n \n+/**\n+ * qcom_get_smem_device() - Get cached SMEM device\n+ *\n+ * Return: Pointer to SMEM device on success, NULL on failure\n+ */\n+struct udevice *qcom_get_smem_device(void);\n+\n+/**\n+ * qcom_get_socinfo() - Get cached socinfo from SMEM\n+ *\n+ * Return: Pointer to socinfo structure on success, NULL on failure\n+ */\n+struct socinfo *qcom_get_socinfo(void);\n+\n+/**\n+ * qcom_get_ram_partitions() - Get cached RAM partition table from SMEM\n+ *\n+ * Return: Pointer to RAM partition table on success, NULL on failure\n+ */\n+struct usable_ram_partition_table *qcom_get_ram_partitions(void);\n+\n #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)\n void qcom_configure_capsule_updates(void);\n #else\ndiff --git a/arch/arm/mach-snapdragon/rampart.h b/arch/arm/mach-snapdragon/rampart.h\nnew file mode 100644\nindex 00000000000..b6f056af2d0\n--- /dev/null\n+++ b/arch/arm/mach-snapdragon/rampart.h\n@@ -0,0 +1,225 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * RAM partition table definitions\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ */\n+\n+#define SMEM_USABLE_RAM_PARTITION_TABLE\t\t402\n+\n+#define RAM_PARTITION_H_MAJOR 03\n+#define RAM_PARTITION_H_MINOR 00\n+\n+\n+/**\n+ * Total length of zero filled name string. This is not a C\n+ * string, as it can occupy the total number of bytes, and if\n+ * it does, it does not require a zero terminator. It cannot\n+ * be manipulated with standard string handling library functions.\n+ */\n+#define RAM_PART_NAME_LENGTH 16\n+\n+/**\n+ * Number of RAM partition entries which are usable by APPS.\n+ */\n+#define RAM_NUM_PART_ENTRIES 32\n+\n+/**\n+ * @name: Magic numbers\n+ * Used in identifying valid RAM partition table.\n+ */\n+#define RAM_PART_MAGIC1 0x9da5e0a8\n+#define RAM_PART_MAGIC2 0xaf9ec4e2\n+\n+/**\n+ * Must increment this version number whenever RAM structure of\n+ * RAM partition table changes.\n+ */\n+#define RAM_PARTITION_VERSION 0x3\n+\n+/*\n+ * Value which indicates the partition can grow to fill the\n+ * rest of RAM. Must only be used on the last partition.\n+ */\n+#define RAM_PARTITION_GROW 0xffffffff\n+\n+/**\n+ * RAM partition API return types.\n+ */\n+enum ram_partition_return_type {\n+\tRAM_PART_SUCCESS = 0, /* Successful return from API */\n+\tRAM_PART_NULL_PTR_ERR, /* Partition table/entry null pointer */\n+\tRAM_PART_OUT_OF_BOUND_PTR_ERR, /* Partition table pointer is not in SMEM */\n+\tRAM_PART_TABLE_EMPTY_ERR, /* Trying to delete entry from empty table */\n+\tRAM_PART_TABLE_FULL_ERR, /* Trying to add entry to full table */\n+\tRAM_PART_CATEGORY_NOT_EXIST_ERR, /* Partition doesn't belong to any memory category */\n+\tRAM_PART_OTHER_ERR, /* Unknown error */\n+\tRAM_PART_RETURN_MAX_SIZE = 0x7fffffff\n+};\n+\n+/**\n+ * RAM partition attributes.\n+ */\n+enum ram_partition_attribute_t {\n+\tRAM_PARTITION_DEFAULT_ATTRB = ~0, /* No specific attribute definition */\n+\tRAM_PARTITION_READ_ONLY = 0, /* Read-only RAM partition */\n+\tRAM_PARTITION_READWRITE, /* Read/write RAM partition */\n+\tRAM_PARTITION_ATTRIBUTE_MAX_SIZE = 0x7fffffff\n+};\n+\n+/**\n+ * RAM partition categories.\n+ */\n+enum ram_partition_category_t {\n+\tRAM_PARTITION_DEFAULT_CATEGORY = ~0, /* No specific category definition */\n+\tRAM_PARTITION_IRAM = 4, /* IRAM RAM partition */\n+\tRAM_PARTITION_IMEM = 5, /* IMEM RAM partition */\n+\tRAM_PARTITION_SDRAM = 14, /* SDRAM type without specific bus information**/\n+\tRAM_PARTITION_CATEGORY_MAX_SIZE = 0x7fffffff\n+};\n+\n+/**\n+ * RAM Partition domains.\n+ * @note: For shared RAM partition, domain value would be 0b11:\\n\n+ * RAM_PARTITION_APPS_DOMAIN | RAM_PARTITION_MODEM_DOMAIN.\n+ */\n+enum ram_partition_domain_t {\n+\tRAM_PARTITION_DEFAULT_DOMAIN = 0, /* 0b00: No specific domain definition */\n+\tRAM_PARTITION_APPS_DOMAIN = 1, /* 0b01: APPS RAM partition */\n+\tRAM_PARTITION_MODEM_DOMAIN = 2, /* 0b10: MODEM RAM partition */\n+\tRAM_PARTITION_DOMAIN_MAX_SIZE = 0x7fffffff\n+};\n+\n+/**\n+ * RAM Partition types.\n+ * @note: The RAM_PARTITION_SYS_MEMORY type represents DDR rams that are attached\n+ * to the current system.\n+ */\n+enum ram_partition_type_t {\n+\tRAM_PARTITION_SYS_MEMORY = 1, /* system memory */\n+\tRAM_PARTITION_BOOT_REGION_MEMORY1, /* boot loader memory 1 */\n+\tRAM_PARTITION_BOOT_REGION_MEMORY2, /* boot loader memory 2, reserved */\n+\tRAM_PARTITION_APPSBL_MEMORY, /* apps boot loader memory */\n+\tRAM_PARTITION_APPS_MEMORY, /* apps usage memory */\n+\tRAM_PARTITION_TOOLS_FV_MEMORY, /* tools usage memory */\n+\tRAM_PARTITION_QUANTUM_FV_MEMORY, /* quantum usage memory */\n+\tRAM_PARTITION_QUEST_FV_MEMORY, /* quest usage memory */\n+\tRAM_PARTITION_TYPE_MAX_SIZE = 0x7fffffff\n+};\n+\n+/* Holds information for an entry in the RAM partition table */\n+struct ram_partition_entry {\n+\tchar name[RAM_PART_NAME_LENGTH]; /* Partition name, unused for now */\n+\tu64 start_address; /* Partition start address in RAM */\n+\tu64 length; /* Partition length in RAM in Bytes */\n+\tu32 partition_attribute; /* Partition attribute */\n+\tu32 partition_category; /* Partition category */\n+\tu32 partition_domain; /* Partition domain */\n+\tu32 partition_type; /* Partition type */\n+\tu32 num_partitions; /* Number of partitions on device */\n+\tu32 hw_info; /* hw information such as type and frequency */\n+\tu8 highest_bank_bit; /* Highest bit corresponding to a bank */\n+\tu8 reserve0; /* Reserved for future use */\n+\tu8 reserve1; /* Reserved for future use */\n+\tu8 reserve2; /* Reserved for future use */\n+\tu32 min_pasr_size; /* Minimum PASR size in MB */\n+\tu64 available_length; /* Available Partition length in RAM in Bytes */\n+};\n+\n+/*\n+ * Defines the RAM partition table structure\n+ *\n+ * Do not change the placement of the first four elements so that future\n+ * compatibility will always be guaranteed at least for the identifiers.\n+ *\n+ * The other portion of the structure may be changed as necessary to accommodate\n+ * new features. Be sure to increment version number if you change it.\n+ */\n+struct usable_ram_partition_table {\n+\tu32 magic1; /* Magic number to identify valid RAM partition table */\n+\tu32 magic2; /* Magic number to identify valid RAM partition table */\n+\tu32 version; /* Version number to track structure definition changes */\n+\tu32 reserved1; /* Reserved for future use */\n+\n+\tu32 num_partitions; /* Number of RAM partition table entries */\n+\n+\tu32 reserved2; /* Added for 8 bytes alignment of header */\n+\n+\t/* RAM partition table entries */\n+\tstruct ram_partition_entry ram_part_entry[RAM_NUM_PART_ENTRIES];\n+};\n+\n+/* Version 1 structure 32 Bit - Holds information for an entry in the RAM partition table */\n+struct ram_partition_entry_v1 {\n+\tchar name[RAM_PART_NAME_LENGTH]; /* Partition name, unused for now */\n+\tu64 start_address; /* Partition start address in RAM */\n+\tu64 length; /* Partition length in RAM in Bytes */\n+\tu32 partition_attribute; /* Partition attribute */\n+\tu32 partition_category; /* Partition category */\n+\tu32 partition_domain; /* Partition domain */\n+\tu32 partition_type; /* Partition type */\n+\tu32 num_partitions; /* Number of partitions on device */\n+\tu32 hw_info; /* hw information such as type and frequency */\n+\tu32 reserved4; /* Reserved for future use */\n+\tu32 reserved5; /* Reserved for future use */\n+};\n+\n+/*\n+ * Defines the RAM partition table structure (Version 1)\n+ *\n+ * Do not change the placement of the first four elements so that future\n+ * compatibility will always be guaranteed at least for the identifiers.\n+ *\n+ * The other portion of the structure may be changed as necessary to accommodate\n+ * new features. Be sure to increment version number if you change it.\n+ */\n+struct usable_ram_partition_table_v1 {\n+\tu32 magic1; /* Magic number to identify valid RAM partition table */\n+\tu32 magic2; /* Magic number to identify valid RAM partition table */\n+\tu32 version; /* Version number to track structure definition changes */\n+\tu32 reserved1; /* Reserved for future use */\n+\n+\tu32 num_partitions; /* Number of RAM partition table entries */\n+\n+\tu32 reserved2; /* Added for 8 bytes alignment of header */\n+\n+\t/* RAM partition table entries */\n+\tstruct ram_partition_entry_v1 ram_part_entry_v1[RAM_NUM_PART_ENTRIES];\n+};\n+\n+/* Version 0 structure 32 Bit - Holds information for an entry in the RAM partition table */\n+struct ram_partition_entry_v0 {\n+\tchar name[RAM_PART_NAME_LENGTH]; /* Partition name, unused for now */\n+\tu32 start_address; /* Partition start address in RAM */\n+\tu32 length; /* Partition length in RAM in Bytes */\n+\tu32 partition_attribute; /* Partition attribute */\n+\tu32 partition_category; /* Partition category */\n+\tu32 partition_domain; /* Partition domain */\n+\tu32 partition_type; /* Partition type */\n+\tu32 num_partitions; /* Number of partitions on device */\n+\tu32 reserved3; /* Reserved for future use */\n+\tu32 reserved4; /* Reserved for future use */\n+\tu32 reserved5; /* Reserved for future use */\n+};\n+\n+/*\n+ * Defines the RAM partition table structure (Version 0)\n+ *\n+ * Do not change the placement of the first four elements so that future\n+ * compatibility will always be guaranteed at least for the identifiers.\n+ *\n+ * The other portion of the structure may be changed as necessary to accommodate\n+ * new features. Be sure to increment version number if you change it.\n+ */\n+struct usable_ram_partition_table_v0 {\n+\tu32 magic1; /* Magic number to identify valid RAM partition table */\n+\tu32 magic2; /* Magic number to identify valid RAM partition table */\n+\tu32 version; /* Version number to track structure definition changes */\n+\tu32 reserved1; /* Reserved for future use */\n+\n+\tu32 num_partitions; /* Number of RAM partition table entries */\n+\n+\t/* RAM partition table entries */\n+\tstruct ram_partition_entry_v0 ram_part_entry_v0[RAM_NUM_PART_ENTRIES];\n+};\ndiff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h\nnew file mode 100644\nindex 00000000000..1bb6e200e1f\n--- /dev/null\n+++ b/include/soc/qcom/socinfo.h\n@@ -0,0 +1,114 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#ifndef __QCOM_SOCINFO_H__\n+#define __QCOM_SOCINFO_H__\n+\n+#include <linux/types.h>\n+\n+/*\n+ * SMEM item id, used to acquire handles to respective\n+ * SMEM region.\n+ */\n+#define SMEM_HW_SW_BUILD_ID\t\t137\n+\n+#define SMEM_SOCINFO_BUILD_ID_LENGTH\t32\n+#define SMEM_SOCINFO_CHIP_ID_LENGTH\t32\n+\n+/*\n+ * SoC version type with major number in the upper 16 bits and minor\n+ * number in the lower 16 bits.\n+ */\n+#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)\n+#define SOCINFO_MINOR(ver) ((ver) & 0xffff)\n+#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16) | ((min) & 0xffff))\n+\n+/* Socinfo SMEM item structure */\n+struct socinfo {\n+\t__le32 fmt;\n+\t__le32 id;\n+\t__le32 ver;\n+\tchar build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];\n+\t/* Version 2 */\n+\t__le32 raw_id;\n+\t__le32 raw_ver;\n+\t/* Version 3 */\n+\t__le32 hw_plat;\n+\t/* Version 4 */\n+\t__le32 plat_ver;\n+\t/* Version 5 */\n+\t__le32 accessory_chip;\n+\t/* Version 6 */\n+\t__le32 hw_plat_subtype;\n+\t/* Version 7 */\n+\t__le32 pmic_model;\n+\t__le32 pmic_die_rev;\n+\t/* Version 8 */\n+\t__le32 pmic_model_1;\n+\t__le32 pmic_die_rev_1;\n+\t__le32 pmic_model_2;\n+\t__le32 pmic_die_rev_2;\n+\t/* Version 9 */\n+\t__le32 foundry_id;\n+\t/* Version 10 */\n+\t__le32 serial_num;\n+\t/* Version 11 */\n+\t__le32 num_pmics;\n+\t__le32 pmic_array_offset;\n+\t/* Version 12 */\n+\t__le32 chip_family;\n+\t__le32 raw_device_family;\n+\t__le32 raw_device_num;\n+\t/* Version 13 */\n+\t__le32 nproduct_id;\n+\tchar chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];\n+\t/* Version 14 */\n+\t__le32 num_clusters;\n+\t__le32 ncluster_array_offset;\n+\t__le32 num_subset_parts;\n+\t__le32 nsubset_parts_array_offset;\n+\t/* Version 15 */\n+\t__le32 nmodem_supported;\n+\t/* Version 16 */\n+\t__le32 feature_code;\n+\t__le32 pcode;\n+\t__le32 npartnamemap_offset;\n+\t__le32 nnum_partname_mapping;\n+\t/* Version 17 */\n+\t__le32 oem_variant;\n+\t/* Version 18 */\n+\t__le32 num_kvps;\n+\t__le32 kvps_offset;\n+\t/* Version 19 */\n+\t__le32 num_func_clusters;\n+\t__le32 boot_cluster;\n+\t__le32 boot_core;\n+};\n+\n+/* Internal feature codes */\n+enum qcom_socinfo_feature_code {\n+\t/* External feature codes */\n+\tSOCINFO_FC_UNKNOWN = 0x0,\n+\tSOCINFO_FC_AA,\n+\tSOCINFO_FC_AB,\n+\tSOCINFO_FC_AC,\n+\tSOCINFO_FC_AD,\n+\tSOCINFO_FC_AE,\n+\tSOCINFO_FC_AF,\n+\tSOCINFO_FC_AG,\n+\tSOCINFO_FC_AH,\n+};\n+\n+/* Internal feature codes */\n+/* Valid values: 0 <= n <= 0xf */\n+#define SOCINFO_FC_Yn(n)\t\t(0xf1 + (n))\n+#define SOCINFO_FC_INT_MAX\t\tSOCINFO_FC_Yn(0xf)\n+\n+/* Product codes */\n+#define SOCINFO_PC_UNKNOWN\t\t0\n+#define SOCINFO_PCn(n)\t\t\t((n) + 1)\n+#define SOCINFO_PC_RESERVE\t\t(BIT(31) - 1)\n+\n+#endif\n", "prefixes": [ "v3", "1/7" ] }