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GET /api/1.2/patches/2224361/?format=api
{ "id": 2224361, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224361/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-2-xiaoou@iscas.ac.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417104652.17857-2-xiaoou@iscas.ac.cn>", "list_archive_url": null, "date": "2026-04-17T10:46:38", "name": "[01/14] target/riscv: rvp: Add option defines and dependency check for packed simd extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "028108d997575cd281ef6c29e32bed3fb0c3c49b", "submitter": { "id": 89843, "url": "http://patchwork.ozlabs.org/api/1.2/people/89843/?format=api", "name": "Molly Chen", "email": "xiaoou@iscas.ac.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-2-xiaoou@iscas.ac.cn/mbox/", "series": [ { "id": 500307, "url": "http://patchwork.ozlabs.org/api/1.2/series/500307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500307", "date": "2026-04-17T10:46:37", "name": "target/riscv: add support for RISC-V P extension (v0.20 draft)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224361/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224361/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxs715JgCz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:48:29 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgjE-00011L-Ps; Fri, 17 Apr 2026 06:47:16 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjB-00010B-8U; Fri, 17 Apr 2026 06:47:14 -0400", "from smtp21.cstnet.cn ([159.226.251.21] helo=cstnet.cn)\n by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgj8-0007u8-ED; Fri, 17 Apr 2026 06:47:13 -0400", "from Huawei.localdomain (unknown [36.110.52.2])\n by APP-01 (Coremail) with SMTP id qwCowAB3H2ulD+JpLDmSDQ--.804S3;\n Fri, 17 Apr 2026 18:47:05 +0800 (CST)" ], "From": "Molly Chen <xiaoou@iscas.ac.cn>", "To": "palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com,\n daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com", "Cc": "xiaoou@iscas.ac.cn,\n\tqemu-riscv@nongnu.org,\n\tqemu-devel@nongnu.org", "Subject": "[PATCH 01/14] target/riscv: rvp: Add option defines and dependency\n check for packed simd extension", "Date": "Fri, 17 Apr 2026 18:46:38 +0800", "Message-Id": "<20260417104652.17857-2-xiaoou@iscas.ac.cn>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "References": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qwCowAB3H2ulD+JpLDmSDQ--.804S3", "X-Coremail-Antispam": "1UD129KBjvJXoWxGw1UurWrtryrurWkuw4rKrg_yoW5Zr4Upr\n ZxG3yakw4DJayfAa93trykXFn8WrsYgws7Kwsruw4xAFZ5ArWUWrnxtw4j9r43GFWrZF42\n 93Wv9F13ZFWUZFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2\n x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0\n Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84\n ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I2\n 62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV\n AFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG\n 0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_Jw0_GFyl42\n xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU\n GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4\n 8JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U\n MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I\n 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUn2-5UUUUU", "X-Originating-IP": "[36.110.52.2]", "X-CM-SenderInfo": "50ld003x6l2u1dvotugofq/", "Received-SPF": "pass client-ip=159.226.251.21; envelope-from=xiaoou@iscas.ac.cn;\n helo=cstnet.cn", "X-Spam_score_int": "-21", "X-Spam_score": "-2.2", "X-Spam_bar": "--", "X-Spam_report": "(-2.2 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.998,\n HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Co-Authored by: Yin Zhang <zhangyin2018@iscas.ac.cn>\nCo-Authored by: Dajun Huang <djhuang_1@std.uestc.edu.cn>\nCo-Authored by: Zhiyuan Yang <zhiyuan.plct@isrc.iscas.ac.cn>\n\nSigned-off-by: Molly Chen <xiaoou@iscas.ac.cn>\n---\n target/riscv/cpu.c | 5 +++--\n target/riscv/cpu.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++\n 3 files changed, 20 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f1..c630faa892 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -41,7 +41,7 @@\n /* RISC-V CPU definitions */\n static const char riscv_single_letter_exts[] = \"IEMAFDQCBPVH\";\n const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,\n- RVC, RVS, RVU, RVH, RVG, RVB, 0};\n+ RVC, RVS, RVU, RVH, RVG, RVB, RVP, 0};\n \n /*\n * From vector_helper.c\n@@ -1172,7 +1172,8 @@ static const MISAExtInfo misa_ext_info_arr[] = {\n MISA_EXT_INFO(RVH, \"h\", \"Hypervisor\"),\n MISA_EXT_INFO(RVV, \"v\", \"Vector operations\"),\n MISA_EXT_INFO(RVG, \"g\", \"General purpose (IMAFD_Zicsr_Zifencei)\"),\n- MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\")\n+ MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\"),\n+ MISA_EXT_INFO(RVP, \"x-p\", \"Packed-SIMD instructions\")\n };\n \n static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)\ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53..e08f57d282 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n #define RVH RV('H')\n #define RVG RV('G')\n #define RVB RV('B')\n+#define RVP RV('P')\n \n extern const uint32_t misa_bits[];\n const char *riscv_get_misa_ext_name(uint32_t bit);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f7808895..4545ae721c 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -601,6 +601,11 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu)\n }\n }\n \n+static void riscv_cpu_validate_p(RISCVCPU *cpu)\n+{\n+ /* Enable sub-extensions here. Do nothing for now. */\n+}\n+\n /*\n * Check consistency between chosen extensions while setting\n * cpu->cfg accordingly.\n@@ -619,6 +624,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n riscv_cpu_validate_b(cpu);\n }\n \n+ if (riscv_has_ext(env, RVP)) {\n+ riscv_cpu_validate_p(cpu);\n+ }\n+\n if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {\n error_setg(errp,\n \"I and E extensions are incompatible\");\n@@ -683,6 +692,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n return;\n }\n \n+ if (riscv_has_ext(env, RVP) &&\n+ !(cpu->cfg.ext_zba && cpu->cfg.ext_zbb && cpu->cfg.ext_zbkb)) {\n+ error_setg(errp, \"P extension requires zba, zbb and zbkb extensions\");\n+ return;\n+ }\n+\n riscv_cpu_validate_v(env, &cpu->cfg, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n@@ -1413,6 +1428,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {\n MISA_CFG(RVV, false),\n MISA_CFG(RVG, false),\n MISA_CFG(RVB, false),\n+ MISA_CFG(RVP, false),\n };\n \n /*\n", "prefixes": [ "01/14" ] }