[{"id":3680574,"web_url":"http://patchwork.ozlabs.org/comment/3680574/","msgid":"<336c0c4b-af67-4cb8-91f3-704348124f55@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-22T11:52:15","subject":"Re: [PATCH 01/14] target/riscv: rvp: Add option defines and\n dependency check for packed simd extension","submitter":{"id":92288,"url":"http://patchwork.ozlabs.org/api/people/92288/","name":"Daniel Henrique Barboza","email":"daniel.barboza@oss.qualcomm.com"},"content":"On 4/17/2026 7:46 AM, Molly Chen wrote:\n> Co-Authored by: Yin Zhang \n> Co-Authored by: Dajun Huang \n> Co-Authored by: Zhiyuan Yang \n> \n> Signed-off-by: Molly Chen \n> ---\n> target/riscv/cpu.c | 5 +++--\n> target/riscv/cpu.h | 1 +\n> target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++\n> 3 files changed, 20 insertions(+), 2 deletions(-)\n> \n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 72c6f4f0f1..c630faa892 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -41,7 +41,7 @@\n> /* RISC-V CPU definitions */\n> static const char riscv_single_letter_exts[] = \"IEMAFDQCBPVH\";\n> const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,\n> - RVC, RVS, RVU, RVH, RVG, RVB, 0};\n> + RVC, RVS, RVU, RVH, RVG, RVB, RVP, 0};\n> \n> /*\n> * From vector_helper.c\n> @@ -1172,7 +1172,8 @@ static const MISAExtInfo misa_ext_info_arr[] = {\n> MISA_EXT_INFO(RVH, \"h\", \"Hypervisor\"),\n> MISA_EXT_INFO(RVV, \"v\", \"Vector operations\"),\n> MISA_EXT_INFO(RVG, \"g\", \"General purpose (IMAFD_Zicsr_Zifencei)\"),\n> - MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\")\n> + MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\"),\n> + MISA_EXT_INFO(RVP, \"x-p\", \"Packed-SIMD instructions\")\n> };\n> \n> static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)\n> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\n> index 4c0676ed53..e08f57d282 100644\n> --- a/target/riscv/cpu.h\n> +++ b/target/riscv/cpu.h\n> @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n> #define RVH RV('H')\n> #define RVG RV('G')\n> #define RVB RV('B')\n> +#define RVP RV('P')\n> \n> extern const uint32_t misa_bits[];\n> const char *riscv_get_misa_ext_name(uint32_t bit);\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index f3f7808895..4545ae721c 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -601,6 +601,11 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu)\n> }\n> }\n> \n> +static void riscv_cpu_validate_p(RISCVCPU *cpu)\n> +{\n> + /* Enable sub-extensions here. Do nothing for now. */\n> +}\n\nTo enable sub-extensions/dependencies we have implicit/implied rules\n(e.g. RVA_IMPLIED in target/riscv/cpu.c). I believe we should also use\nthis logic here when the time comes.\n\nUsually we use 'validate' functions to assert if the preconditions are met, so\nbasically what you ended up doing down there:\n\n\n > + if (riscv_has_ext(env, RVP) &&\n > + !(cpu->cfg.ext_zba && cpu->cfg.ext_zbb && cpu->cfg.ext_zbkb)) {\n > + error_setg(errp, \"P extension requires zba, zbb and zbkb extensions\");\n > + return;\n > + }\n > +\n\n\nI believe this piece of code should be put in riscv_cpu_validate_p().\n\n\nThe rest LGTM. Thanks,\nDaniel\n\n> +\n> /*\n> * Check consistency between chosen extensions while setting\n> * cpu->cfg accordingly.\n> @@ -619,6 +624,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n> riscv_cpu_validate_b(cpu);\n> }\n> \n> + if (riscv_has_ext(env, RVP)) {\n> + riscv_cpu_validate_p(cpu);\n> + }\n> +\n> if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {\n> error_setg(errp,\n> \"I and E extensions are incompatible\");\n> @@ -683,6 +692,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n> return;\n> }\n> \n> + if (riscv_has_ext(env, RVP) &&\n> + !(cpu->cfg.ext_zba && cpu->cfg.ext_zbb && cpu->cfg.ext_zbkb)) {\n> + error_setg(errp, \"P extension requires zba, zbb and zbkb extensions\");\n> + return;\n> + }\n> +\n> riscv_cpu_validate_v(env, &cpu->cfg, &local_err);\n> if (local_err != NULL) {\n> error_propagate(errp, local_err);\n> @@ -1413,6 +1428,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {\n> MISA_CFG(RVV, false),\n> MISA_CFG(RVG, false),\n> MISA_CFG(RVB, false),\n> + MISA_CFG(RVP, false),\n> };\n> \n> /*","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=S0950d8I;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Ot85HlsB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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