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GET /api/1.2/patches/2223475/?format=api
{ "id": 2223475, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260415110301.1701251-1-wangzicong@masscore.cn/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.2/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415110301.1701251-1-wangzicong@masscore.cn>", "list_archive_url": null, "date": "2026-04-15T11:03:01", "name": "[v2] RISC-V: Make tuple vector not tieable to some modes.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a131c82d95cfa4c7b1cf707ce4c98dfb1cd610bf", "submitter": { "id": 93140, "url": "http://patchwork.ozlabs.org/api/1.2/people/93140/?format=api", "name": "wangzicong", "email": "wangzicong@masscore.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260415110301.1701251-1-wangzicong@masscore.cn/mbox/", "series": [ { "id": 499968, "url": "http://patchwork.ozlabs.org/api/1.2/series/499968/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499968", "date": "2026-04-15T11:03:01", "name": "[v2] RISC-V: Make tuple vector not tieable to some modes.", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499968/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223475/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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server2.sourceware.org", "From": "wangzicong <wangzicong@masscore.cn>", "To": "gcc-patches@gcc.gnu.org", "Cc": "rdapp.gcc@gmail.com,\n\tZicong Wang <wangzicong@masscore.cn>", "Subject": "[PATCH v2] RISC-V: Make tuple vector not tieable to some modes.", "Date": "Wed, 15 Apr 2026 19:03:01 +0800", "Message-Id": "<20260415110301.1701251-1-wangzicong@masscore.cn>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "rQCowADH39ZncN9pThYWDg--.21352S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxZrW7CrW7AFWfGFWfJF4ktFb_yoW5AFyfpa\n 1UGws2kF18AFZ7JF1ftFy7JwsxuaykGr1rWw1fZr47Ca9aqrWjqa4qqw43WFy7GF45Wr1a\n 9r17CF1Y9wn8X3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUyl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j\n 6r4UM28EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr\n 0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj\n 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr\n 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAK\n I48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7\n xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xII\n jxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw2\n 0EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x02\n 67AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU0iiSUUUUU", "X-Originating-IP": "[118.112.177.130]", "X-CM-SenderInfo": "pzdqw6xlfr0w46pd22pfruvhdfq/", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Zicong Wang <wangzicong@masscore.cn>\n\nThis patch makes riscv tuple modes not tieable to non-tuple modes. Without \nthis patch some unnecessary type conversions may occur, especially when zvl \nis specified. \nE.g. RVVMF2x4HI and RVVM2DI are tieable in gcc trunk, and when extracting \nan inner vector mode RVVMF2HI from RVVMF2x4HI and zvl is specified, it will \nbe converted to DI, which is not expected.\n\n PR target/124448\n\ngcc/ChangeLog:\n\n * config/riscv/riscv.cc (riscv_modes_tieable_p): Make tuple modes \n not tieable to non-tuple modes.\n\ngcc/testsuite/ChangeLog:\n\n * gcc.target/riscv/rvv/autovec/pr124448.c: New test.\n\nSigned-off-by: Zicong Wang <wangzicong@masscore.cn>\n\n---\n gcc/config/riscv/riscv.cc | 7 ++++\n .../gcc.target/riscv/rvv/autovec/pr124448.c | 36 +++++++++++++++++++\n 2 files changed, 43 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c", "diff": "diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex a6106547757..1d3a6b3338b 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -10897,6 +10897,13 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n E.g. V2SI and DI are not tieable. */\n if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n return false;\n+\n+ /* We also don't allow tuple modes to be tied to non-tuple\n+ modes to avoid unnecessary type conversions.\n+ E.g. RVVMF2x4HI and RVVM2DI are not tieable. */\n+ if (riscv_tuple_mode_p (mode1) != riscv_tuple_mode_p (mode2))\n+ return false;\n+\n return (mode1 == mode2\n \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n \t && GET_MODE_CLASS (mode2) == MODE_FLOAT));\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\nnew file mode 100644\nindex 00000000000..a89448fb81b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n@@ -0,0 +1,36 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fdump-rtl-vregs\" } */\n+\n+typedef short int16_t;\n+\n+void dct( int16_t d[16], int16_t dct[16] )\n+{\n+ int16_t tmp[16];\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = d[i*4+0] + d[i*4+3];\n+ int s12 = d[i*4+1] + d[i*4+2];\n+ int d03 = d[i*4+0] - d[i*4+3];\n+ int d12 = d[i*4+1] - d[i*4+2];\n+ tmp[0*4+i] = s03 + s12;\n+ tmp[1*4+i] = 2*d03 + d12;\n+ tmp[2*4+i] = s03 - s12;\n+ tmp[3*4+i] = d03 - 2*d12;\n+ }\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = tmp[i*4+0] + tmp[i*4+3];\n+ int s12 = tmp[i*4+1] + tmp[i*4+2];\n+ int d03 = tmp[i*4+0] - tmp[i*4+3];\n+ int d12 = tmp[i*4+1] - tmp[i*4+2];\n+\n+ dct[i*4+0] = s03 + s12;\n+ dct[i*4+1] = 2*d03 + d12;\n+ dct[i*4+2] = s03 - s12;\n+ dct[i*4+3] = d03 - 2*d12;\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n+/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n+/* { dg-final { scan-rtl-dump-not {\\(subreg:RVVM2DI \\(reg:RVVMF2x4HI} \"vregs\" } } */\n", "prefixes": [ "v2" ] }