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GET /api/1.2/patches/2204652/?format=api
{ "id": 2204652, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2204652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260304034354.2871-1-dinesh.maniyam@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260304034354.2871-1-dinesh.maniyam@altera.com>", "list_archive_url": null, "date": "2026-03-04T03:43:54", "name": "arm: socfpga: Ensure FPGA in user mode before enabling the bridges", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "2eb3a960343aa20b9ff54cdde9330a1da719ca04", "submitter": { "id": 90303, "url": "http://patchwork.ozlabs.org/api/1.2/people/90303/?format=api", "name": "Maniyam, Dinesh", "email": "dinesh.maniyam@altera.com" }, "delegate": { "id": 152680, "url": "http://patchwork.ozlabs.org/api/1.2/users/152680/?format=api", "username": "TIENFONG", "first_name": "TIEN FONG", "last_name": "CHEE", "email": "tien.fong.chee@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260304034354.2871-1-dinesh.maniyam@altera.com/mbox/", "series": [ { "id": 494296, "url": "http://patchwork.ozlabs.org/api/1.2/series/494296/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=494296", "date": "2026-03-04T03:43:54", "name": "arm: socfpga: Ensure FPGA in user mode before enabling the bridges", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/494296/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2204652/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2204652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", 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b=MxGuK8aPmjJWljwLhHmJyklHaOoyDXHrTD8ywF1+5qOmzhnWiwVwvFe8P/fGXat7rGWLNswe6x5z4LShYD5HzhZehCP8XN7z5K4Wu5aO5dzheDK4tlh2FLqu/oTEJmOygWCoetfZNG56RKiV+JaraI+ZQMruvc5XGBjV1Q3dmj26yaP3KybROyfkYalyYbAAF7Bt0G7GRJYcHYQzvwGOMAa6KAgZ0OeeG5/vlMXb7P/DLM2mDXo24ITndiYzro++H4pa3twh0Teb+cOopEVWoF9esTmMCeewPPgY/tGNQtnFPDJN6j/ieNNrK9Akbs9dNpRCJrLdkGi8r/PwD4lu7A==", "From": "dinesh.maniyam@altera.com", "To": "u-boot@lists.denx.de", "Cc": "Marek Vasut <marex@denx.de>,\n Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,\n Tom Rini <trini@konsulko.com>, Michal Simek <michal.simek@amd.com>,\n Tien Fong <tien.fong.chee@altera.com>,\n Kok Kiang <kok.kiang.hea@altera.com>, Dinesh <dinesh.maniyam@altera.com>,\n Boon Khai <boon.khai.ng@altera.com>,\n Alif <alif.zakuan.yuslaimi@altera.com>,\n Tien Fong Chee <tien.fong.chee@intel.com>", "Subject": "[PATCH] arm: socfpga: Ensure FPGA in user mode before enabling the\n bridges", "Date": "Wed, 4 Mar 2026 11:43:54 +0800", "Message-ID": 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"<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Dinesh Maniyam <dinesh.maniyam@altera.com>\n\nUnexpected behavior and error can occur if FPGA is accessed in unknown\nstate.Always checking with FPGA in user mode is required to ensure\nsystem stability.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\nSigned-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>\n---\n arch/arm/mach-socfpga/misc_arria10.c | 13 ++++++++++---\n 1 file changed, 10 insertions(+), 3 deletions(-)", "diff": "diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c\nindex 7e0f3875b7c..6b25ab917ca 100644\n--- a/arch/arm/mach-socfpga/misc_arria10.c\n+++ b/arch/arm/mach-socfpga/misc_arria10.c\n@@ -13,6 +13,7 @@\n #include <ns16550.h>\n #include <spi_flash.h>\n #include <watchdog.h>\n+#include <asm/arch/fpga_manager.h>\n #include <asm/arch/misc.h>\n #include <asm/arch/pinmux.h>\n #include <asm/arch/reset_manager.h>\n@@ -126,10 +127,16 @@ int print_cpuinfo(void)\n \n void do_bridge_reset(int enable, unsigned int mask)\n {\n-\tif (enable)\n-\t\tsocfpga_reset_deassert_bridges_handoff();\n-\telse\n+\tif (enable) {\n+\t\tif (is_fpgamgr_user_mode()) {\n+\t\t\tsocfpga_reset_deassert_bridges_handoff();\n+\t\t} else {\n+\t\t\tputs(\"Bridges: Failed to enable because FPGA is not \");\n+\t\t\tputs(\"in user mode\\n\");\n+\t\t}\n+\t} else {\n \t\tsocfpga_bridges_reset();\n+\t}\n }\n \n /*\n", "prefixes": [] }