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GET /api/1.1/patches/2232517/?format=api
{ "id": 2232517, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232517/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-5-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-5-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:38", "name": "[v5,05/15] target/arm: emit tag check when MTX without TBI", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7801a316ba3e20c2d9c0780b3a37bd2834a68a20", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-5-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232517/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232517/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=shahjymQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-5-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=9819;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=v+7vHbPDhPrfGr1GkwHZhaMnYJPZJitNx9Vnfe3PjoY=;\n b=NaZtGl0Pm9liG5JteV5wlh/AKOs0wj6oRzIC1Jm7LHmQfHaLsFePB5pbs5z9Zx+mjeuMTz/lY\n 0nS4hV0msbODdrm20ZxRAZi0KfZ6g3CQfChqhawyTQl/7UwyU2wNoDX", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::831;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x831.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Previously, the TBI bit was used to mediate whether tag checks happened.\nWith MTE4, if the MTX bits are enabled, then tag checking happens even\nif TBI is disabled. See AccessIsTagChecked.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\n---\n target/arm/helper.c | 10 ++++++++++\n target/arm/internals.h | 13 ++++++++-----\n target/arm/tcg/helper-a64.c | 7 ++++---\n target/arm/tcg/hflags.c | 9 +++++----\n target/arm/tcg/mte_helper.c | 9 ++++++---\n target/arm/tcg/sme_helper.c | 4 ++--\n target/arm/tcg/sve_helper.c | 6 +++---\n 7 files changed, 38 insertions(+), 20 deletions(-)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex ddf44f4306..18352bd186 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -9559,6 +9559,16 @@ uint64_t arm_sctlr(CPUARMState *env, int el)\n return env->cp15.sctlr_el[el];\n }\n \n+int aa64_va_parameter_mtx(uint64_t tcr, ARMMMUIdx mmu_idx)\n+{\n+ if (regime_has_2_ranges(mmu_idx)) {\n+ return extract64(tcr, 60, 2);\n+ } else {\n+ /* Replicate the single MTX bit so we always have 2 bits. */\n+ return extract64(tcr, 33, 1) * 3;\n+ }\n+}\n+\n int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)\n {\n if (regime_has_2_ranges(mmu_idx)) {\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex a632584a4e..6df2c547c5 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1422,6 +1422,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,\n ARMMMUIdx mmu_idx, bool data,\n bool el1_is_aa32);\n \n+int aa64_va_parameter_mtx(uint64_t tcr, ARMMMUIdx mmu_idx);\n int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);\n int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);\n int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);\n@@ -1557,7 +1558,8 @@ FIELD(MTEDESC, TBI, 4, 2)\n FIELD(MTEDESC, TCMA, 6, 2)\n FIELD(MTEDESC, WRITE, 8, 1)\n FIELD(MTEDESC, ALIGN, 9, 3)\n-FIELD(MTEDESC, SIZEM1, 12, 32 - 12) /* size - 1 */\n+FIELD(MTEDESC, MTX, 12, 2)\n+FIELD(MTEDESC, SIZEM1, 14, 32 - 14) /* size - 1 */\n \n bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);\n uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);\n@@ -1627,10 +1629,11 @@ static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)\n return deposit64(ptr, 56, 4, rtag);\n }\n \n-/* Return true if tbi bits mean that the access is checked. */\n-static inline bool tbi_check(uint32_t desc, int bit55)\n+/* Return true if tbi or mtx bits mean that the access is tag checked. */\n+static inline bool tbi_or_mtx_check(uint32_t desc, int bit55)\n {\n- return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;\n+ uint32_t mask = (1u << R_MTEDESC_TBI_SHIFT) | (1u << R_MTEDESC_MTX_SHIFT);\n+ return desc & (mask << bit55);\n }\n \n /* Return true if tcma bits mean that the access is unchecked. */\n@@ -1664,7 +1667,7 @@ static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)\n {\n #ifdef CONFIG_USER_ONLY\n int64_t clean_ptr = sextract64(ptr, 0, 56);\n- if (tbi_check(desc, clean_ptr < 0)) {\n+ if (tbi_or_mtx_check(desc, clean_ptr < 0)) {\n ptr = clean_ptr;\n }\n #endif\ndiff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c\nindex dd1f9c6dc6..9eef2f7e6d 100644\n--- a/target/arm/tcg/helper-a64.c\n+++ b/target/arm/tcg/helper-a64.c\n@@ -1054,7 +1054,7 @@ static int mops_sizereg(uint32_t syndrome)\n }\n \n /*\n- * Return true if TCMA and TBI bits mean we need to do MTE checks.\n+ * Return true if the TCMA, TBI, and MTX bits mean we need to do MTE checks.\n * We only need to do this once per MOPS insn, not for every page.\n */\n static bool mte_checks_needed(uint64_t ptr, uint32_t desc)\n@@ -1062,12 +1062,13 @@ static bool mte_checks_needed(uint64_t ptr, uint32_t desc)\n int bit55 = extract64(ptr, 55, 1);\n \n /*\n- * Note that tbi_check() returns true for \"access checked\" but\n+ * Note that tbi_or_mtx_check() return true for \"access checked\", but\n * tcma_check() returns true for \"access unchecked\".\n */\n- if (!tbi_check(desc, bit55)) {\n+ if (!tbi_or_mtx_check(desc, bit55)) {\n return false;\n }\n+\n return !tcma_check(desc, bit55, allocation_tag_from_addr(ptr));\n }\n \ndiff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c\nindex 75c55b1a6d..e753124c4c 100644\n--- a/target/arm/tcg/hflags.c\n+++ b/target/arm/tcg/hflags.c\n@@ -245,13 +245,14 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n uint64_t tcr = regime_tcr(env, mmu_idx);\n uint64_t hcr = arm_hcr_el2_eff(env);\n uint64_t sctlr;\n- int tbii, tbid;\n+ int tbii, tbid, mtx;\n \n DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);\n \n /* Get control bits for tagged addresses. */\n tbid = aa64_va_parameter_tbi(tcr, mmu_idx);\n tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);\n+ mtx = aa64_va_parameter_mtx(tcr, mmu_idx);\n \n DP_TBFLAG_A64(flags, TBII, tbii);\n DP_TBFLAG_A64(flags, TBID, tbid);\n@@ -403,14 +404,14 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n /*\n * Set MTE_ACTIVE if any access may be Checked, and leave clear\n * if all accesses must be Unchecked:\n- * 1) If no TBI, then there are no tags in the address to check,\n+ * 1) If TBI and MTX are both unset, accesses are Unchecked.\n * 2) If Tag Check Override, then all accesses are Unchecked,\n * 3) If Tag Check Fail == 0, then Checked access have no effect,\n * 4) If no Allocation Tag Access, then all accesses are Unchecked.\n */\n if (allocation_tag_access_enabled(env, el, sctlr)) {\n DP_TBFLAG_A64(flags, ATA, 1);\n- if (tbid\n+ if ((tbid || mtx)\n && !(env->pstate & PSTATE_TCO)\n && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {\n DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);\n@@ -436,7 +437,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n }\n /* And again for unprivileged accesses, if required. */\n if (EX_TBFLAG_A64(flags, UNPRIV)\n- && tbid\n+ && (tbid || mtx)\n && !(env->pstate & PSTATE_TCO)\n && (sctlr & SCTLR_TCF0)\n && allocation_tag_access_enabled(env, 0, sctlr)) {\ndiff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c\nindex bf35dc10ce..61cdf92c54 100644\n--- a/target/arm/tcg/mte_helper.c\n+++ b/target/arm/tcg/mte_helper.c\n@@ -823,8 +823,11 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr,\n bit55 = extract64(ptr, 55, 1);\n *fault = ptr;\n \n- /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */\n- if (unlikely(!tbi_check(desc, bit55))) {\n+ /*\n+ * If TBI and MTX are disabled, the access is unchecked, and ptr is not\n+ * dirty.\n+ */\n+ if (unlikely(!tbi_or_mtx_check(desc, bit55))) {\n return -1;\n }\n \n@@ -965,7 +968,7 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)\n bit55 = extract64(ptr, 55, 1);\n \n /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */\n- if (unlikely(!tbi_check(desc, bit55))) {\n+ if (unlikely(!tbi_or_mtx_check(desc, bit55))) {\n return ptr;\n }\n \ndiff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c\nindex ab5999c592..68684d1f87 100644\n--- a/target/arm/tcg/sme_helper.c\n+++ b/target/arm/tcg/sme_helper.c\n@@ -680,7 +680,7 @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,\n int bit55 = extract64(addr, 55, 1);\n \n /* Perform gross MTE suppression early. */\n- if (!tbi_check(mtedesc, bit55) ||\n+ if (!tbi_or_mtx_check(mtedesc, bit55) ||\n tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {\n mtedesc = 0;\n }\n@@ -862,7 +862,7 @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,\n int bit55 = extract64(addr, 55, 1);\n \n /* Perform gross MTE suppression early. */\n- if (!tbi_check(mtedesc, bit55) ||\n+ if (!tbi_or_mtx_check(mtedesc, bit55) ||\n tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {\n mtedesc = 0;\n }\ndiff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c\nindex 062d8881bd..c5e6d58a7e 100644\n--- a/target/arm/tcg/sve_helper.c\n+++ b/target/arm/tcg/sve_helper.c\n@@ -6375,7 +6375,7 @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,\n int bit55 = extract64(addr, 55, 1);\n \n /* Perform gross MTE suppression early. */\n- if (!tbi_check(mtedesc, bit55) ||\n+ if (!tbi_or_mtx_check(mtedesc, bit55) ||\n tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {\n mtedesc = 0;\n }\n@@ -6737,7 +6737,7 @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,\n int bit55 = extract64(addr, 55, 1);\n \n /* Perform gross MTE suppression early. */\n- if (!tbi_check(mtedesc, bit55) ||\n+ if (!tbi_or_mtx_check(mtedesc, bit55) ||\n tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {\n mtedesc = 0;\n }\n@@ -6992,7 +6992,7 @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,\n int bit55 = extract64(addr, 55, 1);\n \n /* Perform gross MTE suppression early. */\n- if (!tbi_check(mtedesc, bit55) ||\n+ if (!tbi_or_mtx_check(mtedesc, bit55) ||\n tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {\n mtedesc = 0;\n }\n", "prefixes": [ "v5", "05/15" ] }