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GET /api/1.1/patches/2232311/?format=api
{ "id": 2232311, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232311/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/87qznrxxzx.fsf@googlemail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<87qznrxxzx.fsf@googlemail.com>", "date": "2026-05-04T10:36:18", "name": "aarch64: Fix SVE vec_perm for VL2048 VNx16QI", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b8a2207f440a9652bcc8056d19eac0f4cdbd49bf", "submitter": { "id": 4363, "url": "http://patchwork.ozlabs.org/api/1.1/people/4363/?format=api", "name": "Richard Sandiford", "email": "rdsandiford@googlemail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/87qznrxxzx.fsf@googlemail.com/mbox/", "series": [ { "id": 502641, "url": "http://patchwork.ozlabs.org/api/1.1/series/502641/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502641", "date": "2026-05-04T10:36:18", "name": "aarch64: Fix SVE vec_perm for VL2048 VNx16QI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502641/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232311/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232311/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=googlemail.com header.i=@googlemail.com\n header.a=rsa-sha256 header.s=20251104 header.b=iTOiP3kZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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There are two\nexpansions: one for when the selector is known to refer to only the\nfirst vector, and one for the general case.\n\nThe first expansion uses a single TBL whereas the fallback uses a\nfive-instruction sequence that includes a SUB of nunits and two TBLs.\n\nNormally the first expansion is purely an optimisation. However,\nin the specific case of a VL2048 permutation of bytes, the first\nform is needed for correctness, since the SUB of nunits (256)\nwould be truncated to a SUB of zero.\n\nFor example, in:\n\n svint8_t f(svint8_t x, svint8_t y, svint8_t z) {\n return __builtin_shuffle(x, y, z);\n }\n\n\"z\" can only select from \"x\" for VL2048. The testcase previously\ngenerated:\n\n tbl z0.b, {z0.b}, z2.b\n tbl z1.b, {z1.b}, z2.b\n orr z0.d, z0.d, z1.d\n ret\n\nwhere the SUB is optimised away. This sequence is equivalent to:\n\n return __builtin_shuffle(x | y, x | y, z);\n\neven though \"y\" should be entirely ignored.\n\nI used \"<= nunits - 1U\" rather than \"< nunits\" to match the existing\ncheck and as a hopefully natural way of making the rhs unsigned.\n\nBootstrapped & regression-tested on aarch64-linux-gnu. OK to install?\n\nRichard\n\n\ngcc/\n\t* config/aarch64/aarch64.cc (aarch64_expand_sve_vec_perm): Check\n\twhether all indices of a variable selector refer to the first\n\tvalues vector.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/sve/vec_perm_2.c: New test.\n\t* gcc.target/aarch64/sve/vec_perm_3.c: Likewise.\n---\n gcc/config/aarch64/aarch64.cc | 5 ++--\n .../gcc.target/aarch64/sve/vec_perm_2.c | 26 +++++++++++++++++++\n .../gcc.target/aarch64/sve/vec_perm_3.c | 22 ++++++++++++++++\n 3 files changed, 51 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 62194b96450..e2fa6289e9b 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -27389,8 +27389,9 @@ aarch64_expand_sve_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)\n rtx sel_reg = force_reg (sel_mode, sel);\n \n /* Check if the sel only references the first values vector. */\n- if (CONST_VECTOR_P (sel)\n- && aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1))\n+ if (GET_MODE_MASK (GET_MODE_INNER (sel_mode)) <= nunits - 1U\n+ || (CONST_VECTOR_P (sel)\n+\t && aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1)))\n {\n emit_unspec2 (target, UNSPEC_TBL, op0, sel_reg);\n return;\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\nnew file mode 100644\nindex 00000000000..42fa5f1f97f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n@@ -0,0 +1,26 @@\n+/* { dg-options \"-O2 -msve-vector-bits=2048\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" } } */\n+\n+#include <arm_sve.h>\n+\n+/*\n+** test8:\n+**\ttbl\tz0\\.b, {z0\\.b}, z2\\.b\n+**\tret\n+*/\n+svint8_t\n+test8 (svint8_t x, svint8_t y, svint8_t z)\n+{\n+ return __builtin_shuffle (x, y, z);\n+}\n+\n+svint16_t\n+test16 (svint16_t x, svint16_t y, svint16_t z)\n+{\n+ return __builtin_shuffle (x, y, z);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tand\\t} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tsub\\t} 1 } } */\n+/* { dg-final { scan-assembler-times {\\ttbl\\t} 3 } } */\n+/* { dg-final { scan-assembler-times {\\torr\\t} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\nnew file mode 100644\nindex 00000000000..2fead0890c4\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\n@@ -0,0 +1,22 @@\n+/* { dg-options \"-O2 -msve-vector-bits=1024\" } */\n+\n+#include <arm_sve.h>\n+\n+svint8_t\n+test8 (svint8_t x, svint8_t y, svint8_t z)\n+{\n+ return __builtin_shuffle (x, y, z);\n+}\n+\n+svint16_t\n+test16 (svint16_t x, svint16_t y, svint16_t z)\n+{\n+ return __builtin_shuffle (x, y, z);\n+}\n+\n+/* test8 does not need an AND. In principle, its subtraction of 128\n+ from the selector can be rendered as a SUB, an ADD, or an EOR. */\n+/* { dg-final { scan-assembler-times {\\tand\\t} 1 } } */\n+/* { dg-final { scan-assembler-times {\\t(?:sub|add|eor)\\t} 2 } } */\n+/* { dg-final { scan-assembler-times {\\ttbl\\t} 4 } } */\n+/* { dg-final { scan-assembler-times {\\torr\\t} 2 } } */\n", "prefixes": [] }