[{"id":3685997,"web_url":"http://patchwork.ozlabs.org/comment/3685997/","msgid":"","list_archive_url":null,"date":"2026-05-04T19:50:27","subject":"RE: [PATCH] aarch64: Fix SVE vec_perm for VL2048 VNx16QI","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"> -----Original Message-----\n> From: Richard Sandiford \n> Sent: 04 May 2026 11:36\n> To: gcc-patches@gcc.gnu.org\n> Cc: Tamar Christina \n> Subject: [PATCH] aarch64: Fix SVE vec_perm for VL2048 VNx16QI\n> \n> SVE's vec_perm pattern is restricted to constant VLs. There are two\n> expansions: one for when the selector is known to refer to only the\n> first vector, and one for the general case.\n> \n> The first expansion uses a single TBL whereas the fallback uses a\n> five-instruction sequence that includes a SUB of nunits and two TBLs.\n> \n> Normally the first expansion is purely an optimisation. However,\n> in the specific case of a VL2048 permutation of bytes, the first\n> form is needed for correctness, since the SUB of nunits (256)\n> would be truncated to a SUB of zero.\n> \n> For example, in:\n> \n> svint8_t f(svint8_t x, svint8_t y, svint8_t z) {\n> return __builtin_shuffle(x, y, z);\n> }\n> \n> \"z\" can only select from \"x\" for VL2048. The testcase previously\n> generated:\n> \n> tbl z0.b, {z0.b}, z2.b\n> tbl z1.b, {z1.b}, z2.b\n> orr z0.d, z0.d, z1.d\n> ret\n> \n> where the SUB is optimised away. This sequence is equivalent to:\n> \n> return __builtin_shuffle(x | y, x | y, z);\n> \n> even though \"y\" should be entirely ignored.\n> \n> I used \"<= nunits - 1U\" rather than \"< nunits\" to match the existing\n> check and as a hopefully natural way of making the rhs unsigned.\n> \n> Bootstrapped & regression-tested on aarch64-linux-gnu. OK to install?\n> \n\nOK, thanks!\n\nSorry for the delay, bank holiday :)\n\nThanks,\nTamar\n\n> Richard\n> \n> \n> gcc/\n> \t* config/aarch64/aarch64.cc (aarch64_expand_sve_vec_perm):\n> Check\n> \twhether all indices of a variable selector refer to the first\n> \tvalues vector.\n> \n> gcc/testsuite/\n> \t* gcc.target/aarch64/sve/vec_perm_2.c: New test.\n> \t* gcc.target/aarch64/sve/vec_perm_3.c: Likewise.\n> ---\n> gcc/config/aarch64/aarch64.cc | 5 ++--\n> .../gcc.target/aarch64/sve/vec_perm_2.c | 26 +++++++++++++++++++\n> .../gcc.target/aarch64/sve/vec_perm_3.c | 22 ++++++++++++++++\n> 3 files changed, 51 insertions(+), 2 deletions(-)\n> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n> create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\n> \n> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\n> index 62194b96450..e2fa6289e9b 100644\n> --- a/gcc/config/aarch64/aarch64.cc\n> +++ b/gcc/config/aarch64/aarch64.cc\n> @@ -27389,8 +27389,9 @@ aarch64_expand_sve_vec_perm (rtx target, rtx\n> op0, rtx op1, rtx sel)\n> rtx sel_reg = force_reg (sel_mode, sel);\n> \n> /* Check if the sel only references the first values vector. */\n> - if (CONST_VECTOR_P (sel)\n> - && aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1))\n> + if (GET_MODE_MASK (GET_MODE_INNER (sel_mode)) <= nunits - 1U\n> + || (CONST_VECTOR_P (sel)\n> +\t && aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1)))\n> {\n> emit_unspec2 (target, UNSPEC_TBL, op0, sel_reg);\n> return;\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n> b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n> new file mode 100644\n> index 00000000000..42fa5f1f97f\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_2.c\n> @@ -0,0 +1,26 @@\n> +/* { dg-options \"-O2 -msve-vector-bits=2048\" } */\n> +/* { dg-final { check-function-bodies \"**\" \"\" } } */\n> +\n> +#include \n> +\n> +/*\n> +** test8:\n> +**\ttbl\tz0\\.b, {z0\\.b}, z2\\.b\n> +**\tret\n> +*/\n> +svint8_t\n> +test8 (svint8_t x, svint8_t y, svint8_t z)\n> +{\n> + return __builtin_shuffle (x, y, z);\n> +}\n> +\n> +svint16_t\n> +test16 (svint16_t x, svint16_t y, svint16_t z)\n> +{\n> + return __builtin_shuffle (x, y, z);\n> +}\n> +\n> +/* { dg-final { scan-assembler-times {\\tand\\t} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\tsub\\t} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\ttbl\\t} 3 } } */\n> +/* { dg-final { scan-assembler-times {\\torr\\t} 1 } } */\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\n> b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\n> new file mode 100644\n> index 00000000000..2fead0890c4\n> --- /dev/null\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/vec_perm_3.c\n> @@ -0,0 +1,22 @@\n> +/* { dg-options \"-O2 -msve-vector-bits=1024\" } */\n> +\n> +#include \n> +\n> +svint8_t\n> +test8 (svint8_t x, svint8_t y, svint8_t z)\n> +{\n> + return __builtin_shuffle (x, y, z);\n> +}\n> +\n> +svint16_t\n> +test16 (svint16_t x, svint16_t y, svint16_t z)\n> +{\n> + return __builtin_shuffle (x, y, z);\n> +}\n> +\n> +/* test8 does not need an AND. In principle, its subtraction of 128\n> + from the selector can be rendered as a SUB, an ADD, or an EOR. */\n> +/* { dg-final { scan-assembler-times {\\tand\\t} 1 } } */\n> +/* { dg-final { scan-assembler-times {\\t(?:sub|add|eor)\\t} 2 } } */\n> +/* { dg-final { scan-assembler-times {\\ttbl\\t} 4 } } */\n> +/* { dg-final { scan-assembler-times {\\torr\\t} 2 } } */\n> --\n> 2.54.0","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=cGWjM+Em;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=cGWjM+Em;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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