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GET /api/1.1/patches/2231716/?format=api
{ "id": 2231716, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231716/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-24-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260501101505.3485916-24-peter.maydell@linaro.org>", "date": "2026-05-01T10:15:00", "name": "[PULL,23/28] hvf: sync registers used at EL2", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c7448e9dbc412331e9abde48421463e161804053", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-24-peter.maydell@linaro.org/mbox/", "series": [ { "id": 502437, "url": "http://patchwork.ozlabs.org/api/1.1/series/502437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502437", "date": "2026-05-01T10:14:41", "name": "[PULL,01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231716/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231716/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wtNHsfAi;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6RmP631Xz1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 01 May 2026 20:17:09 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIkuN-00045n-J6; Fri, 01 May 2026 06:15:43 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuJ-00042j-7d\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:39 -0400", "from mail-wm1-x334.google.com ([2a00:1450:4864:20::334])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuH-0000Dk-0j\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:38 -0400", "by mail-wm1-x334.google.com with SMTP id\n 5b1f17b1804b1-488b8bc6bc9so11355755e9.3\n for <qemu-devel@nongnu.org>; Fri, 01 May 2026 03:15:36 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-48a8fede418sm12863335e9.6.2026.05.01.03.15.34\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 01 May 2026 03:15:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777630535; x=1778235335; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=EaU21xUEzEpe3YMvUriI5xAjjTThJB/xFqiCk8ad028=;\n b=wtNHsfAiVNyPha90wLAArAj7hHI5J2WotCETONzKA3Tj9OtXEniefYUt8wC+wuS0q8\n 7YCuNiC4vLxHzp/iLEWEbYkZQTmG31MX7hDlKLAzk++ZWB7tVYZNoaMcLp6Red2KFkiL\n raSEVH257+as678V34Yxv0+Sgf9vPzuYo6ez7Cvby34ud73U3LZ/u9pzd3MmNsdgO8zq\n lUc3m+StH7JRSURVwbM15xio4BOe2pGZV44Lf+8Zfyb1dNGvNa8Fo20/89gucDeRVvyp\n +PKfSbEZhoP1ACQYLKxrK6/Ev5kK2RsXHO7VrNz4qN29n9Lw5qY2X/EamXrn0id26wqO\n 9lcA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777630535; x=1778235335;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=EaU21xUEzEpe3YMvUriI5xAjjTThJB/xFqiCk8ad028=;\n b=B08f6qnL5kEDkZJF/1VhzpPEz+oLI9+gIIaTFtK9t9IT89VZ9z/1ZD1ID6COwzQjQu\n nNfaY3qwRjPmOYU70suDmUZQhEo6gaX6GbSN+mrNXcxv1WBdwppngR4Z/faI8X/b/8jF\n bkcw21phCgsDdEAReB1AOTVTWWf3q1j0SGz62tRetS/eCbUS2QDvIDPETkhpqxMf3Ina\n cushsDIqAeInZNw6Ykpll0Q8mFEQSOJPCDQ8y8cIrmQfuY5HAe9DI9jvnRk+h8br8sXH\n uZjGR3Lvc8+k6a8QNcWG4ybfQLvFKYypKrHxN1zFiowD1VphDfvmIa29+lVZMPXKRgMC\n 788Q==", "X-Gm-Message-State": "AOJu0YyLuk1UegzdPN+t42erY9SLaDDtFBhLg6GN7kTkRdjblFWE/mx7\n CqVOpwqDF3oZYA6IfTqfiNt5T6zV4vKz0y56JWxH0yIdNszqgVc9+9xcEwdrmizG4SZEDUoK8CX\n Mjj8s", "X-Gm-Gg": "AeBDieuKNhphSFcYpsJKH6EP6dk5xTzNVJEFxXxXvmZE03kWE9nrmgwYvS4jyevteo8\n qYmmS56jjaeYgW60oCnHJ1poALHsRrqD4HivD1qteY15/A/FQ93nFV6m1B81zXxmGXXNP+Qqm1V\n Vq1GIvokaZh+7wkg/I9LP5ePeuuB3sPadX+6RNgBl5F2e1t2JDCUy4uiva2ZHZ7zEwxhAizxXOj\n VI6wVEDo5nuNZLIEAv684QUE3BdaPG+8gRZPu+LBd4YYXyS4UhwMgmxzA/JTYbKhQu02zf23Kuy\n 3wDaBRDRitVfvWICc1W8cDfjMK/2WzGLspmgqQpsQF5e0RqGMxIsC7wTQ7J61BYy4BzsATKbiS/\n YntdEg58Ol/NeB+1zuHpnbGBCR3i/1RPr9M+5VmPMkFIEbClq3Cvi+5t+MRDhHxNL4RM9zLmoTD\n CXS0vvuVI+YLAtn/Amv+hBJ6PmXmLXDtTpRCxFc4V1z9S/GHNx+zx2g+K+gqykAWvwA9Ee49bW0\n reYmURAcDtINrM31nhnZH4/V62KTVFbnW5wrE+qhQ==", "X-Received": "by 2002:a05:600c:a40e:b0:488:c40b:c8a4 with SMTP id\n 5b1f17b1804b1-48a83f6e2e9mr84215805e9.1.1777630535333;\n Fri, 01 May 2026 03:15:35 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 23/28] hvf: sync registers used at EL2", "Date": "Fri, 1 May 2026 11:15:00 +0100", "Message-ID": "<20260501101505.3485916-24-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "References": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::334;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nWhen starting up the VM at EL2, more sysregs are available. Sync the state of those.\n\nIn addition, sync the state of the EL1 physical timer when the vGIC is used, even\nif running at EL1. However, no OS running at EL1 is expected to use those registers.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-id: 20260429190532.26538-11-mohamed@unpredictable.fr\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/hvf/hvf.c | 61 +++++++++++++++++++++++++++++++++----\n target/arm/hvf/sysreg.c.inc | 44 ++++++++++++++++++++++++++\n 2 files changed, 99 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 38f88c1a80..ecfe06cd8c 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -467,37 +467,75 @@ static const struct hvf_reg_match hvf_sme2_preg_match[] = {\n *\n * SME2 registers are guarded by a runtime availability attribute instead of a\n * compile-time def, so verify those at runtime in hvf_arch_init_vcpu() below.\n+ *\n+ * Nested virt registers are handled via a runtime check, so override the\n+ * guarded availability check done by Clang.\n */\n \n+#pragma clang diagnostic push\n+#pragma clang diagnostic ignored \"-Wunguarded-availability\"\n+\n #define DEF_SYSREG(HVF_ID, ...) \\\n QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n #define DEF_SYSREG_15_02(...)\n \n+#define DEF_SYSREG_EL2(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n+#define DEF_SYSREG_VGIC(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n+#define DEF_SYSREG_VGIC_EL2(HVF_ID, ...) \\\n+ QEMU_BUILD_BUG_ON(HVF_ID != KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n+\n #include \"sysreg.c.inc\"\n \n #undef DEF_SYSREG\n #undef DEF_SYSREG_15_02\n+#undef DEF_SYSREG_EL2\n+#undef DEF_SYSREG_VGIC\n+#undef DEF_SYSREG_VGIC_EL2\n \n-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID,\n+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID},\n #define DEF_SYSREG_15_02(...)\n+#define DEF_SYSREG_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .el2 = true},\n+#define DEF_SYSREG_VGIC(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, .vgic = true},\n+#define DEF_SYSREG_VGIC_EL2(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID, true, true},\n \n-static const hv_sys_reg_t hvf_sreg_list[] = {\n+struct hvf_sreg {\n+ hv_sys_reg_t sreg;\n+ bool vgic;\n+ bool el2;\n+};\n+\n+static struct hvf_sreg hvf_sreg_list[] = {\n #include \"sysreg.c.inc\"\n };\n \n #undef DEF_SYSREG\n #undef DEF_SYSREG_15_02\n+#undef DEF_SYSREG_EL2\n+#undef DEF_SYSREG_VGIC\n+#undef DEF_SYSREG_VGIC_EL2\n+\n+#pragma clang diagnostic pop\n \n #define DEF_SYSREG(...)\n-#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) HVF_ID,\n+#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) {HVF_ID},\n+#define DEF_SYSREG_EL2(...)\n+#define DEF_SYSREG_VGIC(...)\n+#define DEF_SYSREG_VGIC_EL2(...)\n \n API_AVAILABLE(macos(15.2))\n-static const hv_sys_reg_t hvf_sreg_list_sme2[] = {\n+static struct hvf_sreg hvf_sreg_list_sme2[] = {\n #include \"sysreg.c.inc\"\n };\n \n #undef DEF_SYSREG\n #undef DEF_SYSREG_15_02\n+#undef DEF_SYSREG_EL2\n+#undef DEF_SYSREG_VGIC\n+#undef DEF_SYSREG_VGIC_EL2\n \n /*\n * For FEAT_SME2 migration, we need to store PSTATE.{SM,ZA} bits which are\n@@ -1335,6 +1373,9 @@ int hvf_arch_init_vcpu(CPUState *cpu)\n #define DEF_SYSREG_15_02(HVF_ID, ...) \\\n g_assert(HVF_ID == KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS__)));\n #define DEF_SYSREG(...)\n+#define DEF_SYSREG_EL2(...)\n+#define DEF_SYSREG_VGIC(...)\n+#define DEF_SYSREG_VGIC_EL2(...)\n \n #include \"sysreg.c.inc\"\n \n@@ -1362,11 +1403,19 @@ int hvf_arch_init_vcpu(CPUState *cpu)\n \n /* Populate cp list for all known sysregs */\n for (i = 0; i < ARRAY_SIZE(hvf_sreg_list); i++) {\n- hv_sys_reg_t hvf_id = hvf_sreg_list[i];\n+ hv_sys_reg_t hvf_id = hvf_sreg_list[i].sreg;\n uint64_t kvm_id = HVF_TO_KVMID(hvf_id);\n uint32_t key = kvm_to_cpreg_id(kvm_id);\n const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);\n \n+ if (hvf_sreg_list[i].vgic && !hvf_irqchip_in_kernel()) {\n+ continue;\n+ }\n+\n+ if (hvf_sreg_list[i].el2 && !hvf_nested_virt_enabled()) {\n+ continue;\n+ }\n+\n if (ri) {\n assert(!(ri->type & ARM_CP_NO_RAW));\n arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;\n@@ -1375,7 +1424,7 @@ int hvf_arch_init_vcpu(CPUState *cpu)\n if (__builtin_available(macOS 15.2, *)) {\n if (hvf_arm_sme2_supported()) {\n for (i = 0; i < ARRAY_SIZE(hvf_sreg_list_sme2); i++) {\n- hv_sys_reg_t hvf_id = hvf_sreg_list_sme2[i];\n+ hv_sys_reg_t hvf_id = hvf_sreg_list_sme2[i].sreg;\n uint64_t kvm_id = HVF_TO_KVMID(hvf_id);\n uint32_t key = kvm_to_cpreg_id(kvm_id);\n const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);\ndiff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc\nindex 7a2f880f78..c11dbf274e 100644\n--- a/target/arm/hvf/sysreg.c.inc\n+++ b/target/arm/hvf/sysreg.c.inc\n@@ -153,3 +153,47 @@ DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)\n DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)\n DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4)\n DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6)\n+/*\n+ * Block these because of the same issue as virtual counters in\n+ * that caused the revert in 28b0ed32b32c7e5094cf2f1ec9c0645c65fad2aa\n+ *\n+ * DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CTL_EL0, 3, 3, 14, 2, 1)\n+ * DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_CVAL_EL0, 3, 3, 14, 2, 2)\n+ */\n+#ifdef SYNC_NO_RAW_REGS\n+DEF_SYSREG_VGIC(HV_SYS_REG_CNTP_TVAL_EL0, 3, 3, 14, 2, 0)\n+#endif\n+\n+/*\n+ * Also block these because of the same issue as virtual counters in\n+ * that caused the revert in 28b0ed32b32c7e5094cf2f1ec9c0645c65fad2aa\n+ *\n+ * DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CVAL_EL2, 3, 4, 14, 2, 2)\n+ * DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_CTL_EL2, 3, 4, 14, 2, 1)\n+ */\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHCTL_EL2, 3, 4, 14, 1, 0)\n+#ifdef SYNC_NO_RAW_REGS\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTHP_TVAL_EL2, 3, 4, 14, 2, 0)\n+#endif\n+DEF_SYSREG_VGIC_EL2(HV_SYS_REG_CNTVOFF_EL2, 3, 4, 14, 0, 3)\n+\n+DEF_SYSREG_EL2(HV_SYS_REG_CPTR_EL2, 3, 4, 1, 1, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_ELR_EL2, 3, 4, 4, 0, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_ESR_EL2, 3, 4, 5, 2, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_FAR_EL2, 3, 4, 6, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_HCR_EL2, 3, 4, 1, 1, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_HPFAR_EL2, 3, 4, 6, 0, 4)\n+DEF_SYSREG_EL2(HV_SYS_REG_MAIR_EL2, 3, 4, 10, 2, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_MDCR_EL2, 3, 4, 1, 1, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_SCTLR_EL2, 3, 4, 1, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_SPSR_EL2, 3, 4, 4, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_SP_EL2, 3, 6, 4, 1, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_TCR_EL2, 3, 4, 2, 0, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_TPIDR_EL2, 3, 4, 13, 0, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_TTBR0_EL2, 3, 4, 2, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_TTBR1_EL2, 3, 4, 2, 0, 1)\n+DEF_SYSREG_EL2(HV_SYS_REG_VBAR_EL2, 3, 4, 12, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_VMPIDR_EL2, 3, 4, 0, 0, 5)\n+DEF_SYSREG_EL2(HV_SYS_REG_VPIDR_EL2, 3, 4, 0, 0, 0)\n+DEF_SYSREG_EL2(HV_SYS_REG_VTCR_EL2, 3, 4, 2, 1, 2)\n+DEF_SYSREG_EL2(HV_SYS_REG_VTTBR_EL2, 3, 4, 2, 1, 0)\n", "prefixes": [ "PULL", "23/28" ] }