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GET /api/1.1/patches/2231703/?format=api
{ "id": 2231703, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231703/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/ad077ef9-38d5-47aa-b79f-58f4d0ad5b55@126.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<ad077ef9-38d5-47aa-b79f-58f4d0ad5b55@126.com>", "date": "2026-05-01T08:02:04", "name": "i386: Adjust some c86-4g*.md modeling to reduce build time", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "928181c927ba50829f37bdd1a30079f65583ab45", "submitter": { "id": 93285, "url": "http://patchwork.ozlabs.org/api/1.1/people/93285/?format=api", "name": "Kewen Lin", "email": "linkw_gcc@126.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/ad077ef9-38d5-47aa-b79f-58f4d0ad5b55@126.com/mbox/", "series": [ { "id": 502432, "url": "http://patchwork.ozlabs.org/api/1.1/series/502432/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502432", "date": "2026-05-01T08:02:04", "name": "i386: Adjust some c86-4g*.md modeling to reduce build time", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502432/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231703/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231703/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=126.com header.i=@126.com header.a=rsa-sha256\n header.s=s110527 header.b=ZyFt1EtG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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s=key;\n t=1777622574; c=relaxed/simple;\n bh=qUuv/1ko3KZ1kLkPTHu7OwBAx20wpio8JUcxx72fhNs=;\n h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From;\n b=m+d1Hz3yYrqV+ImA7daWLl+Rl3vEw7v4mCl3YjsdT+ItrTK2K7lMzTX/Rda1HChykEJ2aVTxURVM+3L0Yi8BogVS+b2Nw9Fa8RZUXZxfktgsVaQfE8782wotAqsN/IhlsZMmdDfLSYwxMVgs6OE+R0w4VmRnESeb++k/qPFC3Po=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com;\n s=s110527; h=Message-ID:Date:MIME-Version:Subject:To:From:\n Content-Type; bh=VLp7yZ+M8+kJFK5Fed+vk4F/mrze+uZGnW9nfWmJH/g=;\n b=ZyFt1EtGumANMswDaf0FhWcFWl5qezKGsxP/AmszJsZx5cbw55jx85dRduboS2\n zoZaLTv1dIoyiVHdrAXrn8yP5TYHK/FFhsjrkET0u+AuWbfL9eR3bvEerHXJi/qH\n f8FPn2RWE3KuJ0Se6QBp9qWJok87OX8ndl1dm4bTZjvuU=", "Message-ID": "<ad077ef9-38d5-47aa-b79f-58f4d0ad5b55@126.com>", "Date": "Fri, 1 May 2026 16:02:04 +0800", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Subject": "[PATCH] i386: Adjust some c86-4g*.md modeling to reduce build time", "To": "Uros Bizjak <ubizjak@gmail.com>, Sam James <sam@gentoo.org>", "Cc": "Richard Biener <richard.guenther@gmail.com>, \"H.J. Lu\"\n <hjl.tools@gmail.com>, Rainer Orth <ro@cebitec.uni-bielefeld.de>,\n Kewen Lin <linkewen@hygon.cn>,\n \"gcc-patches@gcc.gnu.org\" <gcc-patches@gcc.gnu.org>, Liulxx\n <liulxx@hygon.cn>, Qingkuan Lai <laiqingkuan@hygon.cn>,\n Feng Xue <xuefeng@hygon.cn>, \"hubicka@ucw.cz\" <hubicka@ucw.cz>,\n \"hongtao.liu@intel.com\" <hongtao.liu@intel.com>,\n Alexander Monakov <amonakov@ispras.ru>, Jakub Jelinek <jakub@redhat.com>", "References": "<387794d9-199a-4373-97be-5e70e772e014@hygon.cn>\n <CAFULd4brt7kwJ7PRm0NjajD0jO63wRV+kdoo9rRorQvTYV8sfg@mail.gmail.com>\n <a784563f-82e0-4de3-a2a9-4e9123e61125@hygon.cn>\n <CAFULd4aNo_pazdW-pzbQPnbtexqBYtnOf5HRsaQSMvj+7NgTOA@mail.gmail.com>\n <yddse8d7958.fsf@CeBiTec.Uni-Bielefeld.DE>\n <CAMe9rOq7ghnNOK-TRrrWJSrZXUurxN1nVMGQO4Rq4fVFr--Vfw@mail.gmail.com>\n <9e20997c-d94e-4115-b0bc-72c5c0744542@126.com>\n <CAFiYyc2y6J__zNnefUBLYz-XB7rxLRgSSrdFYxuUTN9PeF+inA@mail.gmail.com>\n <f91e3aac-086a-40f7-877f-8506aa7732a5@126.com> <87cxzgf0zp.fsf@gentoo.org>\n <CAFULd4aRdjgg58R+B+c1d+TaxkVZk30NV=VY_Aj6_Vsnc3zjyg@mail.gmail.com>", "From": "Kewen Lin <linkw_gcc@126.com>", "In-Reply-To": "\n <CAFULd4aRdjgg58R+B+c1d+TaxkVZk30NV=VY_Aj6_Vsnc3zjyg@mail.gmail.com>", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "7bit", "X-CM-TRANSID": "_____wDnV8UaXvRpHRCaAg--.1769S2", "X-Coremail-Antispam": "1Uf129KBjvAXoWfurWrCr17uw1fXw1xuF4fAFb_yoW8tw17Zo\n WUArnrKrWUJa1qq3s8Ka4vy3WkZFyfGr4Dtr48KFyUJFy5Wr4Duw17Wa1UW34fZr48Gr4q\n vr4Fkry3JrySqFykn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3\n AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxUsj2NDUUUU", "X-Originating-IP": "[2409:8929:149b:4446:541b:66ee:d111:e144]", "X-CM-SenderInfo": "5olqy4pbjfuqqrswhudrp/xtbBrh82wWn0Xh+oswAA3B", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hi all,\n\nCommit r17-203 caused significant increase in GCC build time\non several environment as folks reported, mainly due to\nexcessively long execution time of genautomata.\n\nAs Alexander pointed out, the current division modeling in\nc86-4g*.md can cause a combinatorial explosion in the\nautomaton, that further leads to significant build time\nincrease.\n\nFollowing Alexander's suggestion, this patch introduces the\ndedicated automatons and cpu_units for idiv and fdiv, uses\nthem to updates the integer, floating point division and\nsquare root modeling for now. Some evaluated statistics\nare listed below.\n\nWith r17-202:\n\n *Tested stage-1 i686 build -j 32: 255 seconds*\n\n $ nm -CS -t d --defined-only gcc/insn-automata.o \\\n\t | sed 's/^[0-9]* 0*//' \\\n\t | sort -n | tail -20\n\t13896 r slm_transitions\n\t15360 r znver4_fp_store_transitions\n\t16760 r znver4_ieu_transitions\n\t17776 r bdver1_ieu_transitions\n\t20068 r bdver1_fp_check\n\t20068 r bdver1_fp_transitions\n\t20983 t internal_state_transition(int, DFA_chip*)\n\t22270 t internal_min_issue_delay(int, DFA_chip*)\n\t26208 r slm_min_issue_delay\n\t27244 r bdver1_fp_min_issue_delay\n\t28518 r glm_check\n\t28518 r glm_transitions\n\t33690 r geode_min_issue_delay\n\t45436 r znver4_fpu_min_issue_delay\n\t46980 r bdver3_fp_min_issue_delay\n\t49428 r glm_min_issue_delay\n\t53730 r btver2_fp_min_issue_delay\n\t53760 r znver1_fp_transitions\n\t93960 r bdver3_fp_transitions\n\t181744 r znver4_fpu_transitions\n\nWith culprit commit r17-203:\n\n *Tested stage-1 i686 build -j 32: 949 seconds*\n\n\t$ nm -CS -t d --defined-only gcc/insn-automata.o \\\n\t | sed 's/^[0-9]* 0*//' \\\n\t | sort -n | tail -20\n\t28518 r glm_check\n\t28518 r glm_transitions\n\t33690 r geode_min_issue_delay\n\t45436 r znver4_fpu_min_issue_delay\n\t46980 r bdver3_fp_min_issue_delay\n\t49428 r glm_min_issue_delay\n\t53730 r btver2_fp_min_issue_delay\n\t53760 r znver1_fp_transitions\n\t68160 r c86_4g_ieu_min_issue_delay\n\t93960 r bdver3_fp_transitions\n\t110080 r c86_4g_fp_min_issue_delay\n\t136320 r c86_4g_ieu_transitions\n\t181744 r znver4_fpu_transitions\n\t220160 r c86_4g_fp_transitions\n\t262988 r c86_4g_m7_fpu_base\n\t475225 r c86_4g_m7_ieu_min_issue_delay\n\t950450 r c86_4g_m7_ieu_transitions\n\t4010567 r c86_4g_m7_fpu_min_issue_delay\n\t5496908 r c86_4g_m7_fpu_check\n\t5496908 r c86_4g_m7_fpu_transitions\n\nWith this patch:\n\n *Tested stage-1 i686 build -j 32: 257 seconds*\n\n\t$ nm -CS -t d --defined-only gcc/insn-automata.o \\\n\t | sed 's/^[0-9]* 0*//' \\\n\t | sort -n | tail -20\n\n\t20068 r bdver1_fp_transitions\n\t22354 r c86_4g_m7_ieu_min_issue_delay\n\t25705 t internal_state_transition(int, DFA_chip*)\n\t26208 r slm_min_issue_delay\n\t27164 t internal_min_issue_delay(int, DFA_chip*)\n\t27244 r bdver1_fp_min_issue_delay\n\t28518 r glm_check\n\t28518 r glm_transitions\n\t33690 r geode_min_issue_delay\n\t33728 r c86_4g_fp_transitions\n\t45436 r znver4_fpu_min_issue_delay\n\t46980 r bdver3_fp_min_issue_delay\n\t49428 r glm_min_issue_delay\n\t53730 r btver2_fp_min_issue_delay\n\t53760 r znver1_fp_transitions\n\t89414 r c86_4g_m7_ieu_transitions\n\t93960 r bdver3_fp_transitions\n\t181744 r znver4_fpu_transitions\n\t326322 r c86_4g_m7_fpu_min_issue_delay\n\t1305288 r c86_4g_m7_fpu_transitions\n\nI noticed the number of c86_4g_m7_fpu_transitions is still\nlarge, but this patch can address the build time issue.\nTo avoid impacting folks' daily builds and regular testings,\nI'd like to land this patch first if possible. We can then further\nrefine the c86-4g modeling and investigate large transition\ncount as part of the follow-up work, even potentially part\nof PR 87832.\n\nAny thoughts? It has been bootstrapped and the regression\ntesting is currently ongoing. Is it ok for trunk if everything\ngoes well?\n\n@Sam, could you please double-check if this helps on your\nbuild boxes?\n\nThanks for all inputs, comments and suggestions!\n\nBR,\nKewen\n-----\ngcc/ChangeLog:\n\n\t* config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.\n\t(c86_4g_m7_fdiv): Ditto.\n\t(c86-4g-m7-idiv): New unit.\n\t(c86-4g-m7-fdiv): Ditto.\n\t(c86_4g_m7_idiv_DI): Adjust unit in the reservation.\n\t(c86_4g_m7_idiv_SI): Ditto.\n\t(c86_4g_m7_idiv_HI): Ditto.\n\t(c86_4g_m7_idiv_QI): Ditto.\n\t(c86_4g_m7_idiv_DI_load): Ditto.\n\t(c86_4g_m7_idiv_SI_load): Ditto.\n\t(c86_4g_m7_idiv_HI_load): Ditto.\n\t(c86_4g_m7_idiv_QI_load): Ditto.\n\t(c86_4g_m7_fp_div): Ditto.\n\t(c86_4g_m7_fp_div_load): Ditto.\n\t(c86_4g_m7_fp_idiv_load): Ditto.\n\t(c86_4g_m7_avx512_ssediv): Ditto.\n\t(c86_4g_m7_avx512_ssediv_mem): Ditto.\n\t(c86_4g_m7_avx512_ssediv_z): Ditto.\n\t(c86_4g_m7_avx512_ssediv_zmem): Ditto.\n\t(c86_4g_m7_avx512_sse_sqrt): Ditto.\n\t(c86_4g_m7_avx512_sse_sqrt_load): Ditto.\n\t(c86_4g_m7_fp_sqrt): Ditto. Rename from ...\n\t(c86_4g_m7fp_sqrt): ... here.\n\t* config/i386/c86-4g.md (c86_4g_idiv): New automaton.\n\t(c86_4g_fdiv): Ditto.\n\t(c86-4g-idiv): New unit.\n\t(c86-4g-fdiv): Ditto.\n\t(c86_4g_idiv_DI): Adjust unit in the reservation.\n\t(c86_4g_idiv_SI): Ditto.\n\t(c86_4g_idiv_HI): Ditto.\n\t(c86_4g_idiv_QI): Ditto.\n\t(c86_4g_idiv_mem_DI): Ditto.\n\t(c86_4g_idiv_mem_SI): Ditto.\n\t(c86_4g_idiv_mem_HI): Ditto.\n\t(c86_4g_idiv_mem_QI): Ditto.\n\t(c86_4g_fp_sqrt): Ditto.\n\t(c86_4g_sse_sqrt_sf): Ditto.\n\t(c86_4g_sse_sqrt_sf_mem): Ditto.\n\t(c86_4g_sse_sqrt_df): Ditto.\n\t(c86_4g_sse_sqrt_df_mem): Ditto.\n\t(c86_4g_fp_op_div): Ditto.\n\t(c86_4g_fp_op_div_load): Ditto.\n\t(c86_4g_fp_op_idiv_load): Ditto.\n\t(c86_4g_ssediv_ss_ps): Ditto.\n\t(c86_4g_ssediv_ss_ps_load): Ditto.\n\t(c86_4g_ssediv_ss_pd): Ditto.\n\t(c86_4g_ssediv_ss_pd_load): Ditto.\n\t(c86_4g_ssediv_avx256_ps): Ditto.\n\t(c86_4g_ssediv_avx256_ps_load): Ditto.\n\t(c86_4g_ssediv_avx256_pd): Ditto.\n\t(c86_4g_ssediv_avx256_pd_load): Ditto.\n\nSigned-off-by: Kewen Lin <linkewen@hygon.cn>\n---\n gcc/config/i386/c86-4g-m7.md | 45 +++++++++++++++-------------\n gcc/config/i386/c86-4g.md | 57 ++++++++++++++++++++----------------\n 2 files changed, 56 insertions(+), 46 deletions(-)", "diff": "diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md\nindex 7eda123acaa..a3701460697 100644\n--- a/gcc/config/i386/c86-4g-m7.md\n+++ b/gcc/config/i386/c86-4g-m7.md\n@@ -19,8 +19,9 @@\n \n ;; HYGON c86-4g-m7 Scheduling\n ;; Modeling automatons for decoders, integer execution pipes,\n-;; AGU pipes, branch, floating point execution and fp store units.\n-(define_automaton \"c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu\")\n+;; AGU pipes, branch, floating point execution, fp store units,\n+;; integer and floating point dividers.\n+(define_automaton \"c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu, c86_4g_m7_idiv, c86_4g_m7_fdiv\")\n \n ;; Decoders unit has 4 decoders and all of them can decode fast path\n ;; and vector type instructions.\n@@ -29,6 +30,10 @@ (define_cpu_unit \"c86-4g-m7-decode1\" \"c86_4g_m7\")\n (define_cpu_unit \"c86-4g-m7-decode2\" \"c86_4g_m7\")\n (define_cpu_unit \"c86-4g-m7-decode3\" \"c86_4g_m7\")\n \n+;; Two separated dividers for int and fp.\n+(define_cpu_unit \"c86-4g-m7-idiv\" \"c86_4g_m7_idiv\")\n+(define_cpu_unit \"c86-4g-m7-fdiv\" \"c86_4g_m7_fdiv\")\n+\n ;; Currently blocking all decoders for vector path instructions as\n ;; they are dispatched separetely as microcode sequence.\n (define_reservation \"c86-4g-m7-vector\" \"c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3\")\n@@ -168,56 +173,56 @@ (define_insn_reservation \"c86_4g_m7_idiv_DI\" 41\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"DI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*41\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*41\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_SI\" 25\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"SI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*25\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*25\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_HI\" 17\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"HI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*17\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*17\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_QI\" 15\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"QI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu3*15\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu3,c86-4g-m7-idiv*15\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_DI_load\" 45\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"DI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*41\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*41\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_SI_load\" 29\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"SI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*25\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*25\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_HI_load\" 21\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"HI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*17\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*17\")\n \n (define_insn_reservation \"c86_4g_m7_idiv_QI_load\" 19\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"QI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3*15\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*15\")\n \n ;; Integer/genaral Instructions\n (define_insn_reservation \"c86_4g_m7_insn\" 1\n@@ -439,7 +444,7 @@ (define_insn_reservation \"c86_4g_m7fp_sqrt\" 22\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"fpspc\")\n \t\t\t\t (eq_attr \"c86_attr\" \"sqrt\")))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*22\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*22\")\n \n ;; FPSPC\n (define_insn_reservation \"c86_4g_m7_fp_spc_direct\" 5\n@@ -482,21 +487,21 @@ (define_insn_reservation \"c86_4g_m7_fp_div\" 15\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (eq_attr \"memory\" \"none\")))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n \n (define_insn_reservation \"c86_4g_m7_fp_div_load\" 22\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (and (eq_attr \"fp_int_src\" \"false\")\n \t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n \n (define_insn_reservation \"c86_4g_m7_fp_idiv_load\" 26\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n \t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n \n (define_insn_reservation \"c86_4g_m7_fp_fsgn\" 1\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n@@ -1531,28 +1536,28 @@ (define_insn_reservation \"c86_4g_m7_avx512_ssediv\" 13\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13\")\n \n (define_insn_reservation \"c86_4g_m7_avx512_ssediv_mem\" 20\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13\")\n \n (define_insn_reservation \"c86_4g_m7_avx512_ssediv_z\" 24\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24\")\n \n (define_insn_reservation \"c86_4g_m7_avx512_ssediv_zmem\" 31\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF\")\n \t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24\")\n \n ;; SSECMP\n (define_insn_reservation \"c86_4g_m7_avx512_ssecmp\" 5\n@@ -1932,14 +1937,14 @@ (define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt\" 16\n \t\t\t (and (eq_attr \"type\" \"sse\")\n \t\t\t\t (and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16\")\n \n (define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt_load\" 23\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n \t\t\t (and (eq_attr \"type\" \"sse\")\n \t\t\t\t (and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16\")\n \n ;; MSKLOG/MSKMOV\n (define_insn_reservation \"c86_4g_m7_avx512_msklog\" 1\ndiff --git a/gcc/config/i386/c86-4g.md b/gcc/config/i386/c86-4g.md\nindex 66c4e2cf744..49a46a8aa19 100644\n--- a/gcc/config/i386/c86-4g.md\n+++ b/gcc/config/i386/c86-4g.md\n@@ -29,8 +29,9 @@ (define_attr \"c86_attr\" \"other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,\n \n ;; HYGON Scheduling\n ;; Modeling automatons for decoders, integer execution pipes,\n-;; AGU pipes and floating point execution units.\n-(define_automaton \"c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu\")\n+;; AGU pipes, floating point execution units, integer and\n+;; floating point dividers.\n+(define_automaton \"c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu, c86_4g_idiv, c86_4g_fdiv\")\n \n ;; Decoders unit has 4 decoders and all of them can decode fast path\n ;; and vector type instructions.\n@@ -39,6 +40,10 @@ (define_cpu_unit \"c86-4g-decode1\" \"c86_4g\")\n (define_cpu_unit \"c86-4g-decode2\" \"c86_4g\")\n (define_cpu_unit \"c86-4g-decode3\" \"c86_4g\")\n \n+;; Two separated dividers for int and fp.\n+(define_cpu_unit \"c86-4g-idiv\" \"c86_4g_idiv\")\n+(define_cpu_unit \"c86-4g-fdiv\" \"c86_4g_fdiv\")\n+\n ;; Currently blocking all decoders for vector path instructions as\n ;; they are dispatched separetely as microcode sequence.\n ;; Fix me: Need to revisit this.\n@@ -146,28 +151,28 @@ (define_insn_reservation \"c86_4g_idiv_DI\" 41\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"DI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-double,c86-4g-ieu2*41\")\n+\t\t\t \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*41\")\n \n (define_insn_reservation \"c86_4g_idiv_SI\" 25\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"SI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-double,c86-4g-ieu2*25\")\n+\t\t\t \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*25\")\n \n (define_insn_reservation \"c86_4g_idiv_HI\" 17\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"HI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-double,c86-4g-ieu2*17\")\n+\t\t\t \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*17\")\n \n (define_insn_reservation \"c86_4g_idiv_QI\" 15\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"QI\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-direct,c86-4g-ieu2*15\")\n+\t\t\t \"c86-4g-direct,c86-4g-ieu2,c86-4g-idiv*15\")\n \n ;; Mem operands\n (define_insn_reservation \"c86_4g_idiv_mem_DI\" 45\n@@ -175,28 +180,28 @@ (define_insn_reservation \"c86_4g_idiv_mem_DI\" 45\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"DI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*41\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*41\")\n \n (define_insn_reservation \"c86_4g_idiv_mem_SI\" 29\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"SI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*25\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*25\")\n \n (define_insn_reservation \"c86_4g_idiv_mem_HI\" 21\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"HI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*17\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*17\")\n \n (define_insn_reservation \"c86_4g_idiv_mem_QI\" 19\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"idiv\")\n \t\t\t\t (and (eq_attr \"mode\" \"QI\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-ieu2*15\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*15\")\n \n ;; STR ISHIFT which are micro coded.\n ;; Fix me: Latency need to be rechecked.\n@@ -382,7 +387,7 @@ (define_insn_reservation \"c86_4g_fp_sqrt\" 22\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"fpspc\")\n \t\t\t\t (eq_attr \"c86_attr\" \"sqrt\")))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*22\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*22\")\n \n (define_insn_reservation \"c86_4g_sse_sqrt_sf\" 14\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n@@ -390,7 +395,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_sf\" 14\n \t\t\t\t (and (eq_attr \"memory\" \"none,unknown\")\n \t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*14\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*14\")\n \n (define_insn_reservation \"c86_4g_sse_sqrt_sf_mem\" 21\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n@@ -398,7 +403,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_sf_mem\" 21\n \t\t\t\t (and (eq_attr \"memory\" \"load\")\n \t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*14\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*14\")\n \n (define_insn_reservation \"c86_4g_sse_sqrt_df\" 20\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n@@ -406,7 +411,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_df\" 20\n \t\t\t\t (and (eq_attr \"memory\" \"none,unknown\")\n \t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*20\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*20\")\n \n (define_insn_reservation \"c86_4g_sse_sqrt_df_mem\" 27\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n@@ -414,7 +419,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_df_mem\" 27\n \t\t\t\t (and (eq_attr \"memory\" \"load\")\n \t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n \t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*20\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*20\")\n \n ;; RCP\n (define_insn_reservation \"c86_4g_sse_rcp\" 5\n@@ -487,20 +492,20 @@ (define_insn_reservation \"c86_4g_fp_op_div\" 15\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (eq_attr \"memory\" \"none\")))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*15\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*15\")\n \n (define_insn_reservation \"c86_4g_fp_op_div_load\" 22\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (eq_attr \"memory\" \"load\")))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*15\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*15\")\n \n (define_insn_reservation \"c86_4g_fp_op_idiv_load\" 27\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"type\" \"fdiv\")\n \t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*19\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*19\")\n \n ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions\n (define_insn_reservation \"c86_4g_fp_insn\" 1\n@@ -1019,28 +1024,28 @@ (define_insn_reservation \"c86_4g_ssediv_ss_ps\" 10\n \t\t\t\t\t(eq_attr \"mode\" \"V4SF,SF\"))\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (eq_attr \"memory\" \"none\")))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*10\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*10\")\n \n (define_insn_reservation \"c86_4g_ssediv_ss_ps_load\" 17\n \t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t\t\t(eq_attr \"mode\" \"V4SF,SF\"))\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (eq_attr \"memory\" \"load\")))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*10\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10\")\n \n (define_insn_reservation \"c86_4g_ssediv_sd_pd\" 13\n \t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t\t\t(eq_attr \"mode\" \"V2DF,DF\"))\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (eq_attr \"memory\" \"none\")))\n-\t\t\t \"c86-4g-direct,c86-4g-fp1*13\")\n+\t\t\t \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*13\")\n \n (define_insn_reservation \"c86_4g_ssediv_sd_pd_load\" 20\n \t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t\t\t (eq_attr \"mode\" \"V2DF,DF\"))\n \t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t (eq_attr \"memory\" \"load\")))\n-\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*13\")\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13\")\n \n \n (define_insn_reservation \"c86_4g_ssediv_avx256_ps\" 10\n@@ -1048,28 +1053,28 @@ (define_insn_reservation \"c86_4g_ssediv_avx256_ps\" 10\n \t\t\t (and (eq_attr \"mode\" \"V8SF\")\n \t\t\t\t (and (eq_attr \"memory\" \"none\")\n \t\t\t\t\t(eq_attr \"type\" \"ssediv\"))))\n-\t\t\t \"c86-4g-double,c86-4g-fp1*10\")\n+\t\t\t \"c86-4g-double,c86-4g-fp1,c86-4g-fdiv*10\")\n \n (define_insn_reservation \"c86_4g_ssediv_avx256_ps_load\" 17\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"mode\" \"V8SF\")\n \t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*10\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10\")\n \n (define_insn_reservation \"c86_4g_ssediv_avx256_pd\" 13\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"mode\" \"V4DF\")\n \t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n-\t\t\t \"c86-4g-double,c86-4g-fp1*13\")\n+\t\t\t \"c86-4g-double,c86-4g-fp1,c86-4g-fdiv*13\")\n \n (define_insn_reservation \"c86_4g_ssediv_avx256_pd_load\" 20\n \t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n \t\t\t (and (eq_attr \"mode\" \"V4DF\")\n \t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n \t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n-\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*13\")\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13\")\n ;; SSE MUL\n (define_insn_reservation \"c86_4g_ssemul_ss_ps\" 3\n \t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n", "prefixes": [] }