[{"id":3685054,"web_url":"http://patchwork.ozlabs.org/comment/3685054/","msgid":"","list_archive_url":null,"date":"2026-05-01T08:14:46","subject":"Re: [PATCH] i386: Adjust some c86-4g*.md modeling to reduce build\n time","submitter":{"id":808,"url":"http://patchwork.ozlabs.org/api/people/808/","name":"Uros Bizjak","email":"ubizjak@gmail.com"},"content":"On Fri, May 1, 2026 at 10:06 AM Kewen Lin wrote:\n>\n> Hi all,\n>\n> Commit r17-203 caused significant increase in GCC build time\n> on several environment as folks reported, mainly due to\n> excessively long execution time of genautomata.\n>\n> As Alexander pointed out, the current division modeling in\n> c86-4g*.md can cause a combinatorial explosion in the\n> automaton, that further leads to significant build time\n> increase.\n>\n> Following Alexander's suggestion, this patch introduces the\n> dedicated automatons and cpu_units for idiv and fdiv, uses\n> them to updates the integer, floating point division and\n> square root modeling for now. Some evaluated statistics\n> are listed below.\n>\n> With r17-202:\n>\n> *Tested stage-1 i686 build -j 32: 255 seconds*\n>\n> $ nm -CS -t d --defined-only gcc/insn-automata.o \\\n> | sed 's/^[0-9]* 0*//' \\\n> | sort -n | tail -20\n> 13896 r slm_transitions\n> 15360 r znver4_fp_store_transitions\n> 16760 r znver4_ieu_transitions\n> 17776 r bdver1_ieu_transitions\n> 20068 r bdver1_fp_check\n> 20068 r bdver1_fp_transitions\n> 20983 t internal_state_transition(int, DFA_chip*)\n> 22270 t internal_min_issue_delay(int, DFA_chip*)\n> 26208 r slm_min_issue_delay\n> 27244 r bdver1_fp_min_issue_delay\n> 28518 r glm_check\n> 28518 r glm_transitions\n> 33690 r geode_min_issue_delay\n> 45436 r znver4_fpu_min_issue_delay\n> 46980 r bdver3_fp_min_issue_delay\n> 49428 r glm_min_issue_delay\n> 53730 r btver2_fp_min_issue_delay\n> 53760 r znver1_fp_transitions\n> 93960 r bdver3_fp_transitions\n> 181744 r znver4_fpu_transitions\n>\n> With culprit commit r17-203:\n>\n> *Tested stage-1 i686 build -j 32: 949 seconds*\n>\n> $ nm -CS -t d --defined-only gcc/insn-automata.o \\\n> | sed 's/^[0-9]* 0*//' \\\n> | sort -n | tail -20\n> 28518 r glm_check\n> 28518 r glm_transitions\n> 33690 r geode_min_issue_delay\n> 45436 r znver4_fpu_min_issue_delay\n> 46980 r bdver3_fp_min_issue_delay\n> 49428 r glm_min_issue_delay\n> 53730 r btver2_fp_min_issue_delay\n> 53760 r znver1_fp_transitions\n> 68160 r c86_4g_ieu_min_issue_delay\n> 93960 r bdver3_fp_transitions\n> 110080 r c86_4g_fp_min_issue_delay\n> 136320 r c86_4g_ieu_transitions\n> 181744 r znver4_fpu_transitions\n> 220160 r c86_4g_fp_transitions\n> 262988 r c86_4g_m7_fpu_base\n> 475225 r c86_4g_m7_ieu_min_issue_delay\n> 950450 r c86_4g_m7_ieu_transitions\n> 4010567 r c86_4g_m7_fpu_min_issue_delay\n> 5496908 r c86_4g_m7_fpu_check\n> 5496908 r c86_4g_m7_fpu_transitions\n>\n> With this patch:\n>\n> *Tested stage-1 i686 build -j 32: 257 seconds*\n>\n> $ nm -CS -t d --defined-only gcc/insn-automata.o \\\n> | sed 's/^[0-9]* 0*//' \\\n> | sort -n | tail -20\n>\n> 20068 r bdver1_fp_transitions\n> 22354 r c86_4g_m7_ieu_min_issue_delay\n> 25705 t internal_state_transition(int, DFA_chip*)\n> 26208 r slm_min_issue_delay\n> 27164 t internal_min_issue_delay(int, DFA_chip*)\n> 27244 r bdver1_fp_min_issue_delay\n> 28518 r glm_check\n> 28518 r glm_transitions\n> 33690 r geode_min_issue_delay\n> 33728 r c86_4g_fp_transitions\n> 45436 r znver4_fpu_min_issue_delay\n> 46980 r bdver3_fp_min_issue_delay\n> 49428 r glm_min_issue_delay\n> 53730 r btver2_fp_min_issue_delay\n> 53760 r znver1_fp_transitions\n> 89414 r c86_4g_m7_ieu_transitions\n> 93960 r bdver3_fp_transitions\n> 181744 r znver4_fpu_transitions\n> 326322 r c86_4g_m7_fpu_min_issue_delay\n> 1305288 r c86_4g_m7_fpu_transitions\n>\n> I noticed the number of c86_4g_m7_fpu_transitions is still\n> large, but this patch can address the build time issue.\n> To avoid impacting folks' daily builds and regular testings,\n> I'd like to land this patch first if possible. We can then further\n> refine the c86-4g modeling and investigate large transition\n> count as part of the follow-up work, even potentially part\n> of PR 87832.\n>\n> Any thoughts? It has been bootstrapped and the regression\n> testing is currently ongoing. Is it ok for trunk if everything\n> goes well?\n\nYes, please go ahead ASAP.\n\nThe patch is rubber stamped OK as an emergency fix. Any further\nrefinements can be committed separately as follow-ups.\n\nThanks for the prompt fix,\nUros.\n\n>\n> @Sam, could you please double-check if this helps on your\n> build boxes?\n>\n> Thanks for all inputs, comments and suggestions!\n>\n> BR,\n> Kewen\n> -----\n> gcc/ChangeLog:\n>\n> * config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.\n> (c86_4g_m7_fdiv): Ditto.\n> (c86-4g-m7-idiv): New unit.\n> (c86-4g-m7-fdiv): Ditto.\n> (c86_4g_m7_idiv_DI): Adjust unit in the reservation.\n> (c86_4g_m7_idiv_SI): Ditto.\n> (c86_4g_m7_idiv_HI): Ditto.\n> (c86_4g_m7_idiv_QI): Ditto.\n> (c86_4g_m7_idiv_DI_load): Ditto.\n> (c86_4g_m7_idiv_SI_load): Ditto.\n> (c86_4g_m7_idiv_HI_load): Ditto.\n> (c86_4g_m7_idiv_QI_load): Ditto.\n> (c86_4g_m7_fp_div): Ditto.\n> (c86_4g_m7_fp_div_load): Ditto.\n> (c86_4g_m7_fp_idiv_load): Ditto.\n> (c86_4g_m7_avx512_ssediv): Ditto.\n> (c86_4g_m7_avx512_ssediv_mem): Ditto.\n> (c86_4g_m7_avx512_ssediv_z): Ditto.\n> (c86_4g_m7_avx512_ssediv_zmem): Ditto.\n> (c86_4g_m7_avx512_sse_sqrt): Ditto.\n> (c86_4g_m7_avx512_sse_sqrt_load): Ditto.\n> (c86_4g_m7_fp_sqrt): Ditto. Rename from ...\n> (c86_4g_m7fp_sqrt): ... here.\n> * config/i386/c86-4g.md (c86_4g_idiv): New automaton.\n> (c86_4g_fdiv): Ditto.\n> (c86-4g-idiv): New unit.\n> (c86-4g-fdiv): Ditto.\n> (c86_4g_idiv_DI): Adjust unit in the reservation.\n> (c86_4g_idiv_SI): Ditto.\n> (c86_4g_idiv_HI): Ditto.\n> (c86_4g_idiv_QI): Ditto.\n> (c86_4g_idiv_mem_DI): Ditto.\n> (c86_4g_idiv_mem_SI): Ditto.\n> (c86_4g_idiv_mem_HI): Ditto.\n> (c86_4g_idiv_mem_QI): Ditto.\n> (c86_4g_fp_sqrt): Ditto.\n> (c86_4g_sse_sqrt_sf): Ditto.\n> (c86_4g_sse_sqrt_sf_mem): Ditto.\n> (c86_4g_sse_sqrt_df): Ditto.\n> (c86_4g_sse_sqrt_df_mem): Ditto.\n> (c86_4g_fp_op_div): Ditto.\n> (c86_4g_fp_op_div_load): Ditto.\n> (c86_4g_fp_op_idiv_load): Ditto.\n> (c86_4g_ssediv_ss_ps): Ditto.\n> (c86_4g_ssediv_ss_ps_load): Ditto.\n> (c86_4g_ssediv_ss_pd): Ditto.\n> (c86_4g_ssediv_ss_pd_load): Ditto.\n> (c86_4g_ssediv_avx256_ps): Ditto.\n> (c86_4g_ssediv_avx256_ps_load): Ditto.\n> (c86_4g_ssediv_avx256_pd): Ditto.\n> (c86_4g_ssediv_avx256_pd_load): Ditto.\n>\n> Signed-off-by: Kewen Lin \n> ---\n> gcc/config/i386/c86-4g-m7.md | 45 +++++++++++++++-------------\n> gcc/config/i386/c86-4g.md | 57 ++++++++++++++++++++----------------\n> 2 files changed, 56 insertions(+), 46 deletions(-)\n>\n> diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md\n> index 7eda123acaa..a3701460697 100644\n> --- a/gcc/config/i386/c86-4g-m7.md\n> +++ b/gcc/config/i386/c86-4g-m7.md\n> @@ -19,8 +19,9 @@\n>\n> ;; HYGON c86-4g-m7 Scheduling\n> ;; Modeling automatons for decoders, integer execution pipes,\n> -;; AGU pipes, branch, floating point execution and fp store units.\n> -(define_automaton \"c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu\")\n> +;; AGU pipes, branch, floating point execution, fp store units,\n> +;; integer and floating point dividers.\n> +(define_automaton \"c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu, c86_4g_m7_idiv, c86_4g_m7_fdiv\")\n>\n> ;; Decoders unit has 4 decoders and all of them can decode fast path\n> ;; and vector type instructions.\n> @@ -29,6 +30,10 @@ (define_cpu_unit \"c86-4g-m7-decode1\" \"c86_4g_m7\")\n> (define_cpu_unit \"c86-4g-m7-decode2\" \"c86_4g_m7\")\n> (define_cpu_unit \"c86-4g-m7-decode3\" \"c86_4g_m7\")\n>\n> +;; Two separated dividers for int and fp.\n> +(define_cpu_unit \"c86-4g-m7-idiv\" \"c86_4g_m7_idiv\")\n> +(define_cpu_unit \"c86-4g-m7-fdiv\" \"c86_4g_m7_fdiv\")\n> +\n> ;; Currently blocking all decoders for vector path instructions as\n> ;; they are dispatched separetely as microcode sequence.\n> (define_reservation \"c86-4g-m7-vector\" \"c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3\")\n> @@ -168,56 +173,56 @@ (define_insn_reservation \"c86_4g_m7_idiv_DI\" 41\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"DI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-ieu3*41\")\n> + \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*41\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_SI\" 25\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"SI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-ieu3*25\")\n> + \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*25\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_HI\" 17\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"HI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-ieu3*17\")\n> + \"c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*17\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_QI\" 15\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"QI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-ieu3*15\")\n> + \"c86-4g-m7-direct,c86-4g-m7-ieu3,c86-4g-m7-idiv*15\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_DI_load\" 45\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"DI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*41\")\n> + \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*41\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_SI_load\" 29\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"SI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*25\")\n> + \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*25\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_HI_load\" 21\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"HI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*17\")\n> + \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*17\")\n>\n> (define_insn_reservation \"c86_4g_m7_idiv_QI_load\" 19\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"QI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3*15\")\n> + \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*15\")\n>\n> ;; Integer/genaral Instructions\n> (define_insn_reservation \"c86_4g_m7_insn\" 1\n> @@ -439,7 +444,7 @@ (define_insn_reservation \"c86_4g_m7fp_sqrt\" 22\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"fpspc\")\n> (eq_attr \"c86_attr\" \"sqrt\")))\n> - \"c86-4g-m7-direct,c86-4g-m7-fpu1*22\")\n> + \"c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*22\")\n>\n> ;; FPSPC\n> (define_insn_reservation \"c86_4g_m7_fp_spc_direct\" 5\n> @@ -482,21 +487,21 @@ (define_insn_reservation \"c86_4g_m7_fp_div\" 15\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (eq_attr \"memory\" \"none\")))\n> - \"c86-4g-m7-direct,c86-4g-m7-fpu1*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n>\n> (define_insn_reservation \"c86_4g_m7_fp_div_load\" 22\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (and (eq_attr \"fp_int_src\" \"false\")\n> (eq_attr \"memory\" \"!none\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n>\n> (define_insn_reservation \"c86_4g_m7_fp_idiv_load\" 26\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (and (eq_attr \"fp_int_src\" \"true\")\n> (eq_attr \"memory\" \"!none\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n> + \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fdiv*15\")\n>\n> (define_insn_reservation \"c86_4g_m7_fp_fsgn\" 1\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> @@ -1531,28 +1536,28 @@ (define_insn_reservation \"c86_4g_m7_avx512_ssediv\" 13\n> (and (eq_attr \"type\" \"ssediv\")\n> (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13\")\n>\n> (define_insn_reservation \"c86_4g_m7_avx512_ssediv_mem\" 20\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*13\")\n>\n> (define_insn_reservation \"c86_4g_m7_avx512_ssediv_z\" 24\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (and (eq_attr \"mode\" \"V16SF,V8DF\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24\")\n>\n> (define_insn_reservation \"c86_4g_m7_avx512_ssediv_zmem\" 31\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (and (eq_attr \"mode\" \"V16SF,V8DF\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fdiv*24\")\n>\n> ;; SSECMP\n> (define_insn_reservation \"c86_4g_m7_avx512_ssecmp\" 5\n> @@ -1932,14 +1937,14 @@ (define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt\" 16\n> (and (eq_attr \"type\" \"sse\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16\")\n>\n> (define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt_load\" 23\n> (and (eq_attr \"cpu\" \"c86_4g_m7\")\n> (and (eq_attr \"type\" \"sse\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n> + \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu3,c86-4g-m7-fdiv*16\")\n>\n> ;; MSKLOG/MSKMOV\n> (define_insn_reservation \"c86_4g_m7_avx512_msklog\" 1\n> diff --git a/gcc/config/i386/c86-4g.md b/gcc/config/i386/c86-4g.md\n> index 66c4e2cf744..49a46a8aa19 100644\n> --- a/gcc/config/i386/c86-4g.md\n> +++ b/gcc/config/i386/c86-4g.md\n> @@ -29,8 +29,9 @@ (define_attr \"c86_attr\" \"other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,\n>\n> ;; HYGON Scheduling\n> ;; Modeling automatons for decoders, integer execution pipes,\n> -;; AGU pipes and floating point execution units.\n> -(define_automaton \"c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu\")\n> +;; AGU pipes, floating point execution units, integer and\n> +;; floating point dividers.\n> +(define_automaton \"c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu, c86_4g_idiv, c86_4g_fdiv\")\n>\n> ;; Decoders unit has 4 decoders and all of them can decode fast path\n> ;; and vector type instructions.\n> @@ -39,6 +40,10 @@ (define_cpu_unit \"c86-4g-decode1\" \"c86_4g\")\n> (define_cpu_unit \"c86-4g-decode2\" \"c86_4g\")\n> (define_cpu_unit \"c86-4g-decode3\" \"c86_4g\")\n>\n> +;; Two separated dividers for int and fp.\n> +(define_cpu_unit \"c86-4g-idiv\" \"c86_4g_idiv\")\n> +(define_cpu_unit \"c86-4g-fdiv\" \"c86_4g_fdiv\")\n> +\n> ;; Currently blocking all decoders for vector path instructions as\n> ;; they are dispatched separetely as microcode sequence.\n> ;; Fix me: Need to revisit this.\n> @@ -146,28 +151,28 @@ (define_insn_reservation \"c86_4g_idiv_DI\" 41\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"DI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-double,c86-4g-ieu2*41\")\n> + \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*41\")\n>\n> (define_insn_reservation \"c86_4g_idiv_SI\" 25\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"SI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-double,c86-4g-ieu2*25\")\n> + \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*25\")\n>\n> (define_insn_reservation \"c86_4g_idiv_HI\" 17\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"HI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-double,c86-4g-ieu2*17\")\n> + \"c86-4g-double,c86-4g-ieu2,c86-4g-idiv*17\")\n>\n> (define_insn_reservation \"c86_4g_idiv_QI\" 15\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"QI\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-direct,c86-4g-ieu2*15\")\n> + \"c86-4g-direct,c86-4g-ieu2,c86-4g-idiv*15\")\n>\n> ;; Mem operands\n> (define_insn_reservation \"c86_4g_idiv_mem_DI\" 45\n> @@ -175,28 +180,28 @@ (define_insn_reservation \"c86_4g_idiv_mem_DI\" 45\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"DI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-ieu2*41\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*41\")\n>\n> (define_insn_reservation \"c86_4g_idiv_mem_SI\" 29\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"SI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-ieu2*25\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*25\")\n>\n> (define_insn_reservation \"c86_4g_idiv_mem_HI\" 21\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"HI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-ieu2*17\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*17\")\n>\n> (define_insn_reservation \"c86_4g_idiv_mem_QI\" 19\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"idiv\")\n> (and (eq_attr \"mode\" \"QI\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-ieu2*15\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*15\")\n>\n> ;; STR ISHIFT which are micro coded.\n> ;; Fix me: Latency need to be rechecked.\n> @@ -382,7 +387,7 @@ (define_insn_reservation \"c86_4g_fp_sqrt\" 22\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"fpspc\")\n> (eq_attr \"c86_attr\" \"sqrt\")))\n> - \"c86-4g-direct,c86-4g-fp1*22\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*22\")\n>\n> (define_insn_reservation \"c86_4g_sse_sqrt_sf\" 14\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> @@ -390,7 +395,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_sf\" 14\n> (and (eq_attr \"memory\" \"none,unknown\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"type\" \"sse\")))))\n> - \"c86-4g-direct,c86-4g-fp1*14\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*14\")\n>\n> (define_insn_reservation \"c86_4g_sse_sqrt_sf_mem\" 21\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> @@ -398,7 +403,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_sf_mem\" 21\n> (and (eq_attr \"memory\" \"load\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"type\" \"sse\")))))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-fp1*14\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*14\")\n>\n> (define_insn_reservation \"c86_4g_sse_sqrt_df\" 20\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> @@ -406,7 +411,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_df\" 20\n> (and (eq_attr \"memory\" \"none,unknown\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"type\" \"sse\")))))\n> - \"c86-4g-direct,c86-4g-fp1*20\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*20\")\n>\n> (define_insn_reservation \"c86_4g_sse_sqrt_df_mem\" 27\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> @@ -414,7 +419,7 @@ (define_insn_reservation \"c86_4g_sse_sqrt_df_mem\" 27\n> (and (eq_attr \"memory\" \"load\")\n> (and (eq_attr \"c86_attr\" \"sqrt\")\n> (eq_attr \"type\" \"sse\")))))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-fp1*20\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*20\")\n>\n> ;; RCP\n> (define_insn_reservation \"c86_4g_sse_rcp\" 5\n> @@ -487,20 +492,20 @@ (define_insn_reservation \"c86_4g_fp_op_div\" 15\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (eq_attr \"memory\" \"none\")))\n> - \"c86-4g-direct,c86-4g-fp1*15\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*15\")\n>\n> (define_insn_reservation \"c86_4g_fp_op_div_load\" 22\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (eq_attr \"memory\" \"load\")))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-fp1*15\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*15\")\n>\n> (define_insn_reservation \"c86_4g_fp_op_idiv_load\" 27\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"type\" \"fdiv\")\n> (and (eq_attr \"fp_int_src\" \"true\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-fp1*19\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*19\")\n>\n> ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions\n> (define_insn_reservation \"c86_4g_fp_insn\" 1\n> @@ -1019,28 +1024,28 @@ (define_insn_reservation \"c86_4g_ssediv_ss_ps\" 10\n> (eq_attr \"mode\" \"V4SF,SF\"))\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"none\")))\n> - \"c86-4g-direct,c86-4g-fp1*10\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*10\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_ss_ps_load\" 17\n> (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (eq_attr \"mode\" \"V4SF,SF\"))\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"load\")))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-fp1*10\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_sd_pd\" 13\n> (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (eq_attr \"mode\" \"V2DF,DF\"))\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"none\")))\n> - \"c86-4g-direct,c86-4g-fp1*13\")\n> + \"c86-4g-direct,c86-4g-fp1,c86-4g-fdiv*13\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_sd_pd_load\" 20\n> (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (eq_attr \"mode\" \"V2DF,DF\"))\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"load\")))\n> - \"c86-4g-direct,c86-4g-load,c86-4g-fp1*13\")\n> + \"c86-4g-direct,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13\")\n>\n>\n> (define_insn_reservation \"c86_4g_ssediv_avx256_ps\" 10\n> @@ -1048,28 +1053,28 @@ (define_insn_reservation \"c86_4g_ssediv_avx256_ps\" 10\n> (and (eq_attr \"mode\" \"V8SF\")\n> (and (eq_attr \"memory\" \"none\")\n> (eq_attr \"type\" \"ssediv\"))))\n> - \"c86-4g-double,c86-4g-fp1*10\")\n> + \"c86-4g-double,c86-4g-fp1,c86-4g-fdiv*10\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_avx256_ps_load\" 17\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"mode\" \"V8SF\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-fp1*10\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*10\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_avx256_pd\" 13\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"mode\" \"V4DF\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"none\"))))\n> - \"c86-4g-double,c86-4g-fp1*13\")\n> + \"c86-4g-double,c86-4g-fp1,c86-4g-fdiv*13\")\n>\n> (define_insn_reservation \"c86_4g_ssediv_avx256_pd_load\" 20\n> (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> (and (eq_attr \"mode\" \"V4DF\")\n> (and (eq_attr \"type\" \"ssediv\")\n> (eq_attr \"memory\" \"load\"))))\n> - \"c86-4g-double,c86-4g-load,c86-4g-fp1*13\")\n> + \"c86-4g-double,c86-4g-load,c86-4g-fp1,c86-4g-fdiv*13\")\n> ;; SSE MUL\n> (define_insn_reservation \"c86_4g_ssemul_ss_ps\" 3\n> (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n> --\n> 2.34.1\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=OH2LPaXs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=OH2LPaXs","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","sourceware.org; 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