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GET /api/1.1/patches/2231060/?format=api
{ "id": 2231060, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430095202.1167651-4-amhetre@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260430095202.1167651-4-amhetre@nvidia.com>", "date": "2026-04-30T09:52:02", "name": "[V3,3/3] memory: tegra: Restore MC interrupt masks on resume", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "868080ef199eb9757a3d9d9de62e456d9f5f5249", "submitter": { "id": 75198, "url": "http://patchwork.ozlabs.org/api/1.1/people/75198/?format=api", "name": "Ashish Mhetre", "email": "amhetre@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430095202.1167651-4-amhetre@nvidia.com/mbox/", "series": [ { "id": 502262, "url": "http://patchwork.ozlabs.org/api/1.1/series/502262/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502262", "date": "2026-04-30T09:52:01", "name": "memory: tegra: Restore MC state on system resume", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502262/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231060/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14083-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=jJPLrKi/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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pr=C", "From": "Ashish Mhetre <amhetre@nvidia.com>", "To": "<krzk@kernel.org>, <thierry.reding@kernel.org>, <jonathanh@nvidia.com>", "CC": "<ketanp@nvidia.com>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Ashish Mhetre <amhetre@nvidia.com>", "Subject": "[PATCH V3 3/3] memory: tegra: Restore MC interrupt masks on resume", "Date": "Thu, 30 Apr 2026 09:52:02 +0000", "Message-ID": "<20260430095202.1167651-4-amhetre@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260430095202.1167651-1-amhetre@nvidia.com>", "References": "<20260430095202.1167651-1-amhetre@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH1PEPF0000A349:EE_|DS4PR12MB9633:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e648401a-e776-40e6-5a69-08dea69e3708", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tQtC/h2QI6JS/ryUNDOiBXMQcQFMzzqY9PiP4irXtyP4eQ8gP0MMNvONxhYTNyaG8OqLKZ+IYRZ/l5pZRHhQW1IzoMR1TovixBH3pcegfPAFSDpNvAli+DpAWjJ1dLucqV44VfwL10zcssBENIpqtCUJuQLha/gYKkyuP0o0nEkkJkp0YChBmVs4eoeAmCV7PrTljU/ZldS3GtJml6zxyyqgDg8KXP68Tt3eOhdwnfzXyXCpv+ZlngY5ZhXJThJ7X5/EyoVlU0iaL01booRwa2AmYwHSSzjrM8b0par2wqxEo4xgLnQzfs8B0USX/MeQb/fF1G7+YUeR9maAkdZVkRm1Y2dZu2iMQeTEICfwTBW2aCakPkBB4b9uoLBqjYvldoaK23W2JqZCToRaaYeeaN7fpNUuxqaaiWkrjeLMytTgBQ/bgQOvaG11kNqHrEq4seg/Oc4FEfp1RyPNAtR72j8tNLKYXt/ZYEmsacWkmrUcEDCOpiA4IyWrXxQO+VXG/Wlsd3pmb/w9XPBqHdvulKdR1d+1LXjVITLSjQOEkAr5H3b2c85cXzBMCqwwSHam+fKH9FFXaND38VbZVu2kiVFC7Q8Ftmxun05VJgz2TLJaQYcRdRDKQPIV+6J5rQQCtCgdqcmQyNtLCKKqpgZxpGrtJT8ZxowEMb0pzrKxt4AYFhXhdroCLRZaWQDFOH3qR/+N+VRjxRr/qrwTYhh8ds6BVwinvIevY9BJAynrMGdTHPdXLCvFLWVi8OXwtkTq25g6l3EKttNOAnt52ysXFhQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tkHjF+cKDC2qhjTuK3lGqvnrqfqZUfRDWMeCZLvPbxTrLvPRvbRWMTWoo1QXq5DVBLhx7tgpXwgGVjQ+sP/7TDCqXqBVWMWcPXYiV1nYE/1aJPrPQQEIz77V2jLYmBy97Yi3+TZYIEOE8RfBz9LE02al7zgy8mF6LUB3o+pudTEdr4O6QVWEg0vpFscp3sw+4qy0j2l59dd91BIljEHMvFBS/IXDWkDVfmJxGnHgtUWNb+MwHxjlqa9XI2+JQuw1Tha/OmlGlKMu46iync2DWq3K7qjlUbZTkU4QjNpq6nS5Q3mUVuCpQ+DStntMKpHW3TNkrF1KwPRnO7skeKOmZBjXKxVZ+H9GOm+qZdX0iRY/9AB4T4u103OIXyflR8ESdSn2TtJlCMxBQGQ0YJvJpiS7zmuqtdawbSfrnKflJpZTnn6Yh4EyWIJzpYe2VAUCD", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2026 09:52:38.9980\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e648401a-e776-40e6-5a69-08dea69e3708", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCH1PEPF0000A349.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS4PR12MB9633" }, "content": "The MC interrupt mask registers lose their state across SC7. Without\nre-applying them on resume, MC interrupts that were enabled at probe\nremain masked after wake, so any post-resume MC error goes unreported.\n\nFactor the existing intmask programming out of tegra_mc_probe() into\ntegra_mc_setup_intmask() and reuse it from the system resume callback\nso the mask state is restored on wake.\n\nSigned-off-by: Ashish Mhetre <amhetre@nvidia.com>\n---\n drivers/memory/tegra/mc.c | 23 ++++++++++++++++-------\n 1 file changed, 16 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\nindex 64e41338cdf2..cfcfc7291106 100644\n--- a/drivers/memory/tegra/mc.c\n+++ b/drivers/memory/tegra/mc.c\n@@ -911,6 +911,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)\n \t}\n }\n \n+static void tegra_mc_setup_intmask(struct tegra_mc *mc)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n+\t\tif (mc->soc->num_channels)\n+\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n+\t\t\t\t mc->soc->intmasks[i].reg);\n+\t\telse\n+\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n+\t}\n+}\n+\n static int tegra_mc_probe(struct platform_device *pdev)\n {\n \tstruct tegra_mc *mc;\n@@ -971,13 +984,7 @@ static int tegra_mc_probe(struct platform_device *pdev)\n \t\t\t}\n \t\t}\n \n-\t\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n-\t\t\tif (mc->soc->num_channels)\n-\t\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n-\t\t\t\t\t mc->soc->intmasks[i].reg);\n-\t\t\telse\n-\t\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n-\t\t}\n+\t\ttegra_mc_setup_intmask(mc);\n \t}\n \n \tif (mc->soc->reset_ops) {\n@@ -1018,6 +1025,8 @@ static int tegra_mc_resume(struct device *dev)\n \tif (mc->soc->ops && mc->soc->ops->resume)\n \t\tmc->soc->ops->resume(mc);\n \n+\ttegra_mc_setup_intmask(mc);\n+\n \treturn 0;\n }\n \n", "prefixes": [ "V3", "3/3" ] }