[{"id":3684632,"web_url":"http://patchwork.ozlabs.org/comment/3684632/","msgid":"<df25dd7a-1f59-4fd5-bdae-ba3a99e700f1@nvidia.com>","list_archive_url":null,"date":"2026-04-30T11:42:03","subject":"Re: [PATCH V3 3/3] memory: tegra: Restore MC interrupt masks on\n resume","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 30/04/2026 10:52, Ashish Mhetre wrote:\n> The MC interrupt mask registers lose their state across SC7. Without\n\nSC7 may not mean anything to anyone that is not familiar with Tegra. I \noften refer to this as 'Tegra low power suspend state (aka. SC7)'. Or we \ncan just simply say 'suspend' instead of 'SC7'.\n\nKrzysztof, do you want use to clarify this and update the commit message?\n\n> re-applying them on resume, MC interrupts that were enabled at probe\n> remain masked after wake, so any post-resume MC error goes unreported.\n> \n> Factor the existing intmask programming out of tegra_mc_probe() into\n> tegra_mc_setup_intmask() and reuse it from the system resume callback\n> so the mask state is restored on wake.\n> \n> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>\n> ---\n>   drivers/memory/tegra/mc.c | 23 ++++++++++++++++-------\n>   1 file changed, 16 insertions(+), 7 deletions(-)\n> \n> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\n> index 64e41338cdf2..cfcfc7291106 100644\n> --- a/drivers/memory/tegra/mc.c\n> +++ b/drivers/memory/tegra/mc.c\n> @@ -911,6 +911,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)\n>   \t}\n>   }\n>   \n> +static void tegra_mc_setup_intmask(struct tegra_mc *mc)\n> +{\n> +\tunsigned int i;\n> +\n> +\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n> +\t\tif (mc->soc->num_channels)\n> +\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n> +\t\t\t\t     mc->soc->intmasks[i].reg);\n> +\t\telse\n> +\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n> +\t}\n> +}\n> +\n>   static int tegra_mc_probe(struct platform_device *pdev)\n>   {\n>   \tstruct tegra_mc *mc;\n> @@ -971,13 +984,7 @@ static int tegra_mc_probe(struct platform_device *pdev)\n>   \t\t\t}\n>   \t\t}\n>   \n> -\t\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n> -\t\t\tif (mc->soc->num_channels)\n> -\t\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n> -\t\t\t\t\t     mc->soc->intmasks[i].reg);\n> -\t\t\telse\n> -\t\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n> -\t\t}\n> +\t\ttegra_mc_setup_intmask(mc);\n>   \t}\n>   \n>   \tif (mc->soc->reset_ops) {\n> @@ -1018,6 +1025,8 @@ static int tegra_mc_resume(struct device *dev)\n>   \tif (mc->soc->ops && mc->soc->ops->resume)\n>   \t\tmc->soc->ops->resume(mc);\n>   \n> +\ttegra_mc_setup_intmask(mc);\n> +\n>   \treturn 0;\n>   }\n>   \n\nOtherwise this looks good to me.\n\nJon","headers":{"Return-Path":"\n <linux-tegra+bounces-14114-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Z7KhV9wh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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