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GET /api/1.1/patches/2230217/?format=api
{ "id": 2230217, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429-shikra-pinctrl-v1-2-1b4bb2b3a8d6@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429-shikra-pinctrl-v1-2-1b4bb2b3a8d6@oss.qualcomm.com>", "date": "2026-04-29T13:11:57", "name": "[2/2] pinctrl: qcom: Add Shikra pinctrl driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "558d1374040fd2b776c2d36f42cc7f57345e7eca", "submitter": { "id": 93282, "url": "http://patchwork.ozlabs.org/api/1.1/people/93282/?format=api", "name": "Komal Bajaj", "email": "komal.bajaj@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429-shikra-pinctrl-v1-2-1b4bb2b3a8d6@oss.qualcomm.com/mbox/", "series": [ { "id": 502057, "url": "http://patchwork.ozlabs.org/api/1.1/series/502057/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502057", "date": "2026-04-29T13:11:57", "name": "pinctrl: qcom: Add support for Qualcomm Shikra SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502057/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230217/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230217/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35795-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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"X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777468321; l=46335;\n i=komal.bajaj@oss.qualcomm.com; s=20250710; h=from:subject:message-id;\n bh=bO5zwTidve7vMWrIv+O7QYhAuz9y0j/bBF4/jwIfnEc=;\n b=ke0KdmqJdDeXvwZkZfTKP0TT72cHMRH2IyeSc7WSBUNDjaC1d2R8WPHp4VV2Tyfg3/08YQ6DL\n ZPoW0YggxvfD1k05FBNC7HAtJwmLoKslkNZG1c7fWOrZR38tsob/tEE", "X-Developer-Key": "i=komal.bajaj@oss.qualcomm.com; a=ed25519;\n pk=wKh8mgDh+ePUZ4IIvpBhQOqf16/KvuQHvSvHK20LXNU=", "X-Authority-Analysis": "v=2.4 cv=XtvK/1F9 c=1 sm=1 tr=0 ts=69f203b1 cx=c_pps\n a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22\n a=EUspDBNiAAAA:8 a=QYLgUDXq4FTBpluUT7sA:9 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10\n a=3WC7DwWrALyhR5TkjVHa:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI5MDEzNCBTYWx0ZWRfX8v6Q489fKfmG\n atdxNXFWXOfqx2m2Dhs6onvK5V8/KFytpViTs45myqS/5WntoFjUvlIenzhDjhvmXMNdZL8ATlM\n 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route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290134" }, "content": "Add pinctrl driver for TLMM block found in Shikra SoC.\n\nSigned-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig.msm | 11 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-shikra.c | 1280 +++++++++++++++++++++++++++++++++\n 3 files changed, 1292 insertions(+)", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\nindex 836cdeca1006..c89b0e8790de 100644\n--- a/drivers/pinctrl/qcom/Kconfig.msm\n+++ b/drivers/pinctrl/qcom/Kconfig.msm\n@@ -369,6 +369,17 @@ config PINCTRL_SDX75\n Qualcomm Technologies Inc TLMM block found on the Qualcomm\n Technologies Inc SDX75 platform.\n \n+config PINCTRL_SHIKRA\n+\ttristate \"Qualcomm Technologies Inc Shikra pin controller driver\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\tdefault ARCH_QCOM\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n+\t Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)\n+\t found on the Qualcomm\tTechnologies Inc Shikra platform.\n+\t Say Y here to compile statically, or M here to compile it as a module.\n+\t If unsure, say N.\n+\n config PINCTRL_SM4450\n \ttristate \"Qualcomm Technologies Inc SM4450 pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 84bda3ada874..07c0d236d82f 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -57,6 +57,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o\n obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o\n obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o\n obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o\n+obj-$(CONFIG_PINCTRL_SHIKRA) += pinctrl-shikra.o\n obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o\n obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o\n obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-shikra.c b/drivers/pinctrl/qcom/pinctrl-shikra.c\nnew file mode 100644\nindex 000000000000..25acb74853d2\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-shikra.c\n@@ -0,0 +1,1280 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.grp = PINCTRL_PINGROUP(\"gpio\" #id,\t\\\n+\t\t\tgpio##id##_pins,\t\t\\\n+\t\t\tARRAY_SIZE(gpio##id##_pins)),\t\\\n+\t\t.funcs = (int[]){\t\t\t\\\n+\t\t\tmsm_mux_gpio, /* gpio mode */\t\\\n+\t\t\tmsm_mux_##f1,\t\t\t\\\n+\t\t\tmsm_mux_##f2,\t\t\t\\\n+\t\t\tmsm_mux_##f3,\t\t\t\\\n+\t\t\tmsm_mux_##f4,\t\t\t\\\n+\t\t\tmsm_mux_##f5,\t\t\t\\\n+\t\t\tmsm_mux_##f6,\t\t\t\\\n+\t\t\tmsm_mux_##f7,\t\t\t\\\n+\t\t\tmsm_mux_##f8,\t\t\t\\\n+\t\t\tmsm_mux_##f9,\t\t\t\\\n+\t\t\tmsm_mux_##f10,\t\t\t\\\n+\t\t\tmsm_mux_##f11 /* egpio mode */\t\\\n+\t\t},\t\t\t\t\t\\\n+\t\t.nfuncs = 12,\t\t\t\t\\\n+\t\t.ctl_reg = REG_SIZE * id,\t\t\\\n+\t\t.io_reg = 0x4 + REG_SIZE * id,\t\t\\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id,\t\\\n+\t\t.mux_bit = 2,\t\t\t\\\n+\t\t.pull_bit = 0,\t\t\t\\\n+\t\t.drv_bit = 6,\t\t\t\\\n+\t\t.egpio_enable = 12,\t\t\\\n+\t\t.egpio_present = 11,\t\\\n+\t\t.oe_bit = 9,\t\t\t\\\n+\t\t.in_bit = 0,\t\t\t\\\n+\t\t.out_bit = 1,\t\t\t\\\n+\t\t.intr_enable_bit = 0,\t\t\\\n+\t\t.intr_status_bit = 0,\t\t\\\n+\t\t.intr_wakeup_enable_bit = 7,\t\\\n+\t\t.intr_wakeup_present_bit = 6,\t\\\n+\t\t.intr_target_bit = 8,\t\t\\\n+\t\t.intr_target_kpss_val = 3,\t\\\n+\t\t.intr_raw_status_bit = 4,\t\\\n+\t\t.intr_polarity_bit = 1,\t\t\\\n+\t\t.intr_detection_bit = 2,\t\\\n+\t\t.intr_detection_width = 2,\t\\\n+\t}\n+\n+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n+\t\t\tpg_name##_pins,\t\t\t\\\n+\t\t\tARRAY_SIZE(pg_name##_pins)),\t\\\n+\t\t.ctl_reg = ctl,\t\t\t\t\\\n+\t\t.io_reg = 0,\t\t\t\t\\\n+\t\t.intr_cfg_reg = 0,\t\t\t\\\n+\t\t.intr_status_reg = 0,\t\t\t\\\n+\t\t.mux_bit = -1,\t\t\t\t\\\n+\t\t.pull_bit = pull,\t\t\t\\\n+\t\t.drv_bit = drv,\t\t\t\t\\\n+\t\t.oe_bit = -1,\t\t\t\t\\\n+\t\t.in_bit = -1,\t\t\t\t\\\n+\t\t.out_bit = -1,\t\t\t\t\\\n+\t\t.intr_enable_bit = -1,\t\t\t\\\n+\t\t.intr_status_bit = -1,\t\t\t\\\n+\t\t.intr_target_bit = -1,\t\t\t\\\n+\t\t.intr_raw_status_bit = -1,\t\t\\\n+\t\t.intr_polarity_bit = -1,\t\t\\\n+\t\t.intr_detection_bit = -1,\t\t\\\n+\t\t.intr_detection_width = -1,\t\t\\\n+\t}\n+\n+#define UFS_RESET(pg_name, ctl, io)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,\t\\\n+\t\t\tpg_name##_pins,\t\t\t\\\n+\t\t\tARRAY_SIZE(pg_name##_pins)),\t\\\n+\t\t.ctl_reg = ctl,\t\t\t\t\\\n+\t\t.io_reg = io,\t\t\t\t\\\n+\t\t.intr_cfg_reg = 0,\t\t\t\\\n+\t\t.intr_status_reg = 0,\t\t\t\\\n+\t\t.mux_bit = -1,\t\t\t\t\\\n+\t\t.pull_bit = 3,\t\t\t\t\\\n+\t\t.drv_bit = 0,\t\t\t\t\\\n+\t\t.oe_bit = -1,\t\t\t\t\\\n+\t\t.in_bit = -1,\t\t\t\t\\\n+\t\t.out_bit = 0,\t\t\t\t\\\n+\t\t.intr_enable_bit = -1,\t\t\t\\\n+\t\t.intr_status_bit = -1,\t\t\t\\\n+\t\t.intr_target_bit = -1,\t\t\t\\\n+\t\t.intr_raw_status_bit = -1,\t\t\\\n+\t\t.intr_polarity_bit = -1,\t\t\\\n+\t\t.intr_detection_bit = -1,\t\t\\\n+\t\t.intr_detection_width = -1,\t\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc shikra_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+\tPINCTRL_PIN(47, \"GPIO_47\"),\n+\tPINCTRL_PIN(48, \"GPIO_48\"),\n+\tPINCTRL_PIN(49, \"GPIO_49\"),\n+\tPINCTRL_PIN(50, \"GPIO_50\"),\n+\tPINCTRL_PIN(51, \"GPIO_51\"),\n+\tPINCTRL_PIN(52, \"GPIO_52\"),\n+\tPINCTRL_PIN(53, \"GPIO_53\"),\n+\tPINCTRL_PIN(54, \"GPIO_54\"),\n+\tPINCTRL_PIN(55, \"GPIO_55\"),\n+\tPINCTRL_PIN(56, \"GPIO_56\"),\n+\tPINCTRL_PIN(57, \"GPIO_57\"),\n+\tPINCTRL_PIN(58, \"GPIO_58\"),\n+\tPINCTRL_PIN(59, \"GPIO_59\"),\n+\tPINCTRL_PIN(60, \"GPIO_60\"),\n+\tPINCTRL_PIN(61, \"GPIO_61\"),\n+\tPINCTRL_PIN(62, \"GPIO_62\"),\n+\tPINCTRL_PIN(63, \"GPIO_63\"),\n+\tPINCTRL_PIN(64, \"GPIO_64\"),\n+\tPINCTRL_PIN(65, \"GPIO_65\"),\n+\tPINCTRL_PIN(66, \"GPIO_66\"),\n+\tPINCTRL_PIN(67, \"GPIO_67\"),\n+\tPINCTRL_PIN(68, \"GPIO_68\"),\n+\tPINCTRL_PIN(69, \"GPIO_69\"),\n+\tPINCTRL_PIN(70, \"GPIO_70\"),\n+\tPINCTRL_PIN(71, \"GPIO_71\"),\n+\tPINCTRL_PIN(72, \"GPIO_72\"),\n+\tPINCTRL_PIN(73, \"GPIO_73\"),\n+\tPINCTRL_PIN(74, \"GPIO_74\"),\n+\tPINCTRL_PIN(75, \"GPIO_75\"),\n+\tPINCTRL_PIN(76, \"GPIO_76\"),\n+\tPINCTRL_PIN(77, \"GPIO_77\"),\n+\tPINCTRL_PIN(78, \"GPIO_78\"),\n+\tPINCTRL_PIN(79, \"GPIO_79\"),\n+\tPINCTRL_PIN(80, \"GPIO_80\"),\n+\tPINCTRL_PIN(81, \"GPIO_81\"),\n+\tPINCTRL_PIN(82, \"GPIO_82\"),\n+\tPINCTRL_PIN(83, \"GPIO_83\"),\n+\tPINCTRL_PIN(84, \"GPIO_84\"),\n+\tPINCTRL_PIN(85, \"GPIO_85\"),\n+\tPINCTRL_PIN(86, \"GPIO_86\"),\n+\tPINCTRL_PIN(87, \"GPIO_87\"),\n+\tPINCTRL_PIN(88, \"GPIO_88\"),\n+\tPINCTRL_PIN(89, \"GPIO_89\"),\n+\tPINCTRL_PIN(90, \"GPIO_90\"),\n+\tPINCTRL_PIN(91, \"GPIO_91\"),\n+\tPINCTRL_PIN(92, \"GPIO_92\"),\n+\tPINCTRL_PIN(93, \"GPIO_93\"),\n+\tPINCTRL_PIN(94, \"GPIO_94\"),\n+\tPINCTRL_PIN(95, \"GPIO_95\"),\n+\tPINCTRL_PIN(96, \"GPIO_96\"),\n+\tPINCTRL_PIN(97, \"GPIO_97\"),\n+\tPINCTRL_PIN(98, \"GPIO_98\"),\n+\tPINCTRL_PIN(99, \"GPIO_99\"),\n+\tPINCTRL_PIN(100, \"GPIO_100\"),\n+\tPINCTRL_PIN(101, \"GPIO_101\"),\n+\tPINCTRL_PIN(102, \"GPIO_102\"),\n+\tPINCTRL_PIN(103, \"GPIO_103\"),\n+\tPINCTRL_PIN(104, \"GPIO_104\"),\n+\tPINCTRL_PIN(105, \"GPIO_105\"),\n+\tPINCTRL_PIN(106, \"GPIO_106\"),\n+\tPINCTRL_PIN(107, \"GPIO_107\"),\n+\tPINCTRL_PIN(108, \"GPIO_108\"),\n+\tPINCTRL_PIN(109, \"GPIO_109\"),\n+\tPINCTRL_PIN(110, \"GPIO_110\"),\n+\tPINCTRL_PIN(111, \"GPIO_111\"),\n+\tPINCTRL_PIN(112, \"GPIO_112\"),\n+\tPINCTRL_PIN(113, \"GPIO_113\"),\n+\tPINCTRL_PIN(114, \"GPIO_114\"),\n+\tPINCTRL_PIN(115, \"GPIO_115\"),\n+\tPINCTRL_PIN(116, \"GPIO_116\"),\n+\tPINCTRL_PIN(117, \"GPIO_117\"),\n+\tPINCTRL_PIN(118, \"GPIO_118\"),\n+\tPINCTRL_PIN(119, \"GPIO_119\"),\n+\tPINCTRL_PIN(120, \"GPIO_120\"),\n+\tPINCTRL_PIN(121, \"GPIO_121\"),\n+\tPINCTRL_PIN(122, \"GPIO_122\"),\n+\tPINCTRL_PIN(123, \"GPIO_123\"),\n+\tPINCTRL_PIN(124, \"GPIO_124\"),\n+\tPINCTRL_PIN(125, \"GPIO_125\"),\n+\tPINCTRL_PIN(126, \"GPIO_126\"),\n+\tPINCTRL_PIN(127, \"GPIO_127\"),\n+\tPINCTRL_PIN(128, \"GPIO_128\"),\n+\tPINCTRL_PIN(129, \"GPIO_129\"),\n+\tPINCTRL_PIN(130, \"GPIO_130\"),\n+\tPINCTRL_PIN(131, \"GPIO_131\"),\n+\tPINCTRL_PIN(132, \"GPIO_132\"),\n+\tPINCTRL_PIN(133, \"GPIO_133\"),\n+\tPINCTRL_PIN(134, \"GPIO_134\"),\n+\tPINCTRL_PIN(135, \"GPIO_135\"),\n+\tPINCTRL_PIN(136, \"GPIO_136\"),\n+\tPINCTRL_PIN(137, \"GPIO_137\"),\n+\tPINCTRL_PIN(138, \"GPIO_138\"),\n+\tPINCTRL_PIN(139, \"GPIO_139\"),\n+\tPINCTRL_PIN(140, \"GPIO_140\"),\n+\tPINCTRL_PIN(141, \"GPIO_141\"),\n+\tPINCTRL_PIN(142, \"GPIO_142\"),\n+\tPINCTRL_PIN(143, \"GPIO_143\"),\n+\tPINCTRL_PIN(144, \"GPIO_144\"),\n+\tPINCTRL_PIN(145, \"GPIO_145\"),\n+\tPINCTRL_PIN(146, \"GPIO_146\"),\n+\tPINCTRL_PIN(147, \"GPIO_147\"),\n+\tPINCTRL_PIN(148, \"GPIO_148\"),\n+\tPINCTRL_PIN(149, \"GPIO_149\"),\n+\tPINCTRL_PIN(150, \"GPIO_150\"),\n+\tPINCTRL_PIN(151, \"GPIO_151\"),\n+\tPINCTRL_PIN(152, \"GPIO_152\"),\n+\tPINCTRL_PIN(153, \"GPIO_153\"),\n+\tPINCTRL_PIN(154, \"GPIO_154\"),\n+\tPINCTRL_PIN(155, \"GPIO_155\"),\n+\tPINCTRL_PIN(156, \"GPIO_156\"),\n+\tPINCTRL_PIN(157, \"GPIO_157\"),\n+\tPINCTRL_PIN(158, \"GPIO_158\"),\n+\tPINCTRL_PIN(159, \"GPIO_159\"),\n+\tPINCTRL_PIN(160, \"GPIO_160\"),\n+\tPINCTRL_PIN(161, \"GPIO_161\"),\n+\tPINCTRL_PIN(162, \"GPIO_162\"),\n+\tPINCTRL_PIN(163, \"GPIO_163\"),\n+\tPINCTRL_PIN(164, \"GPIO_164\"),\n+\tPINCTRL_PIN(165, \"GPIO_165\"),\n+\tPINCTRL_PIN(166, \"SDC1_RCLK\"),\n+\tPINCTRL_PIN(167, \"SDC1_CLK\"),\n+\tPINCTRL_PIN(168, \"SDC1_CMD\"),\n+\tPINCTRL_PIN(169, \"SDC1_DATA\"),\n+\tPINCTRL_PIN(170, \"SDC2_CLK\"),\n+\tPINCTRL_PIN(171, \"SDC2_CMD\"),\n+\tPINCTRL_PIN(172, \"SDC2_DATA\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+DECLARE_MSM_GPIO_PINS(47);\n+DECLARE_MSM_GPIO_PINS(48);\n+DECLARE_MSM_GPIO_PINS(49);\n+DECLARE_MSM_GPIO_PINS(50);\n+DECLARE_MSM_GPIO_PINS(51);\n+DECLARE_MSM_GPIO_PINS(52);\n+DECLARE_MSM_GPIO_PINS(53);\n+DECLARE_MSM_GPIO_PINS(54);\n+DECLARE_MSM_GPIO_PINS(55);\n+DECLARE_MSM_GPIO_PINS(56);\n+DECLARE_MSM_GPIO_PINS(57);\n+DECLARE_MSM_GPIO_PINS(58);\n+DECLARE_MSM_GPIO_PINS(59);\n+DECLARE_MSM_GPIO_PINS(60);\n+DECLARE_MSM_GPIO_PINS(61);\n+DECLARE_MSM_GPIO_PINS(62);\n+DECLARE_MSM_GPIO_PINS(63);\n+DECLARE_MSM_GPIO_PINS(64);\n+DECLARE_MSM_GPIO_PINS(65);\n+DECLARE_MSM_GPIO_PINS(66);\n+DECLARE_MSM_GPIO_PINS(67);\n+DECLARE_MSM_GPIO_PINS(68);\n+DECLARE_MSM_GPIO_PINS(69);\n+DECLARE_MSM_GPIO_PINS(70);\n+DECLARE_MSM_GPIO_PINS(71);\n+DECLARE_MSM_GPIO_PINS(72);\n+DECLARE_MSM_GPIO_PINS(73);\n+DECLARE_MSM_GPIO_PINS(74);\n+DECLARE_MSM_GPIO_PINS(75);\n+DECLARE_MSM_GPIO_PINS(76);\n+DECLARE_MSM_GPIO_PINS(77);\n+DECLARE_MSM_GPIO_PINS(78);\n+DECLARE_MSM_GPIO_PINS(79);\n+DECLARE_MSM_GPIO_PINS(80);\n+DECLARE_MSM_GPIO_PINS(81);\n+DECLARE_MSM_GPIO_PINS(82);\n+DECLARE_MSM_GPIO_PINS(83);\n+DECLARE_MSM_GPIO_PINS(84);\n+DECLARE_MSM_GPIO_PINS(85);\n+DECLARE_MSM_GPIO_PINS(86);\n+DECLARE_MSM_GPIO_PINS(87);\n+DECLARE_MSM_GPIO_PINS(88);\n+DECLARE_MSM_GPIO_PINS(89);\n+DECLARE_MSM_GPIO_PINS(90);\n+DECLARE_MSM_GPIO_PINS(91);\n+DECLARE_MSM_GPIO_PINS(92);\n+DECLARE_MSM_GPIO_PINS(93);\n+DECLARE_MSM_GPIO_PINS(94);\n+DECLARE_MSM_GPIO_PINS(95);\n+DECLARE_MSM_GPIO_PINS(96);\n+DECLARE_MSM_GPIO_PINS(97);\n+DECLARE_MSM_GPIO_PINS(98);\n+DECLARE_MSM_GPIO_PINS(99);\n+DECLARE_MSM_GPIO_PINS(100);\n+DECLARE_MSM_GPIO_PINS(101);\n+DECLARE_MSM_GPIO_PINS(102);\n+DECLARE_MSM_GPIO_PINS(103);\n+DECLARE_MSM_GPIO_PINS(104);\n+DECLARE_MSM_GPIO_PINS(105);\n+DECLARE_MSM_GPIO_PINS(106);\n+DECLARE_MSM_GPIO_PINS(107);\n+DECLARE_MSM_GPIO_PINS(108);\n+DECLARE_MSM_GPIO_PINS(109);\n+DECLARE_MSM_GPIO_PINS(110);\n+DECLARE_MSM_GPIO_PINS(111);\n+DECLARE_MSM_GPIO_PINS(112);\n+DECLARE_MSM_GPIO_PINS(113);\n+DECLARE_MSM_GPIO_PINS(114);\n+DECLARE_MSM_GPIO_PINS(115);\n+DECLARE_MSM_GPIO_PINS(116);\n+DECLARE_MSM_GPIO_PINS(117);\n+DECLARE_MSM_GPIO_PINS(118);\n+DECLARE_MSM_GPIO_PINS(119);\n+DECLARE_MSM_GPIO_PINS(120);\n+DECLARE_MSM_GPIO_PINS(121);\n+DECLARE_MSM_GPIO_PINS(122);\n+DECLARE_MSM_GPIO_PINS(123);\n+DECLARE_MSM_GPIO_PINS(124);\n+DECLARE_MSM_GPIO_PINS(125);\n+DECLARE_MSM_GPIO_PINS(126);\n+DECLARE_MSM_GPIO_PINS(127);\n+DECLARE_MSM_GPIO_PINS(128);\n+DECLARE_MSM_GPIO_PINS(129);\n+DECLARE_MSM_GPIO_PINS(130);\n+DECLARE_MSM_GPIO_PINS(131);\n+DECLARE_MSM_GPIO_PINS(132);\n+DECLARE_MSM_GPIO_PINS(133);\n+DECLARE_MSM_GPIO_PINS(134);\n+DECLARE_MSM_GPIO_PINS(135);\n+DECLARE_MSM_GPIO_PINS(136);\n+DECLARE_MSM_GPIO_PINS(137);\n+DECLARE_MSM_GPIO_PINS(138);\n+DECLARE_MSM_GPIO_PINS(139);\n+DECLARE_MSM_GPIO_PINS(140);\n+DECLARE_MSM_GPIO_PINS(141);\n+DECLARE_MSM_GPIO_PINS(142);\n+DECLARE_MSM_GPIO_PINS(143);\n+DECLARE_MSM_GPIO_PINS(144);\n+DECLARE_MSM_GPIO_PINS(145);\n+DECLARE_MSM_GPIO_PINS(146);\n+DECLARE_MSM_GPIO_PINS(147);\n+DECLARE_MSM_GPIO_PINS(148);\n+DECLARE_MSM_GPIO_PINS(149);\n+DECLARE_MSM_GPIO_PINS(150);\n+DECLARE_MSM_GPIO_PINS(151);\n+DECLARE_MSM_GPIO_PINS(152);\n+DECLARE_MSM_GPIO_PINS(153);\n+DECLARE_MSM_GPIO_PINS(154);\n+DECLARE_MSM_GPIO_PINS(155);\n+DECLARE_MSM_GPIO_PINS(156);\n+DECLARE_MSM_GPIO_PINS(157);\n+DECLARE_MSM_GPIO_PINS(158);\n+DECLARE_MSM_GPIO_PINS(159);\n+DECLARE_MSM_GPIO_PINS(160);\n+DECLARE_MSM_GPIO_PINS(161);\n+DECLARE_MSM_GPIO_PINS(162);\n+DECLARE_MSM_GPIO_PINS(163);\n+DECLARE_MSM_GPIO_PINS(164);\n+DECLARE_MSM_GPIO_PINS(165);\n+\n+static const unsigned int sdc1_rclk_pins[] = { 166 };\n+static const unsigned int sdc1_clk_pins[] = { 167 };\n+static const unsigned int sdc1_cmd_pins[] = { 168 };\n+static const unsigned int sdc1_data_pins[] = { 169 };\n+static const unsigned int sdc2_clk_pins[] = { 170 };\n+static const unsigned int sdc2_cmd_pins[] = { 171 };\n+static const unsigned int sdc2_data_pins[] = { 172 };\n+\n+enum shikra_functions {\n+\tmsm_mux_gpio,\n+\tmsm_mux_agera_pll,\n+\tmsm_mux_atest_bbrx,\n+\tmsm_mux_atest_char,\n+\tmsm_mux_atest_gpsadc,\n+\tmsm_mux_atest_tsens,\n+\tmsm_mux_atest_usb,\n+\tmsm_mux_cam_mclk,\n+\tmsm_mux_cci_async,\n+\tmsm_mux_cci_i2c0,\n+\tmsm_mux_cci_i2c1,\n+\tmsm_mux_cci_timer,\n+\tmsm_mux_char_exec,\n+\tmsm_mux_cri_trng,\n+\tmsm_mux_dac_calib,\n+\tmsm_mux_dbg_out_clk,\n+\tmsm_mux_ddr_bist,\n+\tmsm_mux_ddr_pxi,\n+\tmsm_mux_dmic,\n+\tmsm_mux_emac_dll,\n+\tmsm_mux_emac_mcg,\n+\tmsm_mux_emac_phy,\n+\tmsm_mux_emac0_ptp_aux,\n+\tmsm_mux_emac0_ptp_pps,\n+\tmsm_mux_emac1_ptp_aux,\n+\tmsm_mux_emac1_ptp_pps,\n+\tmsm_mux_ext_mclk,\n+\tmsm_mux_gcc_gp,\n+\tmsm_mux_gsm0_tx,\n+\tmsm_mux_i2s0,\n+\tmsm_mux_i2s1,\n+\tmsm_mux_i2s2,\n+\tmsm_mux_i2s3,\n+\tmsm_mux_jitter_bist,\n+\tmsm_mux_m_voc,\n+\tmsm_mux_mdp_vsync_e,\n+\tmsm_mux_mdp_vsync_out0,\n+\tmsm_mux_mdp_vsync_out1,\n+\tmsm_mux_mdp_vsync_p,\n+\tmsm_mux_mdp_vsync_s,\n+\tmsm_mux_mpm_pwr,\n+\tmsm_mux_mss_lte,\n+\tmsm_mux_nav_gpio,\n+\tmsm_mux_pa_indicator_or,\n+\tmsm_mux_pbs_in,\n+\tmsm_mux_pbs_out,\n+\tmsm_mux_pcie0_clk_req_n,\n+\tmsm_mux_phase_flag,\n+\tmsm_mux_pll,\n+\tmsm_mux_prng_rosc,\n+\tmsm_mux_pwm,\n+\tmsm_mux_qdss_cti,\n+\tmsm_mux_qup0_se0,\n+\tmsm_mux_qup0_se1,\n+\tmsm_mux_qup0_se1_01,\n+\tmsm_mux_qup0_se1_23,\n+\tmsm_mux_qup0_se2,\n+\tmsm_mux_qup0_se3_01,\n+\tmsm_mux_qup0_se3_23,\n+\tmsm_mux_qup0_se4_01,\n+\tmsm_mux_qup0_se4_23,\n+\tmsm_mux_qup0_se5,\n+\tmsm_mux_qup0_se6,\n+\tmsm_mux_qup0_se7_01,\n+\tmsm_mux_qup0_se7_23,\n+\tmsm_mux_qup0_se8,\n+\tmsm_mux_qup0_se9,\n+\tmsm_mux_qup0_se9_01,\n+\tmsm_mux_qup0_se9_23,\n+\tmsm_mux_rgmii,\n+\tmsm_mux_sd_write_protect,\n+\tmsm_mux_sdc_cdc,\n+\tmsm_mux_sdc_tb_trig,\n+\tmsm_mux_ssbi_wtr,\n+\tmsm_mux_swr0_rx,\n+\tmsm_mux_swr0_tx,\n+\tmsm_mux_tgu_ch_trigout,\n+\tmsm_mux_tsc_async,\n+\tmsm_mux_tsense_pwm,\n+\tmsm_mux_uim1,\n+\tmsm_mux_uim2,\n+\tmsm_mux_unused_adsp,\n+\tmsm_mux_unused_gsm1,\n+\tmsm_mux_usb0_phy_ps,\n+\tmsm_mux_vfr,\n+\tmsm_mux_vsense_trigger_mirnat,\n+\tmsm_mux_wlan,\n+\tmsm_mux__,\n+};\n+\n+static const char *const gpio_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\",\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\",\n+\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\",\n+\t\"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\", \"gpio22\", \"gpio23\",\n+\t\"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\", \"gpio29\",\n+\t\"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\",\n+\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\",\n+\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\",\n+\t\"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\", \"gpio58\", \"gpio59\",\n+\t\"gpio60\", \"gpio61\", \"gpio62\", \"gpio63\", \"gpio64\", \"gpio65\",\n+\t\"gpio66\", \"gpio67\", \"gpio68\", \"gpio69\", \"gpio70\", \"gpio71\",\n+\t\"gpio72\", \"gpio73\", \"gpio74\", \"gpio75\", \"gpio76\", \"gpio77\",\n+\t\"gpio78\", \"gpio79\", \"gpio80\", \"gpio81\", \"gpio82\", \"gpio83\",\n+\t\"gpio84\", \"gpio85\", \"gpio86\", \"gpio87\", \"gpio88\", \"gpio89\",\n+\t\"gpio90\", \"gpio91\", \"gpio92\", \"gpio93\", \"gpio94\", \"gpio95\",\n+\t\"gpio96\", \"gpio97\", \"gpio98\", \"gpio99\", \"gpio100\", \"gpio101\",\n+\t\"gpio102\", \"gpio103\", \"gpio104\", \"gpio105\", \"gpio106\", \"gpio107\",\n+\t\"gpio108\", \"gpio109\", \"gpio110\", \"gpio111\", \"gpio112\", \"gpio113\",\n+\t\"gpio114\", \"gpio115\", \"gpio116\", \"gpio117\", \"gpio118\", \"gpio119\",\n+\t\"gpio120\", \"gpio121\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\",\n+\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\", \"gpio130\", \"gpio131\",\n+\t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio136\", \"gpio137\",\n+\t\"gpio138\", \"gpio139\", \"gpio140\", \"gpio141\", \"gpio142\", \"gpio143\",\n+\t\"gpio144\", \"gpio145\", \"gpio146\", \"gpio147\", \"gpio148\", \"gpio149\",\n+\t\"gpio150\", \"gpio151\", \"gpio152\", \"gpio153\", \"gpio154\", \"gpio155\",\n+\t\"gpio156\", \"gpio157\", \"gpio158\", \"gpio159\", \"gpio160\", \"gpio161\",\n+\t\"gpio162\", \"gpio163\", \"gpio164\", \"gpio165\",\n+};\n+\n+static const char *const agera_pll_groups[] = {\n+\t\"gpio22\", \"gpio23\",\n+};\n+\n+static const char *const atest_bbrx_groups[] = {\n+\t\"gpio58\", \"gpio59\",\n+};\n+\n+static const char *const atest_char_groups[] = {\n+\t\"gpio56\", \"gpio57\", \"gpio54\", \"gpio55\", \"gpio62\",\n+};\n+\n+static const char *const atest_gpsadc_groups[] = {\n+\t\"gpio60\", \"gpio96\",\n+};\n+\n+static const char *const atest_tsens_groups[] = {\n+\t\"gpio1\", \"gpio2\",\n+};\n+\n+static const char *const atest_usb_groups[] = {\n+\t\"gpio53\", \"gpio58\", \"gpio59\", \"gpio60\", \"gpio61\", \"gpio96\",\n+\t\"gpio98\", \"gpio99\", \"gpio100\", \"gpio101\",\n+};\n+\n+static const char *const cam_mclk_groups[] = {\n+\t\"gpio34\", \"gpio35\", \"gpio96\", \"gpio98\",\n+};\n+\n+static const char *const cci_async_groups[] = {\n+\t\"gpio39\",\n+};\n+\n+static const char *const cci_i2c0_groups[] = {\n+\t\"gpio36\", \"gpio37\",\n+};\n+\n+static const char *const cci_i2c1_groups[] = {\n+\t\"gpio41\", \"gpio42\",\n+};\n+\n+static const char *const cci_timer_groups[] = {\n+\t\"gpio38\", \"gpio40\", \"gpio43\", \"gpio47\",\n+};\n+\n+static const char *const char_exec_groups[] = {\n+\t\"gpio12\", \"gpio13\",\n+};\n+\n+static const char *const cri_trng_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio20\",\n+};\n+\n+static const char *const dac_calib_groups[] = {\n+\t\"gpio3\", \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\", \"gpio8\",\n+\t\"gpio9\", \"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\",\n+\t\"gpio19\", \"gpio63\", \"gpio64\", \"gpio66\", \"gpio68\", \"gpio69\",\n+\t\"gpio70\", \"gpio88\", \"gpio89\", \"gpio90\", \"gpio97\", \"gpio116\",\n+\t\"gpio117\", \"gpio118\",\n+};\n+\n+static const char *const dbg_out_clk_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char *const ddr_bist_groups[] = {\n+\t\"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\",\n+};\n+\n+static const char *const ddr_pxi_groups[] = {\n+\t\"gpio98\", \"gpio99\", \"gpio100\", \"gpio101\",\n+};\n+\n+static const char *const dmic_groups[] = {\n+\t\"gpio96\", \"gpio97\", \"gpio98\", \"gpio99\",\n+};\n+\n+static const char *const emac_dll_groups[] = {\n+\t\"gpio58\", \"gpio59\", \"gpio60\", \"gpio61\",\n+};\n+\n+static const char *const emac_mcg_groups[] = {\n+\t\"gpio28\", \"gpio29\", \"gpio40\", \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\"gpio46\", \"gpio47\",\n+};\n+\n+static const char *const emac_phy_groups[] = {\n+\t\"gpio120\", \"gpio136\",\n+};\n+\n+static const char *const emac0_ptp_aux_groups[] = {\n+\t\"gpio60\", \"gpio63\", \"gpio69\", \"gpio85\",\n+};\n+\n+static const char *const emac0_ptp_pps_groups[] = {\n+\t\"gpio60\", \"gpio63\", \"gpio69\", \"gpio85\",\n+};\n+\n+static const char *const emac1_ptp_aux_groups[] = {\n+\t\"gpio31\", \"gpio33\", \"gpio60\", \"gpio68\",\n+};\n+\n+static const char *const emac1_ptp_pps_groups[] = {\n+\t\"gpio31\", \"gpio33\", \"gpio60\", \"gpio68\",\n+};\n+\n+static const char *const ext_mclk_groups[] = {\n+\t\"gpio103\", \"gpio104\", \"gpio110\", \"gpio114\",\n+};\n+\n+static const char *const gcc_gp_groups[] = {\n+\t\"gpio45\", \"gpio53\", \"gpio61\", \"gpio88\", \"gpio89\", \"gpio110\",\n+};\n+\n+static const char *const gsm0_tx_groups[] = {\n+\t\"gpio75\",\n+};\n+\n+static const char *const i2s0_groups[] = {\n+\t\"gpio105\", \"gpio106\", \"gpio107\", \"gpio108\", \"gpio109\", \"gpio110\",\n+};\n+\n+static const char *const i2s1_groups[] = {\n+\t\"gpio96\", \"gpio97\", \"gpio98\", \"gpio99\",\n+};\n+\n+static const char *const i2s2_groups[] = {\n+\t\"gpio100\", \"gpio101\", \"gpio102\", \"gpio103\",\n+};\n+\n+static const char *const i2s3_groups[] = {\n+\t\"gpio111\", \"gpio112\", \"gpio113\", \"gpio114\",\n+};\n+\n+static const char *const jitter_bist_groups[] = {\n+\t\"gpio96\", \"gpio99\",\n+};\n+\n+static const char *const m_voc_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char *const mdp_vsync_e_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const mdp_vsync_out0_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const mdp_vsync_out1_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const mdp_vsync_p_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const mdp_vsync_s_groups[] = {\n+\t\"gpio95\",\n+};\n+\n+static const char *const mpm_pwr_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char *const mss_lte_groups[] = {\n+\t\"gpio115\", \"gpio116\",\n+};\n+\n+static const char *const nav_gpio_groups[] = {\n+\t\"gpio53\", \"gpio58\", \"gpio63\", \"gpio71\", \"gpio91\", \"gpio92\",\n+\t\"gpio95\", \"gpio100\", \"gpio101\", \"gpio104\",\n+};\n+\n+static const char *const pa_indicator_or_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char *const pbs_in_groups[] = {\n+\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\", \"gpio53\", \"gpio54\",\n+\t\"gpio55\", \"gpio56\", \"gpio57\", \"gpio58\", \"gpio59\", \"gpio60\",\n+\t\"gpio61\", \"gpio62\", \"gpio63\", \"gpio74\",\n+};\n+\n+static const char *const pbs_out_groups[] = {\n+\t\"gpio22\", \"gpio23\", \"gpio24\",\n+};\n+\n+static const char *const pcie0_clk_req_n_groups[] = {\n+\t\"gpio117\",\n+};\n+\n+static const char *const phase_flag_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\",\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio11\", \"gpio16\",\n+\t\"gpio17\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio48\",\n+\t\"gpio49\", \"gpio50\", \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\",\n+\t\"gpio62\", \"gpio63\", \"gpio64\", \"gpio69\", \"gpio70\", \"gpio71\",\n+\t\"gpio72\", \"gpio74\", \"gpio102\",\n+};\n+\n+static const char *const pll_groups[] = {\n+\t\"gpio14\", \"gpio22\", \"gpio43\", \"gpio44\", \"gpio74\", \"gpio76\",\n+};\n+\n+static const char *const prng_rosc_groups[] = {\n+\t\"gpio27\", \"gpio28\",\n+};\n+\n+static const char *const pwm_groups[] = {\n+\t\"gpio32\", \"gpio40\", \"gpio45\", \"gpio53\", \"gpio54\", \"gpio55\",\n+\t\"gpio56\", \"gpio57\", \"gpio58\", \"gpio61\", \"gpio62\", \"gpio68\",\n+\t\"gpio77\", \"gpio79\", \"gpio80\", \"gpio87\", \"gpio102\"\n+};\n+\n+static const char *const qdss_cti_groups[] = {\n+\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio94\", \"gpio95\",\n+};\n+\n+static const char *const qup0_se0_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+};\n+\n+static const char *const qup0_se1_groups[] = {\n+\t\"gpio28\", \"gpio29\",\n+};\n+\n+static const char *const qup0_se1_01_groups[] = {\n+\t\"gpio4\", \"gpio5\",\n+};\n+\n+static const char *const qup0_se1_23_groups[] = {\n+\t\"gpio4\", \"gpio5\",\n+};\n+\n+static const char *const qup0_se2_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio30\", \"gpio31\",\n+};\n+\n+static const char *const qup0_se3_01_groups[] = {\n+\t\"gpio10\", \"gpio11\",\n+};\n+\n+static const char *const qup0_se3_23_groups[] = {\n+\t\"gpio10\", \"gpio11\",\n+};\n+\n+static const char *const qup0_se4_01_groups[] = {\n+\t\"gpio12\", \"gpio13\",\n+};\n+\n+static const char *const qup0_se4_23_groups[] = {\n+\t\"gpio12\", \"gpio13\",\n+};\n+\n+static const char *const qup0_se5_groups[] = {\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\",\n+};\n+\n+static const char *const qup0_se6_groups[] = {\n+\t\"gpio18\", \"gpio19\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\",\n+};\n+\n+static const char *const qup0_se7_01_groups[] = {\n+\t\"gpio20\", \"gpio21\",\n+};\n+\n+static const char *const qup0_se7_23_groups[] = {\n+\t\"gpio20\", \"gpio21\",\n+};\n+\n+static const char *const qup0_se8_groups[] = {\n+\t\"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\",\n+};\n+\n+static const char *const qup0_se9_groups[] = {\n+\t\"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\",\n+};\n+\n+static const char *const qup0_se9_01_groups[] = {\n+\t\"gpio26\", \"gpio27\",\n+};\n+\n+static const char *const qup0_se9_23_groups[] = {\n+\t\"gpio26\", \"gpio27\",\n+};\n+\n+static const char *const rgmii_groups[] = {\n+\t\"gpio121\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\", \"gpio126\",\n+\t\"gpio127\", \"gpio128\", \"gpio129\", \"gpio130\", \"gpio131\", \"gpio132\",\n+\t\"gpio133\", \"gpio134\", \"gpio137\", \"gpio138\", \"gpio139\", \"gpio140\",\n+\t\"gpio141\", \"gpio142\", \"gpio143\", \"gpio144\", \"gpio145\", \"gpio146\",\n+\t\"gpio147\", \"gpio148\", \"gpio149\", \"gpio150\",\n+};\n+\n+static const char *const sd_write_protect_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const sdc_cdc_groups[] = {\n+\t\"gpio98\", \"gpio99\", \"gpio100\", \"gpio101\",\n+};\n+\n+static const char *const sdc_tb_trig_groups[] = {\n+\t\"gpio32\", \"gpio33\",\n+};\n+\n+static const char *const ssbi_wtr_groups[] = {\n+\t\"gpio68\", \"gpio69\", \"gpio70\", \"gpio71\",\n+};\n+\n+static const char *const swr0_rx_groups[] = {\n+\t\"gpio107\", \"gpio108\", \"gpio109\",\n+};\n+\n+static const char *const swr0_tx_groups[] = {\n+\t\"gpio105\", \"gpio106\",\n+};\n+\n+static const char *const tgu_ch_trigout_groups[] = {\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\",\n+};\n+\n+static const char *const tsc_async_groups[] = {\n+\t\"gpio45\", \"gpio46\",\n+};\n+\n+static const char *const tsense_pwm_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char *const uim1_groups[] = {\n+\t\"gpio81\", \"gpio82\", \"gpio83\", \"gpio84\",\n+};\n+\n+static const char *const uim2_groups[] = {\n+\t\"gpio77\", \"gpio78\", \"gpio79\", \"gpio80\",\n+};\n+\n+static const char *const unused_adsp_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const unused_gsm1_groups[] = {\n+\t\"gpio64\",\n+};\n+\n+static const char *const usb0_phy_ps_groups[] = {\n+\t\"gpio90\",\n+};\n+\n+static const char *const vfr_groups[] = {\n+\t\"gpio59\",\n+};\n+\n+static const char *const vsense_trigger_mirnat_groups[] = {\n+\t\"gpio58\",\n+};\n+\n+static const char *const wlan_groups[] = {\n+\t\"gpio14\", \"gpio15\",\n+};\n+\n+static const struct pinfunction shikra_functions[] = {\n+\tMSM_GPIO_PIN_FUNCTION(gpio),\n+\tMSM_PIN_FUNCTION(agera_pll),\n+\tMSM_PIN_FUNCTION(atest_bbrx),\n+\tMSM_PIN_FUNCTION(atest_char),\n+\tMSM_PIN_FUNCTION(atest_gpsadc),\n+\tMSM_PIN_FUNCTION(atest_tsens),\n+\tMSM_PIN_FUNCTION(atest_usb),\n+\tMSM_PIN_FUNCTION(cam_mclk),\n+\tMSM_PIN_FUNCTION(cci_async),\n+\tMSM_PIN_FUNCTION(cci_i2c0),\n+\tMSM_PIN_FUNCTION(cci_i2c1),\n+\tMSM_PIN_FUNCTION(cci_timer),\n+\tMSM_PIN_FUNCTION(char_exec),\n+\tMSM_PIN_FUNCTION(cri_trng),\n+\tMSM_PIN_FUNCTION(dac_calib),\n+\tMSM_PIN_FUNCTION(dbg_out_clk),\n+\tMSM_PIN_FUNCTION(ddr_bist),\n+\tMSM_PIN_FUNCTION(ddr_pxi),\n+\tMSM_PIN_FUNCTION(dmic),\n+\tMSM_PIN_FUNCTION(emac_dll),\n+\tMSM_PIN_FUNCTION(emac_mcg),\n+\tMSM_PIN_FUNCTION(emac_phy),\n+\tMSM_PIN_FUNCTION(emac0_ptp_aux),\n+\tMSM_PIN_FUNCTION(emac0_ptp_pps),\n+\tMSM_PIN_FUNCTION(emac1_ptp_aux),\n+\tMSM_PIN_FUNCTION(emac1_ptp_pps),\n+\tMSM_PIN_FUNCTION(ext_mclk),\n+\tMSM_PIN_FUNCTION(gcc_gp),\n+\tMSM_PIN_FUNCTION(gsm0_tx),\n+\tMSM_PIN_FUNCTION(i2s0),\n+\tMSM_PIN_FUNCTION(i2s1),\n+\tMSM_PIN_FUNCTION(i2s2),\n+\tMSM_PIN_FUNCTION(i2s3),\n+\tMSM_PIN_FUNCTION(jitter_bist),\n+\tMSM_PIN_FUNCTION(m_voc),\n+\tMSM_PIN_FUNCTION(mdp_vsync_e),\n+\tMSM_PIN_FUNCTION(mdp_vsync_out0),\n+\tMSM_PIN_FUNCTION(mdp_vsync_out1),\n+\tMSM_PIN_FUNCTION(mdp_vsync_p),\n+\tMSM_PIN_FUNCTION(mdp_vsync_s),\n+\tMSM_PIN_FUNCTION(mpm_pwr),\n+\tMSM_PIN_FUNCTION(mss_lte),\n+\tMSM_PIN_FUNCTION(nav_gpio),\n+\tMSM_PIN_FUNCTION(pa_indicator_or),\n+\tMSM_PIN_FUNCTION(pbs_in),\n+\tMSM_PIN_FUNCTION(pbs_out),\n+\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n+\tMSM_PIN_FUNCTION(phase_flag),\n+\tMSM_PIN_FUNCTION(pll),\n+\tMSM_PIN_FUNCTION(prng_rosc),\n+\tMSM_PIN_FUNCTION(pwm),\n+\tMSM_PIN_FUNCTION(qdss_cti),\n+\tMSM_PIN_FUNCTION(qup0_se0),\n+\tMSM_PIN_FUNCTION(qup0_se1),\n+\tMSM_PIN_FUNCTION(qup0_se1_01),\n+\tMSM_PIN_FUNCTION(qup0_se1_23),\n+\tMSM_PIN_FUNCTION(qup0_se2),\n+\tMSM_PIN_FUNCTION(qup0_se3_01),\n+\tMSM_PIN_FUNCTION(qup0_se3_23),\n+\tMSM_PIN_FUNCTION(qup0_se4_01),\n+\tMSM_PIN_FUNCTION(qup0_se4_23),\n+\tMSM_PIN_FUNCTION(qup0_se5),\n+\tMSM_PIN_FUNCTION(qup0_se6),\n+\tMSM_PIN_FUNCTION(qup0_se7_01),\n+\tMSM_PIN_FUNCTION(qup0_se7_23),\n+\tMSM_PIN_FUNCTION(qup0_se8),\n+\tMSM_PIN_FUNCTION(qup0_se9),\n+\tMSM_PIN_FUNCTION(qup0_se9_01),\n+\tMSM_PIN_FUNCTION(qup0_se9_23),\n+\tMSM_PIN_FUNCTION(rgmii),\n+\tMSM_PIN_FUNCTION(sd_write_protect),\n+\tMSM_PIN_FUNCTION(sdc_cdc),\n+\tMSM_PIN_FUNCTION(sdc_tb_trig),\n+\tMSM_PIN_FUNCTION(ssbi_wtr),\n+\tMSM_PIN_FUNCTION(swr0_rx),\n+\tMSM_PIN_FUNCTION(swr0_tx),\n+\tMSM_PIN_FUNCTION(tgu_ch_trigout),\n+\tMSM_PIN_FUNCTION(tsc_async),\n+\tMSM_PIN_FUNCTION(tsense_pwm),\n+\tMSM_PIN_FUNCTION(uim1),\n+\tMSM_PIN_FUNCTION(uim2),\n+\tMSM_PIN_FUNCTION(unused_adsp),\n+\tMSM_PIN_FUNCTION(unused_gsm1),\n+\tMSM_PIN_FUNCTION(usb0_phy_ps),\n+\tMSM_PIN_FUNCTION(vfr),\n+\tMSM_PIN_FUNCTION(vsense_trigger_mirnat),\n+\tMSM_PIN_FUNCTION(wlan),\n+};\n+\n+static const struct msm_pingroup shikra_groups[] = {\n+\t[0] = PINGROUP(0, qup0_se0, m_voc, _, phase_flag, _, _, _, _, _, _, _),\n+\t[1] = PINGROUP(1, qup0_se0, mpm_pwr, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _),\n+\t[2] = PINGROUP(2, qup0_se0, ddr_bist, _, phase_flag, atest_tsens, _, _, _, _, _, _),\n+\t[3] = PINGROUP(3, qup0_se0, ddr_bist, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[4] = PINGROUP(4, qup0_se1_23, qup0_se1_01, ddr_bist, _, phase_flag, dac_calib, _, _, _,\n+\t\t _, _),\n+\t[5] = PINGROUP(5, qup0_se1_23, qup0_se1_01, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[6] = PINGROUP(6, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[7] = PINGROUP(7, qup0_se2, cri_trng, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[8] = PINGROUP(8, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),\n+\t[9] = PINGROUP(9, qup0_se2, _, phase_flag, dac_calib, _, _, _, _, _, _, _),\n+\t[10] = PINGROUP(10, qup0_se3_01, qup0_se3_23, _, _, _, _, _, _, _, _, _),\n+\t[11] = PINGROUP(11, qup0_se3_01, qup0_se3_23, _, phase_flag, _, _, _, _, _, _, _),\n+\t[12] = PINGROUP(12, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),\n+\t[13] = PINGROUP(13, qup0_se4_01, qup0_se4_23, char_exec, _, _, _, _, _, _, _, _),\n+\t[14] = PINGROUP(14, qup0_se5, pll, tgu_ch_trigout, dac_calib, wlan, _, _, _, _, _, _),\n+\t[15] = PINGROUP(15, qup0_se5, tgu_ch_trigout, _, dac_calib, wlan, _, _, _, _, _, _),\n+\t[16] = PINGROUP(16, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[17] = PINGROUP(17, qup0_se5, tgu_ch_trigout, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[18] = PINGROUP(18, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),\n+\t[19] = PINGROUP(19, qup0_se6, dac_calib, _, _, _, _, _, _, _, _, _),\n+\t[20] = PINGROUP(20, qup0_se7_01, qup0_se7_23, cri_trng, _, _, _, _, _, _, _, _),\n+\t[21] = PINGROUP(21, qup0_se7_01, qup0_se7_23, tsense_pwm, _, _, _, _, _, _, _, _),\n+\t[22] = PINGROUP(22, qup0_se8, pll, agera_pll, pbs_out, _, _, _, _, _, _, _),\n+\t[23] = PINGROUP(23, qup0_se8, agera_pll, pbs_out, _, _, _, _, _, _, _, _),\n+\t[24] = PINGROUP(24, qup0_se8, pbs_out, _, _, _, _, _, _, _, _, _),\n+\t[25] = PINGROUP(25, qup0_se8, _, _, _, _, _, _, _, _, _, _),\n+\t[26] = PINGROUP(26, qup0_se9_23, qup0_se9_01, _, _, _, _, _, _, _, _, _),\n+\t[27] = PINGROUP(27, qup0_se9_23, qup0_se9_01, prng_rosc, _, _, _, _, _, _, _, _),\n+\t[28] = PINGROUP(28, qup0_se1, qup0_se6, emac_mcg, prng_rosc, _, phase_flag, qdss_cti,\n+\t\t\t_, _, _, _),\n+\t[29] = PINGROUP(29, qup0_se1, qup0_se6, emac_mcg, _, phase_flag, qdss_cti, _, _, _, _, _),\n+\t[30] = PINGROUP(30, qup0_se2, qup0_se6, _, phase_flag, qdss_cti, _, _, _, _, _, _),\n+\t[31] = PINGROUP(31, qup0_se2, qup0_se6, emac1_ptp_aux, emac1_ptp_pps, _, phase_flag,\n+\t\t\tqdss_cti, _, _, _, _),\n+\t[32] = PINGROUP(32, pwm, sdc_tb_trig, _, _, _, _, _, _, _, _, _),\n+\t[33] = PINGROUP(33, emac1_ptp_aux, emac1_ptp_pps, sdc_tb_trig, _, _, _, _, _, _, _, _),\n+\t[34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _, _, _, _, _),\n+\t[35] = PINGROUP(35, cam_mclk, unused_adsp, _, _, _, _, _, _, _, _, _),\n+\t[36] = PINGROUP(36, cci_i2c0, _, _, _, _, _, _, _, _, _, _),\n+\t[37] = PINGROUP(37, cci_i2c0, _, _, _, _, _, _, _, _, _, _),\n+\t[38] = PINGROUP(38, cci_timer, _, _, _, _, _, _, _, _, _, _),\n+\t[39] = PINGROUP(39, cci_async, _, _, _, _, _, _, _, _, _, _),\n+\t[40] = PINGROUP(40, cci_timer, emac_mcg, pwm, _, _, _, _, _, _, _, _),\n+\t[41] = PINGROUP(41, cci_i2c1, _, _, _, _, _, _, _, _, _, _),\n+\t[42] = PINGROUP(42, cci_i2c1, _, _, _, _, _, _, _, _, _, _),\n+\t[43] = PINGROUP(43, cci_timer, emac_mcg, pll, _, _, _, _, _, _, _, _),\n+\t[44] = PINGROUP(44, emac_mcg, pll, _, _, _, _, _, _, _, _, _),\n+\t[45] = PINGROUP(45, tsc_async, emac_mcg, pwm, gcc_gp, _, _, _, _, _, _, _),\n+\t[46] = PINGROUP(46, tsc_async, emac_mcg, _, _, _, _, _, _, _, _, _),\n+\t[47] = PINGROUP(47, cci_timer, emac_mcg, _, _, _, _, _, _, _, _, _),\n+\t[48] = PINGROUP(48, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),\n+\t[49] = PINGROUP(49, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),\n+\t[50] = PINGROUP(50, _, qup0_se9, _, _, pbs_in, phase_flag, _, _, _, _, _),\n+\t[51] = PINGROUP(51, _, qup0_se9, pbs_in, _, _, _, _, _, _, _, _),\n+\t[52] = PINGROUP(52, _, _, _, _, _, _, _, _, _, _, _),\n+\t[53] = PINGROUP(53, _, nav_gpio, gcc_gp, pwm, _, pbs_in, atest_usb, _, _, _, _),\n+\t[54] = PINGROUP(54, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),\n+\t[55] = PINGROUP(55, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),\n+\t[56] = PINGROUP(56, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),\n+\t[57] = PINGROUP(57, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),\n+\t[58] = PINGROUP(58, _, nav_gpio, pwm, _, pbs_in, atest_bbrx, atest_usb,\n+\t\t\tvsense_trigger_mirnat, emac_dll, _, _),\n+\t[59] = PINGROUP(59, _, vfr, _, pbs_in, atest_bbrx, atest_usb, emac_dll, _, _, _, _),\n+\t[60] = PINGROUP(60, _, emac1_ptp_aux, emac1_ptp_pps, emac0_ptp_aux, emac0_ptp_pps, _,\n+\t\t\tpbs_in, atest_gpsadc, atest_usb, emac_dll, _),\n+\t[61] = PINGROUP(61, _, pwm, gcc_gp, pa_indicator_or, dbg_out_clk, pbs_in, atest_usb,\n+\t\t\temac_dll, _, _, _),\n+\t[62] = PINGROUP(62, _, pwm, _, pbs_in, phase_flag, atest_char, _, _, _, _, _),\n+\t[63] = PINGROUP(63, _, nav_gpio, emac0_ptp_aux, emac0_ptp_pps, _, pbs_in, phase_flag,\n+\t\t\tdac_calib, _, _, _),\n+\t[64] = PINGROUP(64, _, unused_gsm1, dac_calib, _, _, _, _, _, _, _, _),\n+\t[65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _),\n+\t[66] = PINGROUP(66, _, dac_calib, _, _, _, _, _, _, _, _, _),\n+\t[67] = PINGROUP(67, _, _, _, _, _, _, _, _, _, _, _),\n+\t[68] = PINGROUP(68, _, ssbi_wtr, emac1_ptp_aux, emac1_ptp_pps, pwm, dac_calib, _, _, _,\n+\t\t\t_, _),\n+\t[69] = PINGROUP(69, _, ssbi_wtr, emac0_ptp_aux, emac0_ptp_pps, _, phase_flag, dac_calib,\n+\t\t\t_, _, _, _),\n+\t[70] = PINGROUP(70, _, ssbi_wtr, _, phase_flag, dac_calib, _, _, _, _, _, _),\n+\t[71] = PINGROUP(71, _, ssbi_wtr, nav_gpio, _, phase_flag, _, _, _, _, _, _),\n+\t[72] = PINGROUP(72, _, _, phase_flag, _, _, _, _, _, _, _, _),\n+\t[73] = PINGROUP(73, _, _, _, _, _, _, _, _, _, _, _),\n+\t[74] = PINGROUP(74, pll, _, pbs_in, phase_flag, _, _, _, _, _, _, _),\n+\t[75] = PINGROUP(75, gsm0_tx, _, _, _, _, _, _, _, _, _, _),\n+\t[76] = PINGROUP(76, pll, _, _, _, _, _, _, _, _, _, _),\n+\t[77] = PINGROUP(77, uim2, pwm, _, _, _, _, _, _, _, _, _),\n+\t[78] = PINGROUP(78, uim2, _, _, _, _, _, _, _, _, _, _),\n+\t[79] = PINGROUP(79, uim2, pwm, _, _, _, _, _, _, _, _, _),\n+\t[80] = PINGROUP(80, uim2, pwm, _, _, _, _, _, _, _, _, _),\n+\t[81] = PINGROUP(81, uim1, _, _, _, _, _, _, _, _, _, _),\n+\t[82] = PINGROUP(82, uim1, _, _, _, _, _, _, _, _, _, _),\n+\t[83] = PINGROUP(83, uim1, _, _, _, _, _, _, _, _, _, _),\n+\t[84] = PINGROUP(84, uim1, _, _, _, _, _, _, _, _, _, _),\n+\t[85] = PINGROUP(85, emac0_ptp_aux, emac0_ptp_pps, _, _, _, _, _, _, _, _, _),\n+\t[86] = PINGROUP(86, mdp_vsync_p, mdp_vsync_out0, mdp_vsync_out1, _, _, _, _, _, _, _, _),\n+\t[87] = PINGROUP(87, _, pwm, _, _, _, _, _, _, _, _, _),\n+\t[88] = PINGROUP(88, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),\n+\t[89] = PINGROUP(89, gcc_gp, _, dac_calib, _, _, _, _, _, _, _, _),\n+\t[90] = PINGROUP(90, usb0_phy_ps, _, dac_calib, _, _, _, _, _, _, _, _),\n+\t[91] = PINGROUP(91, nav_gpio, _, _, _, _, _, _, _, _, _, _),\n+\t[92] = PINGROUP(92, nav_gpio, _, _, _, _, _, _, _, _, _, _),\n+\t[93] = PINGROUP(93, _, _, _, _, _, _, _, _, _, _, _),\n+\t[94] = PINGROUP(94, mdp_vsync_e, qdss_cti, qdss_cti, _, _, _, _, _, _, _, _),\n+\t[95] = PINGROUP(95, nav_gpio, mdp_vsync_s, qdss_cti, qdss_cti, _, _, _, _, _, _, _),\n+\t[96] = PINGROUP(96, dmic, cam_mclk, i2s1, jitter_bist, atest_gpsadc, atest_usb, _, _, _,\n+\t\t\t_, _),\n+\t[97] = PINGROUP(97, dmic, i2s1, dac_calib, _, _, _, _, _, _, _, _),\n+\t[98] = PINGROUP(98, dmic, cam_mclk, i2s1, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _),\n+\t[99] = PINGROUP(99, dmic, i2s1, jitter_bist, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),\n+\t[100] = PINGROUP(100, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),\n+\t[101] = PINGROUP(101, i2s2, nav_gpio, _, sdc_cdc, atest_usb, ddr_pxi, _, _, _, _, _),\n+\t[102] = PINGROUP(102, i2s2, pwm, _, phase_flag, _, _, _, _, _, _, _),\n+\t[103] = PINGROUP(103, ext_mclk, i2s2, _, _, _, _, _, _, _, _, _),\n+\t[104] = PINGROUP(104, ext_mclk, nav_gpio, _, _, _, _, _, _, _, _, _),\n+\t[105] = PINGROUP(105, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),\n+\t[106] = PINGROUP(106, swr0_tx, i2s0, _, _, _, _, _, _, _, _, _),\n+\t[107] = PINGROUP(107, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),\n+\t[108] = PINGROUP(108, swr0_rx, i2s0, _, _, _, _, _, _, _, _, _),\n+\t[109] = PINGROUP(109, swr0_rx, i2s0, sd_write_protect, _, _, _, _, _, _, _, _),\n+\t[110] = PINGROUP(110, ext_mclk, i2s0, _, gcc_gp, _, _, _, _, _, _, _),\n+\t[111] = PINGROUP(111, i2s3, _, _, _, _, _, _, _, _, _, _),\n+\t[112] = PINGROUP(112, i2s3, _, _, _, _, _, _, _, _, _, _),\n+\t[113] = PINGROUP(113, i2s3, _, _, _, _, _, _, _, _, _, _),\n+\t[114] = PINGROUP(114, ext_mclk, i2s3, _, _, _, _, _, _, _, _, _),\n+\t[115] = PINGROUP(115, mss_lte, _, _, _, _, _, _, _, _, _, _),\n+\t[116] = PINGROUP(116, mss_lte, _, dac_calib, _, _, _, _, _, _, _, _),\n+\t[117] = PINGROUP(117, pcie0_clk_req_n, _, dac_calib, _, _, _, _, _, _, _, _),\n+\t[118] = PINGROUP(118, _, dac_calib, _, _, _, _, _, _, _, _, _),\n+\t[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _),\n+\t[120] = PINGROUP(120, emac_phy, _, _, _, _, _, _, _, _, _, _),\n+\t[121] = PINGROUP(121, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[122] = PINGROUP(122, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[123] = PINGROUP(123, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[124] = PINGROUP(124, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[125] = PINGROUP(125, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[126] = PINGROUP(126, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[127] = PINGROUP(127, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[128] = PINGROUP(128, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[129] = PINGROUP(129, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[130] = PINGROUP(130, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[131] = PINGROUP(131, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[132] = PINGROUP(132, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[133] = PINGROUP(133, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[134] = PINGROUP(134, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, _),\n+\t[136] = PINGROUP(136, emac_phy, _, _, _, _, _, _, _, _, _, _),\n+\t[137] = PINGROUP(137, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[138] = PINGROUP(138, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[139] = PINGROUP(139, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[140] = PINGROUP(140, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[141] = PINGROUP(141, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[142] = PINGROUP(142, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[143] = PINGROUP(143, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[144] = PINGROUP(144, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[145] = PINGROUP(145, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[146] = PINGROUP(146, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[147] = PINGROUP(147, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[148] = PINGROUP(148, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[149] = PINGROUP(149, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[150] = PINGROUP(150, rgmii, _, _, _, _, _, _, _, _, _, _),\n+\t[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, _),\n+\t[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, _),\n+\t[153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, _),\n+\t[154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _),\n+\t[155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _),\n+\t[156] = PINGROUP(156, _, _, _, _, _, _, _, _, _, _, _),\n+\t[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),\n+\t[158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _),\n+\t[159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _),\n+\t[160] = PINGROUP(160, _, _, _, _, _, _, _, _, _, _, _),\n+\t[161] = PINGROUP(161, _, _, _, _, _, _, _, _, _, _, _),\n+\t[162] = PINGROUP(162, _, _, _, _, _, _, _, _, _, _, _),\n+\t[163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, _),\n+\t[164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, _),\n+\t[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, _),\n+\t[166] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xac004, 0, 0),\n+\t[167] = SDC_QDSD_PINGROUP(sdc1_clk, 0xac000, 13, 6),\n+\t[168] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xac000, 11, 3),\n+\t[169] = SDC_QDSD_PINGROUP(sdc1_data, 0xac000, 9, 0),\n+\t[170] = SDC_QDSD_PINGROUP(sdc2_clk, 0xaa000, 14, 6),\n+\t[171] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xaa000, 11, 3),\n+\t[172] = SDC_QDSD_PINGROUP(sdc2_data, 0xaa000, 9, 0),\n+};\n+\n+static const struct msm_gpio_wakeirq_map shikra_mpm_map[] = {\n+\t{1, 9}, {2, 31}, {5, 49}, {6, 53}, {9, 72}, {10, 10},\n+\t{12, 22}, {14, 26}, {17, 29}, {18, 24}, {20, 32}, {22, 33},\n+\t{25, 34}, {27, 35}, {28, 36}, {29, 37}, {30, 38}, {31, 39},\n+\t{32, 40}, {33, 41}, {38, 42}, {40, 43}, {43, 44}, {44, 45},\n+\t{45, 46}, {46, 47}, {47, 48}, {48, 60}, {50, 50}, {51, 51},\n+\t{52, 61}, {53, 62}, {57, 52}, {58, 63}, {60, 54}, {63, 64},\n+\t{73, 55}, {74, 56}, {75, 57}, {77, 3}, {80, 4}, {84, 5},\n+\t{85, 67}, {86, 69}, {88, 70}, {89, 71}, {90, 73}, {91, 74},\n+\t{92, 75}, {93, 76}, {94, 77}, {95, 78}, {97, 79}, {99, 80},\n+\t{100, 11}, {101, 13}, {102, 14}, {103, 15}, {106, 16}, {108, 17},\n+\t{112, 18}, {116, 19}, {117, 20}, {119, 21}, {120, 23}, {136, 25},\n+\t{159, 27}, {161, 28},\n+};\n+\n+static const struct msm_pinctrl_soc_data shikra_tlmm = {\n+\t.pins = shikra_pins,\n+\t.npins = ARRAY_SIZE(shikra_pins),\n+\t.functions = shikra_functions,\n+\t.nfunctions = ARRAY_SIZE(shikra_functions),\n+\t.groups = shikra_groups,\n+\t.ngroups = ARRAY_SIZE(shikra_groups),\n+\t.ngpios = 166,\n+\t.wakeirq_map = shikra_mpm_map,\n+\t.nwakeirq_map = ARRAY_SIZE(shikra_mpm_map),\n+\t.egpio_func = 11,\n+};\n+\n+static int shikra_tlmm_probe(struct platform_device *pdev)\n+{\n+\treturn msm_pinctrl_probe(pdev, &shikra_tlmm);\n+}\n+\n+static const struct of_device_id shikra_tlmm_of_match[] = {\n+\t{ .compatible = \"qcom,shikra-tlmm\", .data = &shikra_tlmm },\n+\t{},\n+};\n+\n+static struct platform_driver shikra_tlmm_driver = {\n+\t.driver = {\n+\t\t.name = \"shikra-tlmm\",\n+\t\t.of_match_table = shikra_tlmm_of_match,\n+\t},\n+\t.probe = shikra_tlmm_probe,\n+};\n+\n+static int __init shikra_tlmm_init(void)\n+{\n+\treturn platform_driver_register(&shikra_tlmm_driver);\n+}\n+arch_initcall(shikra_tlmm_init);\n+\n+static void __exit shikra_tlmm_exit(void)\n+{\n+\tplatform_driver_unregister(&shikra_tlmm_driver);\n+}\n+module_exit(shikra_tlmm_exit);\n+\n+MODULE_DESCRIPTION(\"QTI Shikra TLMM driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DEVICE_TABLE(of, shikra_tlmm_of_match);\n", "prefixes": [ "2/2" ] }