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GET /api/1.1/patches/2230116/?format=api
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{
    "id": 2230116,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230116/?format=api",
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        "name": "GNU Compiler Collection",
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        "web_url": null,
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    },
    "msgid": "<20260429093257.62004-1-jinma@linux.alibaba.com>",
    "date": "2026-04-29T09:32:57",
    "name": "RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw pattern [PR???]",
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    "pull_url": null,
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    "submitter": {
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        "name": "Jin Ma",
        "email": "jinma@linux.alibaba.com"
    },
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            "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502024",
            "date": "2026-04-29T09:32:57",
            "name": "RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw pattern [PR???]",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/502024/mbox/"
        }
    ],
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    "checks": "http://patchwork.ozlabs.org/api/patches/2230116/checks/",
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        "From": "Jin Ma <jinma@linux.alibaba.com>",
        "To": "gcc-patches@gcc.gnu.org",
        "Cc": "jeffreyalaw@gmail.com, palmer@dabbelt.com, richard.sandiford@arm.com,\n Jin Ma <jinma@linux.alibaba.com>",
        "Subject": "[PATCH] RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw\n pattern [PR???]",
        "Date": "Wed, 29 Apr 2026 17:32:57 +0800",
        "Message-ID": "<20260429093257.62004-1-jinma@linux.alibaba.com>",
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        "X-BeenThere": "gcc-patches@gcc.gnu.org",
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        "Precedence": "list",
        "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>",
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        "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"
    },
    "content": "The AND case in riscv_rtx_costs for the slli.uw pattern (zba extension)\nhas a multi-statement if body without braces.  This causes the\n'return true' to execute unconditionally whenever the left operand of\nAND is an ASHIFT, regardless of whether the inner condition (checking\nregister_operand, CONST_INT_P, and the 0xffffffff mask) is satisfied.\n\nThis effectively short-circuits the entire AND cost calculation for any\nAND+ASHIFT combination when TARGET_ZBA && TARGET_64BIT && DImode,\nskipping subsequent pattern checks (bclri, bclr, etc.) and the\nfallthrough to PLUS/MINUS.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces\n\taround the if body for the slli.uw pattern in the AND case.\n---\n gcc/config/riscv/riscv.cc | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 97272b4349a..39da4410cd8 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -4377,8 +4377,10 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN\n \t      && CONST_INT_P (ashift_rhs)\n \t      && CONST_INT_P (and_rhs)\n \t      && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))\n-\t    *total = COSTS_N_INSNS (1);\n-\t    return true;\n+\t    {\n+\t      *total = COSTS_N_INSNS (1);\n+\t      return true;\n+\t    }\n \t}\n       /* bclri pattern for zbs.  */\n       if (TARGET_ZBS\n",
    "prefixes": []
}