[{"id":3684937,"web_url":"http://patchwork.ozlabs.org/comment/3684937/","msgid":"","list_archive_url":null,"date":"2026-04-30T20:54:27","subject":"Re: [PATCH] RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw\n pattern [PR???]","submitter":{"id":92871,"url":"http://patchwork.ozlabs.org/api/people/92871/","name":"Jeffrey Law","email":"jefflaw@qti.qualcomm.com"},"content":"On 4/29/2026 3:32 AM, Jin Ma wrote:\n> The AND case in riscv_rtx_costs for the slli.uw pattern (zba extension)\n> has a multi-statement if body without braces. This causes the\n> 'return true' to execute unconditionally whenever the left operand of\n> AND is an ASHIFT, regardless of whether the inner condition (checking\n> register_operand, CONST_INT_P, and the 0xffffffff mask) is satisfied.\n>\n> This effectively short-circuits the entire AND cost calculation for any\n> AND+ASHIFT combination when TARGET_ZBA && TARGET_64BIT && DImode,\n> skipping subsequent pattern checks (bclri, bclr, etc.) and the\n> fallthrough to PLUS/MINUS.\n>\n> gcc/ChangeLog:\n>\n> \t* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces\n> \taround the if body for the slli.uw pattern in the AND case.\nOK.\n\nI'd kind of hoped something would fail in the testsuite which we could \nturn into a test, but it tested cleanly.  It's also worth noting that \nShreya has several fixes into the costing & length estimation space.  \n  For the former she's focused on ALU instructions that reporting a cost \nother than 4 (which is equivalent to 1 fast instruction) for the latter \nshe's focused on cases where the reported length is != 4, but which we \nare encoding with compressed instructions.    So if you're looking at \ncosting or length computation more generally, let me know as we've \nalready got many fixes queued up.\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=eYIjrQuX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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This causes the\n> 'return true' to execute unconditionally whenever the left operand of\n> AND is an ASHIFT, regardless of whether the inner condition (checking\n> register_operand, CONST_INT_P, and the 0xffffffff mask) is satisfied.\n>\n> This effectively short-circuits the entire AND cost calculation for any\n> AND+ASHIFT combination when TARGET_ZBA && TARGET_64BIT && DImode,\n> skipping subsequent pattern checks (bclri, bclr, etc.) and the\n> fallthrough to PLUS/MINUS.\n>\n> gcc/ChangeLog:\n>\n> \t* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces\n> \taround the if body for the slli.uw pattern in the AND case.\nI went ahead and pushed this (trying to clean up the patch queues as I'm \noffline most of next week).\n\njeff","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HXHcTppZ;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=gY+PyO3o;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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