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GET /api/1.1/patches/2229985/?format=api
{ "id": 2229985, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229985/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429035134.1023330-2-happycpu@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429035134.1023330-2-happycpu@gmail.com>", "date": "2026-04-29T03:51:33", "name": "[v2,1/2] dt-bindings: gpio: fairchild,74hc595: add lines-initial-states property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cf72af9aefb2e0936594fe5fca63a54f9672be56", "submitter": { "id": 93205, "url": "http://patchwork.ozlabs.org/api/1.1/people/93205/?format=api", "name": "정찬홍", "email": "happycpu@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429035134.1023330-2-happycpu@gmail.com/mbox/", "series": [ { "id": 501980, "url": "http://patchwork.ozlabs.org/api/1.1/series/501980/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501980", "date": "2026-04-29T03:51:33", "name": "[v2,1/2] dt-bindings: gpio: fairchild,74hc595: add lines-initial-states property", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501980/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229985/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229985/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35745-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ffqmqJpU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35745-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"ffqmqJpU\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.210.176", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g53Nz4HMSz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 13:55:31 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 45AE8307C7C9\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 03:51:48 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 6210338424F;\n\tWed, 29 Apr 2026 03:51:42 +0000 (UTC)", "from mail-pf1-f176.google.com (mail-pf1-f176.google.com\n [209.85.210.176])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 065D23502A4\n\tfor <linux-gpio@vger.kernel.org>; Wed, 29 Apr 2026 03:51:40 +0000 (UTC)", "by mail-pf1-f176.google.com with SMTP id\n d2e1a72fcca58-82f351ca23cso6227861b3a.2\n for <linux-gpio@vger.kernel.org>;\n Tue, 28 Apr 2026 20:51:40 -0700 (PDT)", "from happycpu-p1.. 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Bit N corresponds to GPIO line N. Because the 74HC595/74LVC594\nfamily is push-pull output only (no input mode, no high-impedance state\nunder software control), bit=0 drives the line low and bit=1 drives it\nhigh; this differs from nxp,pcf8575, where the 0/1 polarity reflects the\nquasi-bidirectional nature of that part.\n\nThe bitmask covers up to 32 lines, which fits the typical 1-4 chip\ncascades that appear in tree. Should longer chains require seeding in\nthe future, the property can be extended to a uint32-array without\nbreaking the bit-N-equals-line-N convention.\n\nSuggested-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Chanhong Jung <happycpu@gmail.com>\n---\n .../devicetree/bindings/gpio/fairchild,74hc595.yaml | 13 +++++++++++++\n 1 file changed, 13 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml\nindex 23410aeca..451538df6 100644\n--- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml\n+++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml\n@@ -45,6 +45,18 @@ properties:\n $ref: /schemas/types.yaml#/definitions/uint32\n description: Number of daisy-chained shift registers\n \n+ lines-initial-states:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description:\n+ Bitmask that specifies the initial state of each output line, written\n+ by the driver before the gpiochip is registered. Bit N corresponds to\n+ GPIO line N, following the convention already documented for\n+ nxp,pcf8575. Because the 74HC595/74LVC594 family is push-pull output\n+ only, a bit set to zero drives the line low and a bit set to one\n+ drives it high. The bitmask covers up to 32 lines (four cascaded\n+ registers); outputs beyond that come up zeroed. When the property is\n+ absent all outputs come up low, preserving the previous behaviour.\n+\n enable-gpios:\n description: GPIO connected to the OE (Output Enable) pin.\n maxItems: 1\n@@ -79,6 +91,7 @@ examples:\n gpio-controller;\n #gpio-cells = <2>;\n registers-number = <4>;\n+ lines-initial-states = <0xffff0000>;\n spi-max-frequency = <100000>;\n };\n };\n", "prefixes": [ "v2", "1/2" ] }