[{"id":3684648,"web_url":"http://patchwork.ozlabs.org/comment/3684648/","msgid":"","list_archive_url":null,"date":"2026-04-30T12:08:15","subject":"Re: [PATCH v2 1/2] dt-bindings: gpio: fairchild,74hc595: add\n lines-initial-states property","submitter":{"id":92050,"url":"http://patchwork.ozlabs.org/api/people/92050/","name":"Linus Walleij","email":"linusw@kernel.org"},"content":"On Wed, Apr 29, 2026 at 5:51 AM Chanhong Jung wrote:\n\n> The 74HC595 and 74LVC594 shift registers latch their outputs until the\n> first serial write, so boards that depend on a specific power-on pattern\n> (for example active-low indicators, reset lines, or other signals that\n> must come up non-zero) have no way to express that today: the Linux\n> driver always writes zeros from its zero-initialised buffer during\n> probe.\n>\n> Document support for the existing lines-initial-states bitmask, already\n> defined for nxp,pcf8575, so the same convention covers this output-only\n> device. Bit N corresponds to GPIO line N. Because the 74HC595/74LVC594\n> family is push-pull output only (no input mode, no high-impedance state\n> under software control), bit=0 drives the line low and bit=1 drives it\n> high; this differs from nxp,pcf8575, where the 0/1 polarity reflects the\n> quasi-bidirectional nature of that part.\n>\n> The bitmask covers up to 32 lines, which fits the typical 1-4 chip\n> cascades that appear in tree. Should longer chains require seeding in\n> the future, the property can be extended to a uint32-array without\n> breaking the bit-N-equals-line-N convention.\n>\n> Suggested-by: Linus Walleij \n\nMy old email but who cares.\n\n> Signed-off-by: Chanhong Jung \n\nThis works for me.\nReviewed-by: Linus Walleij \n\nYours,\nLinus Walleij","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=mXFyrHDV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35911-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"mXFyrHDV\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5tLP1cRnz1xqf\n\tfor ; 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Thu, 30 Apr 2026\n 05:08:27 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"\n <20260429035134.1023330-2-happycpu@gmail.com>","In-Reply-To":"<20260429035134.1023330-2-happycpu@gmail.com>","From":"Linus Walleij ","Date":"Thu, 30 Apr 2026 14:08:15 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4I0ki9rGDzmVa6bSPlog4a2U1FZNKcs6D7nH0y5brqxdc8g0KW-DN9bc0E","Message-ID":"\n ","Subject":"Re: [PATCH v2 1/2] dt-bindings: gpio: fairchild,74hc595: add\n lines-initial-states property","To":"Chanhong Jung ","Cc":"Bartosz Golaszewski , Rob Herring ,\n\tKrzysztof Kozlowski , Conor Dooley ,\n\tMaxime Ripard , linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}}]