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GET /api/1.1/patches/2229669/?format=api

HTTP 200 OK
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{
    "id": 2229669,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229669/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-3-mikhail.kshevetskiy@iopsys.eu/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260428153448.980150-3-mikhail.kshevetskiy@iopsys.eu>",
    "date": "2026-04-28T15:34:44",
    "name": "[v2,2/6] pinctrl: airoha: add pin controller and gpio driver for AN7581 SoC",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "c2798d0f53e914e12d9f47be96a124d7a7fe331a",
    "submitter": {
        "id": 84987,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/84987/?format=api",
        "name": "Mikhail Kshevetskiy",
        "email": "mikhail.kshevetskiy@iopsys.eu"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-3-mikhail.kshevetskiy@iopsys.eu/mbox/",
    "series": [
        {
            "id": 501878,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501878/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501878",
            "date": "2026-04-28T15:34:43",
            "name": "pinctrl: add support of Airoha SoCs",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/501878/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2229669/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2229669/checks/",
    "tags": {},
    "headers": {
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        "From": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>",
        "To": "Tom Rini <trini@konsulko.com>, Christian Marangi <ansuelsmth@gmail.com>,\n Simon Glass <sjg@chromium.org>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>, Peng Fan <peng.fan@nxp.com>,\n Sean Anderson <sean.anderson@linux.dev>, Yao Zi <me@ziyao.cc>,\n Michal Simek <michal.simek@amd.com>, Anis Chali <chalianis1@gmail.com>,\n u-boot@lists.denx.de, Lorenzo Bianconi <lorenzo@kernel.org>,\n Markus Gothe <markus.gothe@genexis.eu>,\n Matheus Sampaio Queiroga <srherobrine20@gmail.com>,\n Benjamin Larsson <benjamin.larsson@genexis.eu>,\n David Lechner <dlechner@baylibre.com>",
        "Cc": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>",
        "Subject": "[PATCH v2 2/6] pinctrl: airoha: add pin controller and gpio driver\n for AN7581 SoC",
        "Date": "Tue, 28 Apr 2026 18:34:44 +0300",
        "Message-ID": "<20260428153448.980150-3-mikhail.kshevetskiy@iopsys.eu>",
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    },
    "content": "The driver based on official linux airoha pinctrl and gpio driver with\nMatheus Sampaio Queiroga <srherobrine20@gmail.com> changes.\nThe changes:\n * Separate code for each SoC and keep some of the functions in\n   common between them,\n * Add pinctrl driver for EN7523 SoC.\n\nThe original Matheus Sampaio Queiroga driver can be taken from the repo:\n  https://sirherobrine23.com.br/airoha_an7523/kernel/commits/branch/airoha_an7523_pinctrl\n\nThis patch adds U-Boot pin controller and gpio driver for Airoha AN7581 SoC.\n\nSigned-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>\n---\n drivers/pinctrl/Kconfig                 |    1 +\n drivers/pinctrl/Makefile                |    1 +\n drivers/pinctrl/airoha/Kconfig          |   16 +\n drivers/pinctrl/airoha/Makefile         |    5 +\n drivers/pinctrl/airoha/airoha-common.h  |  513 +++++++++++\n drivers/pinctrl/airoha/pinctrl-airoha.c |  691 +++++++++++++++\n drivers/pinctrl/airoha/pinctrl-an7581.c | 1060 +++++++++++++++++++++++\n 7 files changed, 2287 insertions(+)\n create mode 100644 drivers/pinctrl/airoha/Kconfig\n create mode 100644 drivers/pinctrl/airoha/Makefile\n create mode 100644 drivers/pinctrl/airoha/airoha-common.h\n create mode 100644 drivers/pinctrl/airoha/pinctrl-airoha.c\n create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c",
    "diff": "diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig\nindex 578edbf8168..46a95a1ab6b 100644\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -405,6 +405,7 @@ config SPL_PINCTRL_ZYNQMP\n \n endif\n \n+source \"drivers/pinctrl/airoha/Kconfig\"\n source \"drivers/pinctrl/broadcom/Kconfig\"\n source \"drivers/pinctrl/exynos/Kconfig\"\n source \"drivers/pinctrl/intel/Kconfig\"\ndiff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile\nindex 29fb9b484d0..b03e838ab39 100644\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_PIC32)\t+= pinctrl_pic32.o\n obj-$(CONFIG_PINCTRL_EXYNOS)\t+= exynos/\n obj-$(CONFIG_PINCTRL_K210)\t+= pinctrl-k210.o\n obj-$(CONFIG_PINCTRL_MESON)\t+= meson/\n+obj-$(CONFIG_PINCTRL_AIROHA)\t+= airoha/\n obj-$(CONFIG_PINCTRL_MTK)\t+= mediatek/\n obj-$(CONFIG_PINCTRL_MSCC)\t+= mscc/\n obj-$(CONFIG_ARCH_MVEBU)\t+= mvebu/\ndiff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig\nnew file mode 100644\nindex 00000000000..986d23c2e3d\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/Kconfig\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+\n+config PINCTRL_AIROHA\n+\tdepends on ARCH_AIROHA\n+\tselect PINCTRL_FULL\n+\tselect PINCTRL_GENERIC\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect REGMAP\n+\tselect SYSCON\n+\tbool\n+\n+config PINCTRL_AIROHA_AN7581\n+\ttristate \"AN7581 pin controller and gpio driver\"\n+\tdepends on TARGET_AN7581\n+\tselect PINCTRL_AIROHA\ndiff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile\nnew file mode 100644\nindex 00000000000..909bd9a04d9\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/Makefile\n@@ -0,0 +1,5 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+obj-$(CONFIG_PINCTRL_AIROHA)\t\t+= pinctrl-airoha.o\n+\n+obj-$(CONFIG_PINCTRL_AIROHA_AN7581)\t+= pinctrl-an7581.o\ndiff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h\nnew file mode 100644\nindex 00000000000..21bc9f50083\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/airoha-common.h\n@@ -0,0 +1,513 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+#ifndef __AIROHA_COMMON_HEADER__\n+#define __AIROHA_COMMON_HEADER__\n+\n+#include <linux/types.h>\n+#include <linux/bitops.h>\n+#include <linux/bitfield.h>\n+#include <linux/pinctrl/pinctrl.h>\n+\n+#include <dm/device.h>\n+#include <dm/pinctrl.h>\n+\n+#define PINCTRL_PIN_GROUP(id, table)\t\t\t\t\t\\\n+\tPINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))\n+\n+#define PINCTRL_FUNC_DESC(id, table)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.desc = PINCTRL_PINFUNCTION(id, table##_groups,\t\\\n+\t\t\t\t\t    ARRAY_SIZE(table##_groups)),\\\n+\t\t.groups = table##_func_group,\t\t\t\t\\\n+\t\t.group_size = ARRAY_SIZE(table##_func_group),\t\t\\\n+\t}\n+\n+#define PINCTRL_CONF_DESC(p, offset, mask)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.pin = p,\t\t\t\t\t\t\\\n+\t\t.reg = { offset, mask },\t\t\t\t\\\n+\t}\n+\n+/* MUX */\n+#define AN7581_REG_GPIO_2ND_I2C_MODE\t0x0214\n+#define EN7523_REG_GPIO_2ND_I2C_MODE\t0x0210\n+#define GPIO_MDC_IO_MASTER_MODE_MODE\tBIT(14)\n+#define GPIO_I2C_MASTER_MODE_MODE\tBIT(13)\n+#define GPIO_I2S_MODE_MASK\t\tBIT(12)\n+#define GPIO_I2C_SLAVE_MODE_MODE\tBIT(11)\n+#define GPIO_LAN3_LED1_MODE_MASK\tBIT(10)\n+#define GPIO_LAN3_LED0_MODE_MASK\tBIT(9)\n+#define GPIO_LAN2_LED1_MODE_MASK\tBIT(8)\n+#define GPIO_LAN2_LED0_MODE_MASK\tBIT(7)\n+#define GPIO_LAN1_LED1_MODE_MASK\tBIT(6)\n+#define GPIO_LAN1_LED0_MODE_MASK\tBIT(5)\n+#define GPIO_LAN0_LED1_MODE_MASK\tBIT(4)\n+#define GPIO_LAN0_LED0_MODE_MASK\tBIT(3)\n+#define PON_TOD_1PPS_MODE_MASK\t\tBIT(2)\n+#define GSW_TOD_1PPS_MODE_MASK\t\tBIT(1)\n+#define GPIO_2ND_I2C_MODE_MASK\t\tBIT(0)\n+#define NPU_UART_MODE_MASK\t\tBIT(2)\n+\n+#define REG_GPIO_SPI_CS1_MODE\t\t0x0218\n+#define EN7523_REG_GPIO_SPI_CS1_MODE\t0x0214\n+\n+#define GPIO_PCM_SPI_CS4_MODE_MASK\t\tBIT(21)\n+#define GPIO_PCM_SPI_CS3_MODE_MASK\t\tBIT(20)\n+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK\t\tBIT(19)\n+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK\t\tBIT(18)\n+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK\tBIT(18)\n+#define GPIO_PCM_SPI_CS1_MODE_MASK\t\tBIT(17)\n+#define GPIO_PCM_SPI_MODE_MASK\t\t\tBIT(16)\n+#define GPIO_PCM2_MODE_MASK\t\t\tBIT(13)\n+#define GPIO_PCM1_MODE_MASK\t\t\tBIT(12)\n+#define GPIO_PCM_INT_MODE_MASK\t\t\tBIT(9)\n+#define GPIO_PCM_RESET_MODE_MASK\t\tBIT(8)\n+#define GPIO_SPI_QUAD_MODE_MASK\t\t\tBIT(4)\n+#define GPIO_SPI_CS4_MODE_MASK\t\t\tBIT(3)\n+#define GPIO_SPI_CS3_MODE_MASK\t\t\tBIT(2)\n+#define GPIO_SPI_CS2_MODE_MASK\t\t\tBIT(1)\n+#define GPIO_SPI_CS1_MODE_MASK\t\t\tBIT(0)\n+\n+#define REG_GPIO_PON_MODE\t\t\t0x021c\n+#define EN7523_REG_GPIO_PON_MODE\t\t0x0218\n+#define GPIO_PARALLEL_NAND_MODE_MASK\t\tBIT(14)\n+#define GPIO_SGMII_MDIO_MODE_MASK\t\tBIT(13)\n+#define GPIO_PCIE_RESET2_MASK\t\t\tBIT(12)\n+#define SIPO_RCLK_MODE_MASK\t\t\tBIT(11)\n+#define GPIO_PCIE_RESET1_MASK\t\t\tBIT(10)\n+#define GPIO_PCIE_RESET0_MASK\t\t\tBIT(9)\n+#define GPIO_UART5_MODE_MASK\t\t\tBIT(8)\n+#define GPIO_UART4_MODE_MASK\t\t\tBIT(7)\n+#define GPIO_HSUART_CTS_RTS_MODE_MASK\t\tBIT(6)\n+#define GPIO_HSUART_MODE_MASK\t\t\tBIT(5)\n+#define GPIO_UART2_CTS_RTS_MODE_MASK\t\tBIT(4)\n+#define GPIO_UART2_MODE_MASK\t\t\tBIT(3)\n+#define GPIO_SIPO_MODE_MASK\t\t\tBIT(2)\n+#define GPIO_EMMC_MODE_MASK\t\t\tBIT(1)\n+#define GPIO_PON_MODE_MASK\t\t\tBIT(0)\n+\n+#define REG_NPU_UART_EN\t\t\t0x0224\n+#define EN7523_REG_NPU_UART_EN\t\t0x0220\n+#define JTAG_UDI_EN_MASK\t\tBIT(4)\n+#define JTAG_DFD_EN_MASK\t\tBIT(3)\n+\n+#define REG_FORCE_GPIO_EN\t\t0x0228\n+#define FORCE_GPIO_EN(n)\t\tBIT(n)\n+\n+/* LED MAP */\n+#define REG_LAN_LED0_MAPPING\t\t0x027c\n+#define REG_LAN_LED1_MAPPING\t\t0x0280\n+\n+#define LAN4_LED_MAPPING_MASK\t\tGENMASK(18, 16)\n+#define LAN4_PHY_LED_MAP(_n)\t\tFIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))\n+\n+#define LAN3_LED_MAPPING_MASK\t\tGENMASK(14, 12)\n+#define LAN3_PHY_LED_MAP(_n)\t\tFIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))\n+\n+#define LAN2_LED_MAPPING_MASK\t\tGENMASK(10, 8)\n+#define LAN2_PHY_LED_MAP(_n)\t\tFIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))\n+\n+#define LAN1_LED_MAPPING_MASK\t\tGENMASK(6, 4)\n+#define LAN1_PHY_LED_MAP(_n)\t\tFIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))\n+\n+#define LAN0_LED_MAPPING_MASK\t\tGENMASK(2, 0)\n+#define LAN0_PHY_LED_MAP(_n)\t\tFIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))\n+\n+/* CONF */\n+#define REG_I2C_SDA_E2\t\t\t0x001c\n+#define AN7583_I2C1_SCL_E2_MASK\t\tBIT(16)\n+#define AN7583_I2C1_SDA_E2_MASK\t\tBIT(15)\n+#define SPI_MISO_E2_MASK\t\tBIT(14)\n+#define SPI_MOSI_E2_MASK\t\tBIT(13)\n+#define SPI_CLK_E2_MASK\t\t\tBIT(12)\n+#define SPI_CS0_E2_MASK\t\t\tBIT(11)\n+#define EN7523_SPI_MISO_E2_MASK\t\tBIT(13)\n+#define EN7523_SPI_MOSI_E2_MASK\t\tBIT(12)\n+#define EN7523_SPI_CLK_E2_MASK\t\tBIT(11)\n+#define EN7523_SPI_CS0_E2_MASK\t\tBIT(10)\n+#define PCIE2_RESET_E2_MASK\t\tBIT(10)\n+#define PCIE1_RESET_E2_MASK\t\tBIT(9)\n+#define PCIE0_RESET_E2_MASK\t\tBIT(8)\n+#define AN7583_MDIO_0_E2_MASK\t\tBIT(5)\n+#define AN7583_MDC_0_E2_MASK\t\tBIT(4)\n+#define UART1_RXD_E2_MASK\t\tBIT(3)\n+#define UART1_TXD_E2_MASK\t\tBIT(2)\n+#define I2C_SCL_E2_MASK\t\t\tBIT(1)\n+#define I2C_SDA_E2_MASK\t\t\tBIT(0)\n+\n+#define REG_I2C_SDA_E4\t\t\t0x0020\n+#define AN7583_I2C1_SCL_E4_MASK\t\tBIT(16)\n+#define AN7583_I2C1_SDA_E4_MASK\t\tBIT(15)\n+#define SPI_MISO_E4_MASK\t\tBIT(14)\n+#define SPI_MOSI_E4_MASK\t\tBIT(13)\n+#define SPI_CLK_E4_MASK\t\t\tBIT(12)\n+#define SPI_CS0_E4_MASK\t\t\tBIT(11)\n+#define EN7523_SPI_MISO_E4_MASK\t\tBIT(13)\n+#define EN7523_SPI_MOSI_E4_MASK\t\tBIT(12)\n+#define EN7523_SPI_CLK_E4_MASK\t\tBIT(11)\n+#define EN7523_SPI_CS0_E4_MASK\t\tBIT(10)\n+#define PCIE2_RESET_E4_MASK\t\tBIT(10)\n+#define PCIE1_RESET_E4_MASK\t\tBIT(9)\n+#define PCIE0_RESET_E4_MASK\t\tBIT(8)\n+#define AN7583_MDIO_0_E4_MASK\t\tBIT(5)\n+#define AN7583_MDC_0_E4_MASK\t\tBIT(4)\n+#define UART1_RXD_E4_MASK\t\tBIT(3)\n+#define UART1_TXD_E4_MASK\t\tBIT(2)\n+#define I2C_SCL_E4_MASK\t\t\tBIT(1)\n+#define I2C_SDA_E4_MASK\t\t\tBIT(0)\n+\n+#define REG_GPIO_L_E2\t\t\t0x0024\n+#define REG_GPIO_L_E4\t\t\t0x0028\n+#define REG_GPIO_H_E2\t\t\t0x002c\n+#define REG_GPIO_H_E4\t\t\t0x0030\n+\n+#define REG_I2C_SDA_PU\t\t\t0x0044\n+#define AN7583_I2C1_SCL_PU_MASK\t\tBIT(16)\n+#define AN7583_I2C1_SDA_PU_MASK\t\tBIT(15)\n+#define SPI_MISO_PU_MASK\t\tBIT(14)\n+#define SPI_MOSI_PU_MASK\t\tBIT(13)\n+#define SPI_CLK_PU_MASK\t\t\tBIT(12)\n+#define SPI_CS0_PU_MASK\t\t\tBIT(11)\n+#define EN7523_SPI_MISO_PU_MASK\t\tBIT(13)\n+#define EN7523_SPI_MOSI_PU_MASK\t\tBIT(12)\n+#define EN7523_SPI_CLK_PU_MASK\t\tBIT(11)\n+#define EN7523_SPI_CS0_PU_MASK\t\tBIT(10)\n+#define PCIE2_RESET_PU_MASK\t\tBIT(10)\n+#define PCIE1_RESET_PU_MASK\t\tBIT(9)\n+#define PCIE0_RESET_PU_MASK\t\tBIT(8)\n+#define AN7583_MDIO_0_PU_MASK\t\tBIT(5)\n+#define AN7583_MDC_0_PU_MASK\t\tBIT(4)\n+#define UART1_RXD_PU_MASK\t\tBIT(3)\n+#define UART1_TXD_PU_MASK\t\tBIT(2)\n+#define I2C_SCL_PU_MASK\t\t\tBIT(1)\n+#define I2C_SDA_PU_MASK\t\t\tBIT(0)\n+\n+#define REG_I2C_SDA_PD\t\t\t0x0048\n+#define AN7583_I2C1_SDA_PD_MASK\t\tBIT(16)\n+#define AN7583_I2C1_SCL_PD_MASK\t\tBIT(15)\n+#define SPI_MISO_PD_MASK\t\tBIT(14)\n+#define SPI_MOSI_PD_MASK\t\tBIT(13)\n+#define SPI_CLK_PD_MASK\t\t\tBIT(12)\n+#define SPI_CS0_PD_MASK\t\t\tBIT(11)\n+#define EN7523_SPI_MISO_PD_MASK\t\tBIT(13)\n+#define EN7523_SPI_MOSI_PD_MASK\t\tBIT(12)\n+#define EN7523_SPI_CLK_PD_MASK\t\tBIT(11)\n+#define EN7523_SPI_CS0_PD_MASK\t\tBIT(10)\n+#define PCIE2_RESET_PD_MASK\t\tBIT(10)\n+#define PCIE1_RESET_PD_MASK\t\tBIT(9)\n+#define PCIE0_RESET_PD_MASK\t\tBIT(8)\n+#define AN7583_MDIO_0_PD_MASK\t\tBIT(5)\n+#define AN7583_MDC_0_PD_MASK\t\tBIT(4)\n+#define UART1_RXD_PD_MASK\t\tBIT(3)\n+#define UART1_TXD_PD_MASK\t\tBIT(2)\n+#define I2C_SCL_PD_MASK\t\t\tBIT(1)\n+#define I2C_SDA_PD_MASK\t\t\tBIT(0)\n+\n+#define REG_GPIO_L_PU\t\t\t0x004c\n+#define REG_GPIO_L_PD\t\t\t0x0050\n+#define REG_GPIO_H_PU\t\t\t0x0054\n+#define REG_GPIO_H_PD\t\t\t0x0058\n+\n+#define REG_PCIE_RESET_OD\t\t0x018c\n+#define PCIE2_RESET_OD_MASK\t\tBIT(2)\n+#define PCIE1_RESET_OD_MASK\t\tBIT(1)\n+#define PCIE0_RESET_OD_MASK\t\tBIT(0)\n+\n+/* GPIOs */\n+#define REG_GPIO_CTRL\t\t0x0000\n+#define REG_GPIO_DATA\t\t0x0004\n+#define REG_GPIO_INT\t\t0x0008\n+#define REG_GPIO_INT_EDGE\t0x000c\n+#define REG_GPIO_INT_LEVEL\t0x0010\n+#define REG_GPIO_OE\t\t0x0014\n+#define REG_GPIO_CTRL1\t\t0x0020\n+\n+/* PWM MODE CONF */\n+#define REG_GPIO_FLASH_MODE_CFG\t\t0x0034\n+#define GPIO15_FLASH_MODE_CFG\t\tBIT(15)\n+#define GPIO14_FLASH_MODE_CFG\t\tBIT(14)\n+#define GPIO13_FLASH_MODE_CFG\t\tBIT(13)\n+#define GPIO12_FLASH_MODE_CFG\t\tBIT(12)\n+#define GPIO11_FLASH_MODE_CFG\t\tBIT(11)\n+#define GPIO10_FLASH_MODE_CFG\t\tBIT(10)\n+#define GPIO9_FLASH_MODE_CFG\t\tBIT(9)\n+#define GPIO8_FLASH_MODE_CFG\t\tBIT(8)\n+#define GPIO7_FLASH_MODE_CFG\t\tBIT(7)\n+#define GPIO6_FLASH_MODE_CFG\t\tBIT(6)\n+#define GPIO5_FLASH_MODE_CFG\t\tBIT(5)\n+#define GPIO4_FLASH_MODE_CFG\t\tBIT(4)\n+#define GPIO3_FLASH_MODE_CFG\t\tBIT(3)\n+#define GPIO2_FLASH_MODE_CFG\t\tBIT(2)\n+#define GPIO1_FLASH_MODE_CFG\t\tBIT(1)\n+#define GPIO0_FLASH_MODE_CFG\t\tBIT(0)\n+\n+#define REG_GPIO_CTRL2\t0x0060\n+#define REG_GPIO_CTRL3\t0x0064\n+\n+/* PWM MODE CONF EXT */\n+#define REG_GPIO_FLASH_MODE_CFG_EXT\t0x0068\n+#define GPIO51_FLASH_MODE_CFG\t\tBIT(31)\n+#define GPIO50_FLASH_MODE_CFG\t\tBIT(30)\n+#define GPIO49_FLASH_MODE_CFG\t\tBIT(29)\n+#define GPIO48_FLASH_MODE_CFG\t\tBIT(28)\n+#define GPIO47_FLASH_MODE_CFG\t\tBIT(27)\n+#define GPIO46_FLASH_MODE_CFG\t\tBIT(26)\n+#define GPIO45_FLASH_MODE_CFG\t\tBIT(25)\n+#define GPIO44_FLASH_MODE_CFG\t\tBIT(24)\n+#define GPIO43_FLASH_MODE_CFG\t\tBIT(23)\n+#define GPIO42_FLASH_MODE_CFG\t\tBIT(22)\n+#define GPIO41_FLASH_MODE_CFG\t\tBIT(21)\n+#define GPIO40_FLASH_MODE_CFG\t\tBIT(20)\n+#define GPIO39_FLASH_MODE_CFG\t\tBIT(19)\n+#define GPIO38_FLASH_MODE_CFG\t\tBIT(18)\n+#define GPIO37_FLASH_MODE_CFG\t\tBIT(17)\n+#define GPIO36_FLASH_MODE_CFG\t\tBIT(16)\n+#define GPIO31_FLASH_MODE_CFG\t\tBIT(15)\n+#define GPIO30_FLASH_MODE_CFG\t\tBIT(14)\n+#define GPIO29_FLASH_MODE_CFG\t\tBIT(13)\n+#define GPIO28_FLASH_MODE_CFG\t\tBIT(12)\n+#define GPIO27_FLASH_MODE_CFG\t\tBIT(11)\n+#define GPIO26_FLASH_MODE_CFG\t\tBIT(10)\n+#define GPIO25_FLASH_MODE_CFG\t\tBIT(9)\n+#define GPIO24_FLASH_MODE_CFG\t\tBIT(8)\n+#define GPIO23_FLASH_MODE_CFG\t\tBIT(7)\n+#define GPIO22_FLASH_MODE_CFG\t\tBIT(6)\n+#define GPIO21_FLASH_MODE_CFG\t\tBIT(5)\n+#define GPIO20_FLASH_MODE_CFG\t\tBIT(4)\n+#define GPIO19_FLASH_MODE_CFG\t\tBIT(3)\n+#define GPIO18_FLASH_MODE_CFG\t\tBIT(2)\n+#define GPIO17_FLASH_MODE_CFG\t\tBIT(1)\n+#define GPIO16_FLASH_MODE_CFG\t\tBIT(0)\n+\n+#define REG_GPIO_DATA1\t\t\t0x0070\n+#define REG_GPIO_OE1\t\t\t0x0078\n+#define REG_GPIO_INT1\t\t\t0x007c\n+#define REG_GPIO_INT_EDGE1\t\t0x0080\n+#define REG_GPIO_INT_EDGE2\t\t0x0084\n+#define REG_GPIO_INT_EDGE3\t\t0x0088\n+#define REG_GPIO_INT_LEVEL1\t\t0x008c\n+#define REG_GPIO_INT_LEVEL2\t\t0x0090\n+#define REG_GPIO_INT_LEVEL3\t\t0x0094\n+\n+#define AIROHA_NUM_PINS\t\t\t64\n+#define AIROHA_PIN_BANK_SIZE\t\t(AIROHA_NUM_PINS / 2)\n+#define AIROHA_REG_GPIOCTRL_NUM_PIN\t(AIROHA_NUM_PINS / 4)\n+\n+/* PWM */\n+#define AIROHA_PINCTRL_PWM(gpio, mux_val)\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = (gpio),\t\t\t\t\\\n+\t\t.regmap[0] = {\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_PWM_MUX,\t\t\\\n+\t\t\tREG_GPIO_FLASH_MODE_CFG,\t\\\n+\t\t\t(mux_val),\t\t\t\\\n+\t\t\t(mux_val)\t\t\t\\\n+\t\t},\t\t\t\t\t\\\n+\t\t.regmap_size = 1,\t\t\t\\\n+\t}\t\t\t\t\t\t\\\n+\n+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = (gpio),\t\t\t\t\\\n+\t\t.regmap[0] = {\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_PWM_EXT_MUX,\t\\\n+\t\t\tREG_GPIO_FLASH_MODE_CFG_EXT,\t\\\n+\t\t\t(mux_val),\t\t\t\\\n+\t\t\t(mux_val)\t\t\t\\\n+\t\t},\t\t\t\t\t\\\n+\t\t.regmap_size = 1,\t\t\t\\\n+\t}\t\t\t\t\t\t\\\n+\n+#define AIROHA_PINCTRL_PHY_LED0(variant, gpio, mux_val, map_mask, map_val)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.name = (gpio),\t\t\t\t\t\t\\\n+\t\t.regmap[0] = {\t\t\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n+\t\t\tvariant##_REG_GPIO_2ND_I2C_MODE,\t\t\t\t\\\n+\t\t\t(mux_val),\t\t\t\t\t\\\n+\t\t\t(mux_val),\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.regmap[1] = {\t\t\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n+\t\t\tREG_LAN_LED0_MAPPING,\t\t\t\t\\\n+\t\t\t(map_mask),\t\t\t\t\t\\\n+\t\t\t(map_val),\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.regmap_size = 2,\t\t\t\t\t\\\n+\t}\n+\n+#define AIROHA_PINCTRL_PHY_LED1(variant, gpio, mux_val, map_mask, map_val)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.name = (gpio),\t\t\t\t\t\t\\\n+\t\t.regmap[0] = {\t\t\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n+\t\t\tvariant##_REG_GPIO_2ND_I2C_MODE,\t\t\t\t\\\n+\t\t\t(mux_val),\t\t\t\t\t\\\n+\t\t\t(mux_val),\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.regmap[1] = {\t\t\t\t\t\t\\\n+\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n+\t\t\tREG_LAN_LED1_MAPPING,\t\t\t\t\\\n+\t\t\t(map_mask),\t\t\t\t\t\\\n+\t\t\t(map_val),\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t.regmap_size = 2,\t\t\t\t\t\\\n+\t}\n+\n+#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,\t\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,\t\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,\t\\\n+\t\t\t\t(pin), (val))\n+#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)\t\t\t\\\n+\tairoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,\t\\\n+\t\t\t\t(pin), (val))\n+\n+static const u32 gpio_data_regs[] = {\n+\tREG_GPIO_DATA,\n+\tREG_GPIO_DATA1\n+};\n+\n+static const u32 gpio_out_regs[] = {\n+\tREG_GPIO_OE,\n+\tREG_GPIO_OE1\n+};\n+\n+static const u32 gpio_dir_regs[] = {\n+\tREG_GPIO_CTRL,\n+\tREG_GPIO_CTRL1,\n+\tREG_GPIO_CTRL2,\n+\tREG_GPIO_CTRL3\n+};\n+\n+static const u32 irq_status_regs[] = {\n+\tREG_GPIO_INT,\n+\tREG_GPIO_INT1\n+};\n+\n+static const u32 irq_level_regs[] = {\n+\tREG_GPIO_INT_LEVEL,\n+\tREG_GPIO_INT_LEVEL1,\n+\tREG_GPIO_INT_LEVEL2,\n+\tREG_GPIO_INT_LEVEL3\n+};\n+\n+static const u32 irq_edge_regs[] = {\n+\tREG_GPIO_INT_EDGE,\n+\tREG_GPIO_INT_EDGE1,\n+\tREG_GPIO_INT_EDGE2,\n+\tREG_GPIO_INT_EDGE3\n+};\n+\n+struct airoha_pinctrl_reg {\n+\tu32 offset;\n+\tu32 mask;\n+};\n+\n+enum airoha_pinctrl_mux_func {\n+\tAIROHA_FUNC_MUX,\n+\tAIROHA_FUNC_PWM_MUX,\n+\tAIROHA_FUNC_PWM_EXT_MUX,\n+};\n+\n+struct airoha_pinctrl_func_group {\n+\tconst char *name;\n+\tstruct {\n+\t\tenum airoha_pinctrl_mux_func mux;\n+\t\tu32 offset;\n+\t\tu32 mask;\n+\t\tu32 val;\n+\t} regmap[2];\n+\tint regmap_size;\n+};\n+\n+struct airoha_pinctrl_func {\n+\tconst struct pinfunction desc;\n+\tconst struct airoha_pinctrl_func_group *groups;\n+\tu8 group_size;\n+};\n+\n+struct airoha_pinctrl_conf {\n+\tu32 pin;\n+\tstruct airoha_pinctrl_reg reg;\n+};\n+\n+struct airoha_pinctrl_gpiochip {\n+\tstruct udevice *dev;\n+\n+\t/* gpio */\n+\tconst u32 *data;\n+\tconst u32 *dir;\n+\tconst u32 *out;\n+\t/* irq */\n+\tconst u32 *status;\n+\tconst u32 *level;\n+\tconst u32 *edge;\n+\n+\tu32 irq_type[AIROHA_NUM_PINS];\n+};\n+\n+struct airoha_pinctrl_confs_info {\n+\tconst struct airoha_pinctrl_conf *confs;\n+\tunsigned int num_confs;\n+};\n+\n+enum airoha_pinctrl_confs_type {\n+\tAIROHA_PINCTRL_CONFS_PULLUP,\n+\tAIROHA_PINCTRL_CONFS_PULLDOWN,\n+\tAIROHA_PINCTRL_CONFS_DRIVE_E2,\n+\tAIROHA_PINCTRL_CONFS_DRIVE_E4,\n+\tAIROHA_PINCTRL_CONFS_PCIE_RST_OD,\n+\n+\tAIROHA_PINCTRL_CONFS_MAX,\n+};\n+\n+struct airoha_pinctrl {\n+\tstruct udevice *dev;\n+\tstruct airoha_pinctrl_match_data *data;\n+\n+\tstruct regmap *chip_scu;\n+\tstruct regmap *regmap;\n+\n+\tstruct airoha_pinctrl_gpiochip gpiochip;\n+};\n+\n+struct airoha_pinctrl_match_data {\n+\tconst int gpio_offs;\n+\tconst int gpio_pin_cnt;\n+\tconst struct pinctrl_pin_desc *pins;\n+\tconst unsigned int num_pins;\n+\tconst struct pingroup *grps;\n+\tconst unsigned int num_grps;\n+\tconst struct airoha_pinctrl_func *funcs;\n+\tconst unsigned int num_funcs;\n+\tconst struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];\n+};\n+\n+extern const struct pinctrl_ops airoha_pinctrl_ops;\n+\n+int airoha_pinctrl_probe(struct udevice *dev);\n+int airoha_pinctrl_bind(struct udevice *dev);\n+\n+#endif\ndiff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c\nnew file mode 100644\nindex 00000000000..c8a22792d51\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c\n@@ -0,0 +1,691 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>\n+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>\n+ * Author: Markus Gothe <markus.gothe@genexis.eu>\n+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>\n+ */\n+#include <dm.h>\n+#include <dm/device_compat.h>\n+#include <dm/device-internal.h>\n+#include <dm/lists.h>\n+#include <dm/ofnode.h>\n+#include <asm-generic/gpio.h>\n+#include <dt-bindings/pinctrl/mt65xx.h>\n+#include <regmap.h>\n+\n+#include <syscon.h>\n+#include <asm/arch/scu-regmap.h>\n+\n+#include \"airoha-common.h\"\n+\n+//#define PINCTRL_GET_STATE\n+\n+static int pin_to_gpio(struct airoha_pinctrl *pinctrl, unsigned int pin)\n+{\n+\tstruct airoha_pinctrl_match_data *data = pinctrl->data;\n+\n+\tif ((pin < data->gpio_offs) ||\n+\t    (pin >= data->gpio_offs + data->gpio_pin_cnt))\n+\t\treturn -EINVAL;\n+\n+\treturn pin - data->gpio_offs;\n+}\n+\n+/* gpio callbacks */\n+static int airoha_gpio_set(struct udevice *dev, unsigned int gpio,\n+\t\t\t   int value)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent);\n+\tu32 offset = gpio % AIROHA_PIN_BANK_SIZE;\n+\tu8 index = gpio / AIROHA_PIN_BANK_SIZE;\n+\n+\treturn regmap_update_bits(pinctrl->regmap,\n+\t\t\t\t  pinctrl->gpiochip.data[index],\n+\t\t\t\t  BIT(offset), value ? BIT(offset) : 0);\n+}\n+\n+static int airoha_gpio_get(struct udevice *dev, unsigned int gpio)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent);\n+\tu32 val, pin = gpio % AIROHA_PIN_BANK_SIZE;\n+\tu8 index = gpio / AIROHA_PIN_BANK_SIZE;\n+\tint err;\n+\n+\terr = regmap_read(pinctrl->regmap,\n+\t\t\t  pinctrl->gpiochip.data[index], &val);\n+\n+\treturn err ? err : !!(val & BIT(pin));\n+}\n+\n+static int airoha_gpio_get_direction(struct udevice *dev, unsigned int gpio)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent);\n+\tu32 mask, index, val;\n+\tint err, field_shift;\n+\n+\tfield_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);\n+\tmask = GENMASK(field_shift + 1, field_shift);\n+\tindex = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;\n+\n+\terr = regmap_read(pinctrl->regmap,\n+\t\t\t  pinctrl->gpiochip.dir[index], &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif ((val & mask) > BIT(field_shift))\n+\t\treturn -EINVAL;\n+\n+\treturn (val & mask) ? GPIOF_OUTPUT : GPIOF_INPUT;\n+}\n+\n+static int airoha_gpio_set_direction(struct udevice *dev,\n+\t\t\t\t     unsigned int gpio, bool input)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent);\n+\tu32 mask, index;\n+\tint err, field_shift;\n+\n+\t/* set output enable */\n+\tmask = BIT(gpio % AIROHA_PIN_BANK_SIZE);\n+\tindex = gpio / AIROHA_PIN_BANK_SIZE;\n+\terr = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],\n+\t\t\t\t mask, !input ? mask : 0);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* set direction */\n+\tfield_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);\n+\tmask = GENMASK(field_shift + 1, field_shift);\n+\tindex = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;\n+\n+\treturn regmap_update_bits(pinctrl->regmap,\n+\t\t\t\t  pinctrl->gpiochip.dir[index],\n+\t\t\t\t  mask, !input ? BIT(field_shift) : 0);\n+}\n+\n+static int airoha_gpio_direction_input(struct udevice *dev, unsigned int gpio)\n+{\n+\treturn airoha_gpio_set_direction(dev, gpio, true);\n+}\n+\n+static int airoha_gpio_direction_output(struct udevice *dev, unsigned int gpio,\n+\t\t\t\t\tint val)\n+{\n+\tint err;\n+\n+\terr = airoha_gpio_set_direction(dev, gpio, false);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn airoha_gpio_set(dev, gpio, val);\n+}\n+\n+static int airoha_pinctrl_gpio_probe(struct udevice *dev)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent);\n+\tstruct gpio_dev_priv *uc_priv;\n+\n+\tuc_priv = dev_get_uclass_priv(dev);\n+\tuc_priv->bank_name = \"airoha\";\n+\tuc_priv->gpio_count = pinctrl->data->gpio_pin_cnt;\n+\n+\treturn 0;\n+}\n+\n+static int airoha_pinctrl_gpio_bind(struct udevice *dev)\n+{\n+\tdev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_gpio_ops airoha_pinctrl_gpio_ops = {\n+\t.set_value = airoha_gpio_set,\n+\t.get_value = airoha_gpio_get,\n+\t.get_function = airoha_gpio_get_direction,\n+\t.direction_input = airoha_gpio_direction_input,\n+\t.direction_output = airoha_gpio_direction_output,\n+};\n+\n+static struct driver airoha_pinctrl_gpio_driver = {\n+\t.name = \"airoha_pinctrl_gpio\",\n+\t.id = UCLASS_GPIO,\n+\t.probe = airoha_pinctrl_gpio_probe,\n+\t.bind = airoha_pinctrl_gpio_bind,\n+\t.ops = &airoha_pinctrl_gpio_ops,\n+};\n+\n+static int airoha_gpiochip_register(struct udevice *parent)\n+{\n+\tstruct airoha_pinctrl *pinctrl;\n+\tstruct uclass_driver *drv;\n+\tstruct udevice *dev;\n+\tint ret;\n+\tofnode node;\n+\n+\tdrv = lists_uclass_lookup(UCLASS_GPIO);\n+\tif (!drv)\n+\t\treturn -ENOENT;\n+\n+\t/*\n+\t * Support upstream linux DTSI that define gpio-controller\n+\t * in the root node (instead of a dedicated subnode)\n+\t */\n+\tif (dev_read_bool(parent, \"gpio-controller\")) {\n+\t\tnode = dev_ofnode(parent);\n+\t\tgoto bind;\n+\t}\n+\n+\tret = -ENOENT;\n+\tdev_for_each_subnode(node, parent)\n+\t\tif (ofnode_read_bool(node, \"gpio-controller\")) {\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+bind:\n+\tret = device_bind_with_driver_data(parent, &airoha_pinctrl_gpio_driver,\n+\t\t\t\t\t   \"airoha_pinctrl_gpio\", 0, node,\n+\t\t\t\t\t   &dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tpinctrl = dev_get_priv(parent);\n+\tpinctrl->gpiochip.dev = dev;\n+\n+\treturn 0;\n+}\n+\n+/* pinmux callbacks */\n+static int airoha_pinmux_set_mux(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t unsigned int selector,\n+\t\t\t\t unsigned int group)\n+{\n+\tconst struct airoha_pinctrl_func *func;\n+\tconst struct pingroup *grp;\n+\tint i;\n+\n+\tfunc = &pinctrl->data->funcs[selector];\n+\tgrp = &pinctrl->data->grps[group];\n+\n+\tdev_dbg(pinctrl->dev, \"enable function %s group %s\\n\",\n+\t\tfunc->desc.name, grp->name);\n+\n+\tfor (i = 0; i < func->group_size; i++) {\n+\t\tconst struct airoha_pinctrl_func_group *group;\n+\t\tint j;\n+\n+\t\tgroup = &func->groups[i];\n+\t\tif (strcmp(group->name, grp->name))\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < group->regmap_size; j++) {\n+\t\t\tswitch (group->regmap[j].mux) {\n+\t\t\tcase AIROHA_FUNC_PWM_EXT_MUX:\n+\t\t\tcase AIROHA_FUNC_PWM_MUX:\n+\t\t\t\tregmap_update_bits(pinctrl->regmap,\n+\t\t\t\t\t\t   group->regmap[j].offset,\n+\t\t\t\t\t\t   group->regmap[j].mask,\n+\t\t\t\t\t\t   group->regmap[j].val);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tregmap_update_bits(pinctrl->chip_scu,\n+\t\t\t\t\t\t   group->regmap[j].offset,\n+\t\t\t\t\t\t   group->regmap[j].mask,\n+\t\t\t\t\t\t   group->regmap[j].val);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int airoha_pinmux_set_direction(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t       unsigned int p, bool input)\n+{\n+\tint gpio;\n+\n+\tgpio = pin_to_gpio(pinctrl, p);\n+\tif (gpio < 0)\n+\t\treturn gpio;\n+\n+\treturn airoha_gpio_set_direction(pinctrl->gpiochip.dev, gpio, input);\n+}\n+\n+/* pinconf callbacks */\n+static const struct airoha_pinctrl_reg *\n+airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf,\n+\t\t\t    int conf_size, int pin)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < conf_size; i++) {\n+\t\tif (conf[i].pin == pin)\n+\t\t\treturn &conf[i].reg;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+#if defined(PINCTRL_GET_STATE)\n+static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t   enum airoha_pinctrl_confs_type conf_type,\n+\t\t\t\t   int pin, u32 *val)\n+{\n+\tconst struct airoha_pinctrl_confs_info *confs_info;\n+\tconst struct airoha_pinctrl_reg *reg;\n+\n+\tconfs_info = &pinctrl->data->confs_info[conf_type];\n+\n+\treg = airoha_pinctrl_get_conf_reg(confs_info->confs,\n+\t\t\t\t\t  confs_info->num_confs,\n+\t\t\t\t\t  pin);\n+\tif (!reg)\n+\t\treturn -EINVAL;\n+\n+\tif (regmap_read(pinctrl->chip_scu, reg->offset, val))\n+\t\treturn -EINVAL;\n+\n+\t*val = (*val & reg->mask) >> __ffs(reg->mask);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t   enum airoha_pinctrl_confs_type conf_type,\n+\t\t\t\t   int pin, u32 val)\n+{\n+\tconst struct airoha_pinctrl_confs_info *confs_info;\n+\tconst struct airoha_pinctrl_reg *reg = NULL;\n+\n+\tconfs_info = &pinctrl->data->confs_info[conf_type];\n+\n+\treg = airoha_pinctrl_get_conf_reg(confs_info->confs,\n+\t\t\t\t\t  confs_info->num_confs,\n+\t\t\t\t\t  pin);\n+\tif (!reg)\n+\t\treturn -EINVAL;\n+\n+\tif (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,\n+\t\t\t       val << __ffs(reg->mask)))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+#if defined(PINCTRL_GET_STATE)\n+static int airoha_pinconf_get_direction(struct airoha_pinctrl *pinctrl, u32 p)\n+{\n+\tint gpio;\n+\n+\tgpio = pin_to_gpio(pinctrl, p);\n+\tif (gpio < 0)\n+\t\treturn gpio;\n+\n+\treturn airoha_gpio_get_direction(pinctrl->gpiochip.dev, gpio);\n+}\n+\n+static int airoha_pinconf_get(struct airoha_pinctrl *pinctrl,\n+\t\t\t      unsigned int pin, unsigned long *config)\n+{\n+\tenum pin_config_param param = pinconf_to_config_param(*config);\n+\tu32 arg;\n+\n+\tswitch (param) {\n+\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n+\tcase PIN_CONFIG_BIAS_DISABLE:\n+\tcase PIN_CONFIG_BIAS_PULL_UP: {\n+\t\tu32 pull_up, pull_down;\n+\n+\t\tif (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) ||\n+\t\t    airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (param == PIN_CONFIG_BIAS_PULL_UP &&\n+\t\t    !(pull_up && !pull_down))\n+\t\t\treturn -EINVAL;\n+\t\telse if (param == PIN_CONFIG_BIAS_PULL_DOWN &&\n+\t\t\t !(pull_down && !pull_up))\n+\t\t\treturn -EINVAL;\n+\t\telse if (pull_up || pull_down)\n+\t\t\treturn -EINVAL;\n+\n+\t\targ = 1;\n+\t\tbreak;\n+\t}\n+\tcase PIN_CONFIG_DRIVE_STRENGTH: {\n+\t\tu32 e2, e4;\n+\n+\t\tif (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) ||\n+\t\t    airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4))\n+\t\t\treturn -EINVAL;\n+\n+\t\targ = e4 << 1 | e2;\n+\t\tbreak;\n+\t}\n+\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n+\t\tif (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg))\n+\t\t\treturn -EINVAL;\n+\t\tbreak;\n+\tcase PIN_CONFIG_OUTPUT_ENABLE:\n+\tcase PIN_CONFIG_INPUT_ENABLE:\n+\t\targ = airoha_pinconf_get_direction(pinctrl, pin);\n+\t\tif (arg != param)\n+\t\t\treturn -EINVAL;\n+\n+\t\targ = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\t*config = pinconf_to_config_packed(param, arg);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static int airoha_pinconf_set_pin_value(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t\tunsigned int p, bool value)\n+{\n+\tint gpio;\n+\n+\tgpio = pin_to_gpio(pinctrl, p);\n+\tif (gpio < 0)\n+\t\treturn gpio;\n+\n+\treturn airoha_gpio_set(pinctrl->gpiochip.dev, gpio, value);\n+}\n+\n+static int airoha_pinconf_set(struct airoha_pinctrl *pinctrl,\n+\t\t\t      unsigned int pin, unsigned long *configs,\n+\t\t\t      unsigned int num_configs)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < num_configs; i++) {\n+\t\tu32 param = pinconf_to_config_param(configs[i]);\n+\t\tu32 arg = pinconf_to_config_argument(configs[i]);\n+\n+\t\tswitch (param) {\n+\t\tcase PIN_CONFIG_BIAS_DISABLE:\n+\t\t\tairoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);\n+\t\t\tairoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);\n+\t\t\tbreak;\n+\t\tcase PIN_CONFIG_BIAS_PULL_UP:\n+\t\t\tairoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);\n+\t\t\tairoha_pinctrl_set_pullup_conf(pinctrl, pin, 1);\n+\t\t\tbreak;\n+\t\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n+\t\t\tairoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1);\n+\t\t\tairoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);\n+\t\t\tbreak;\n+\t\tcase PIN_CONFIG_DRIVE_STRENGTH: {\n+\t\t\tu32 e2 = 0, e4 = 0;\n+\n+\t\t\tswitch (arg) {\n+\t\t\tcase MTK_DRIVE_2mA:\n+\t\t\t\tbreak;\n+\t\t\tcase MTK_DRIVE_4mA:\n+\t\t\t\te2 = 1;\n+\t\t\t\tbreak;\n+\t\t\tcase MTK_DRIVE_6mA:\n+\t\t\t\te4 = 1;\n+\t\t\t\tbreak;\n+\t\t\tcase MTK_DRIVE_8mA:\n+\t\t\t\te2 = 1;\n+\t\t\t\te4 = 1;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\n+\t\t\tairoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2);\n+\t\t\tairoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4);\n+\t\t\tbreak;\n+\t\t}\n+\t\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n+\t\t\tairoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg);\n+\t\t\tbreak;\n+\t\tcase PIN_CONFIG_OUTPUT_ENABLE:\n+\t\tcase PIN_CONFIG_INPUT_ENABLE:\n+\t\tcase PIN_CONFIG_OUTPUT: {\n+\t\t\tbool input = param == PIN_CONFIG_INPUT_ENABLE;\n+\t\t\tint err;\n+\n+\t\t\terr = airoha_pinmux_set_direction(pinctrl, pin, input);\n+\t\t\tif (err)\n+\t\t\t\treturn err;\n+\n+\t\t\tif (param == PIN_CONFIG_OUTPUT) {\n+\t\t\t\terr = airoha_pinconf_set_pin_value(pinctrl,\n+\t\t\t\t\t\t\t\t   pin, !!arg);\n+\t\t\t\tif (err)\n+\t\t\t\t\treturn err;\n+\t\t\t}\n+\n+\t\t\tbreak;\n+\t\t}\n+\t\tdefault:\n+\t\t\treturn -ENOTSUPP;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#if defined(PINCTRL_GET_STATE)\n+static int airoha_pinconf_group_get(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t    unsigned int group, unsigned long *config)\n+{\n+\tu32 cur_config = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < pinctrl->data->grps[group].npins; i++) {\n+\t\tif (airoha_pinconf_get(pinctrl,\n+\t\t\t\t       pinctrl->data->grps[group].pins[i],\n+\t\t\t\t       config))\n+\t\t\treturn -ENOTSUPP;\n+\n+\t\tif (i && cur_config != *config)\n+\t\t\treturn -ENOTSUPP;\n+\n+\t\tcur_config = *config;\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static int airoha_pinconf_group_set(struct airoha_pinctrl *pinctrl,\n+\t\t\t\t    unsigned int group, unsigned long *configs,\n+\t\t\t\t    unsigned int num_configs)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < pinctrl->data->grps[group].npins; i++) {\n+\t\tint err;\n+\n+\t\terr = airoha_pinconf_set(pinctrl,\n+\t\t\t\t\t pinctrl->data->grps[group].pins[i],\n+\t\t\t\t\t configs, num_configs);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int airoha_get_pins_count(struct udevice *dev)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->num_pins;\n+}\n+\n+static const char *airoha_get_pin_name(struct udevice *dev, unsigned selector)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->pins[selector].name;\n+}\n+\n+static int airoha_get_groups_count(struct udevice *dev)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->num_grps;\n+}\n+\n+static const char *airoha_get_group_name(struct udevice *dev, unsigned selector)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->grps[selector].name;\n+}\n+\n+static int airoha_get_funcs_count(struct udevice *dev)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->num_funcs;\n+}\n+\n+static const char *airoha_get_func_name(struct udevice *dev, unsigned selector)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\treturn pinctrl->data->funcs[selector].desc.name;\n+}\n+\n+static int airoha_pinmux_group_set(struct udevice *dev, unsigned group_selector,\n+\t\t\t\t   unsigned func_selector)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\tdev_info(dev, \"enabling %s function for pin group %s\\n\",\n+\t\tairoha_get_func_name(dev, func_selector),\n+\t\tairoha_get_group_name(dev, group_selector));\n+\n+\treturn airoha_pinmux_set_mux(pinctrl, func_selector, group_selector);\n+}\n+\n+static int airoha_pinmux_set(struct udevice *dev, unsigned pin_selector,\n+\t\t\t     unsigned func_selector)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\tconst struct airoha_pinctrl_match_data *data = pinctrl->data;\n+\tconst char *pin_name;\n+\tunsigned selector;\n+\n+\tpin_name = data->pins[pin_selector].name;\n+\n+\t/* find group matching the pin_name */\n+\tfor (selector = 0; selector < data->num_grps; selector++) {\n+\t\tif (!strcmp(pin_name, data->grps[selector].name))\n+\t\t\treturn airoha_pinmux_group_set(dev, selector,\n+\t\t\t\t\t\t       func_selector);\n+\t}\n+\n+\treturn -ENOENT;\n+}\n+\n+static const struct pinconf_param airoha_pinconf_params[] = {\n+\t{ \"bias-disable\",     PIN_CONFIG_BIAS_DISABLE,     0 },\n+\t{ \"bias-pull-up\",     PIN_CONFIG_BIAS_PULL_UP,     1 },\n+\t{ \"bias-pull-down\",   PIN_CONFIG_BIAS_PULL_DOWN,   1 },\n+\t{ \"drive-strength\",   PIN_CONFIG_DRIVE_STRENGTH,   0 },\n+\t{ \"drive-open-drain\", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },\n+\t{ \"output-enable\",    PIN_CONFIG_OUTPUT_ENABLE,    1 },\n+\t{ \"input-enable\",     PIN_CONFIG_INPUT_ENABLE,     1 },\n+};\n+\n+static int airoha_pinconf_set_handler(struct udevice *dev, unsigned pin_selector,\n+\t\t\t\t      unsigned param, unsigned argument)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\tunsigned long configs[1] = { param };\n+\tunsigned int pin = pinctrl->data->pins[pin_selector].number;\n+\n+\tdev_info(dev, \"enabling %s=%d property for pin %s\\n\",\n+\t\tairoha_pinconf_params[param].property, argument,\n+\t\tairoha_get_pin_name(dev, pin_selector));\n+\n+\treturn airoha_pinconf_set(pinctrl, pin, configs, 1);\n+}\n+\n+static int airoha_pinconf_group_set_handler(struct udevice *dev, unsigned group_selector,\n+\t\t\t\t\t    unsigned param, unsigned argument)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\tunsigned long configs[1] = { param };\n+\n+\tdev_info(dev, \"enabling %s=%d property for pin group %s\\n\",\n+\t\tairoha_pinconf_params[param].property, argument,\n+\t\tairoha_get_group_name(dev, group_selector));\n+\n+\treturn airoha_pinconf_group_set(pinctrl, group_selector, configs, 1);\n+}\n+\n+const struct pinctrl_ops airoha_pinctrl_ops = {\n+\t.get_pins_count\t\t= airoha_get_pins_count,\n+\t.get_pin_name\t\t= airoha_get_pin_name,\n+\t.get_groups_count\t= airoha_get_groups_count,\n+\t.get_group_name\t\t= airoha_get_group_name,\n+\t.get_functions_count\t= airoha_get_funcs_count,\n+\t.get_function_name\t= airoha_get_func_name,\n+\t.pinmux_set\t\t= airoha_pinmux_set,\n+\t.pinmux_group_set\t= airoha_pinmux_group_set,\n+\n+\t.pinconf_num_params\t= ARRAY_SIZE(airoha_pinconf_params),\n+\t.pinconf_params\t\t= airoha_pinconf_params,\n+\t.pinconf_set\t\t= airoha_pinconf_set_handler,\n+\t.pinconf_group_set\t= airoha_pinconf_group_set_handler,\n+\n+\t.set_state\t\t= pinctrl_generic_set_state,\n+};\n+\n+int airoha_pinctrl_probe(struct udevice *dev)\n+{\n+\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n+\n+\tpinctrl->dev = dev;\n+\tpinctrl->data = (struct airoha_pinctrl_match_data *)dev_get_driver_data(dev);\n+\n+\tpinctrl->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));\n+\tif (IS_ERR(pinctrl->regmap))\n+\t\treturn PTR_ERR(pinctrl->regmap);\n+\n+\tpinctrl->chip_scu = airoha_get_chip_scu_regmap();\n+\tif (IS_ERR(pinctrl->chip_scu))\n+\t\treturn PTR_ERR(pinctrl->chip_scu);\n+\n+\tpinctrl->gpiochip.data   = gpio_data_regs;\n+\tpinctrl->gpiochip.dir    = gpio_dir_regs;\n+\tpinctrl->gpiochip.out    = gpio_out_regs;\n+\tpinctrl->gpiochip.status = irq_status_regs;\n+\tpinctrl->gpiochip.level  = irq_level_regs;\n+\tpinctrl->gpiochip.edge   = irq_edge_regs;\n+\n+\treturn 0;\n+}\n+\n+int airoha_pinctrl_bind(struct udevice *dev)\n+{\n+\t/*\n+\t * Make sure that the pinctrl driver gets probed after binding\n+\t * as on EN7523/AN7581/AN7583 the pinctrl driver is the one that\n+\t * is also registering the GPIO one during probe, so if its not\n+\t * probed GPIO-s are not registered as well.\n+\t */\n+\tdev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);\n+\n+\treturn airoha_gpiochip_register(dev);\n+}\ndiff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c\nnew file mode 100644\nindex 00000000000..c70952e9ba8\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c\n@@ -0,0 +1,1060 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>\n+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>\n+ * Author: Markus Gothe <markus.gothe@genexis.eu>\n+ */\n+#include \"airoha-common.h\"\n+\n+static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };\n+static const int en7581_pon_tod_1pps_pins[] = { 46 };\n+static const int en7581_gsw_tod_1pps_pins[] = { 46 };\n+static const int en7581_sipo_pins[] = { 16, 17 };\n+static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };\n+static const int en7581_mdio_pins[] = { 14, 15 };\n+static const int en7581_uart2_pins[] = { 48, 55 };\n+static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };\n+static const int en7581_hsuart_pins[] = { 28, 29 };\n+static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };\n+static const int en7581_uart4_pins[] = { 38, 39 };\n+static const int en7581_uart5_pins[] = { 18, 19 };\n+static const int en7581_i2c0_pins[] = { 2, 3 };\n+static const int en7581_i2c1_pins[] = { 14, 15 };\n+static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };\n+static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };\n+static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };\n+static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };\n+static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };\n+static const int en7581_spi_quad_pins[] = { 32, 33 };\n+static const int en7581_spi_pins[] = { 4, 5, 6, 7 };\n+static const int en7581_spi_cs1_pins[] = { 34 };\n+static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };\n+static const int en7581_pcm_spi_int_pins[] = { 14 };\n+static const int en7581_pcm_spi_rst_pins[] = { 15 };\n+static const int en7581_pcm_spi_cs1_pins[] = { 43 };\n+static const int en7581_pcm_spi_cs2_pins[] = { 40 };\n+static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };\n+static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };\n+static const int en7581_pcm_spi_cs3_pins[] = { 41 };\n+static const int en7581_pcm_spi_cs4_pins[] = { 42 };\n+static const int en7581_emmc_pins[] = {\n+\t4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37\n+};\n+static const int en7581_pnand_pins[] = { 4,  5,\t 6,  7,\t 30, 31, 32, 33, 34,\n+\t\t\t\t\t 35, 36, 37, 38, 39, 40, 41, 42 };\n+static const int en7581_gpio0_pins[] = { 13 };\n+static const int en7581_gpio1_pins[] = { 14 };\n+static const int en7581_gpio2_pins[] = { 15 };\n+static const int en7581_gpio3_pins[] = { 16 };\n+static const int en7581_gpio4_pins[] = { 17 };\n+static const int en7581_gpio5_pins[] = { 18 };\n+static const int en7581_gpio6_pins[] = { 19 };\n+static const int en7581_gpio7_pins[] = { 20 };\n+static const int en7581_gpio8_pins[] = { 21 };\n+static const int en7581_gpio9_pins[] = { 22 };\n+static const int en7581_gpio10_pins[] = { 23 };\n+static const int en7581_gpio11_pins[] = { 24 };\n+static const int en7581_gpio12_pins[] = { 25 };\n+static const int en7581_gpio13_pins[] = { 26 };\n+static const int en7581_gpio14_pins[] = { 27 };\n+static const int en7581_gpio15_pins[] = { 28 };\n+static const int en7581_gpio16_pins[] = { 29 };\n+static const int en7581_gpio17_pins[] = { 30 };\n+static const int en7581_gpio18_pins[] = { 31 };\n+static const int en7581_gpio19_pins[] = { 32 };\n+static const int en7581_gpio20_pins[] = { 33 };\n+static const int en7581_gpio21_pins[] = { 34 };\n+static const int en7581_gpio22_pins[] = { 35 };\n+static const int en7581_gpio23_pins[] = { 36 };\n+static const int en7581_gpio24_pins[] = { 37 };\n+static const int en7581_gpio25_pins[] = { 38 };\n+static const int en7581_gpio26_pins[] = { 39 };\n+static const int en7581_gpio27_pins[] = { 40 };\n+static const int en7581_gpio28_pins[] = { 41 };\n+static const int en7581_gpio29_pins[] = { 42 };\n+static const int en7581_gpio30_pins[] = { 43 };\n+static const int en7581_gpio31_pins[] = { 44 };\n+static const int en7581_gpio33_pins[] = { 46 };\n+static const int en7581_gpio34_pins[] = { 47 };\n+static const int en7581_gpio35_pins[] = { 48 };\n+static const int en7581_gpio36_pins[] = { 49 };\n+static const int en7581_gpio37_pins[] = { 50 };\n+static const int en7581_gpio38_pins[] = { 51 };\n+static const int en7581_gpio39_pins[] = { 52 };\n+static const int en7581_gpio40_pins[] = { 53 };\n+static const int en7581_gpio41_pins[] = { 54 };\n+static const int en7581_gpio42_pins[] = { 55 };\n+static const int en7581_gpio43_pins[] = { 56 };\n+static const int en7581_gpio44_pins[] = { 57 };\n+static const int en7581_gpio45_pins[] = { 58 };\n+static const int en7581_gpio46_pins[] = { 59 };\n+static const int en7581_pcie_reset0_pins[] = { 61 };\n+static const int en7581_pcie_reset1_pins[] = { 62 };\n+static const int en7581_pcie_reset2_pins[] = { 63 };\n+\n+static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {\n+\tPINCTRL_PIN(0, \"uart1_txd\"),\n+\tPINCTRL_PIN(1, \"uart1_rxd\"),\n+\tPINCTRL_PIN(2, \"i2c_scl\"),\n+\tPINCTRL_PIN(3, \"i2c_sda\"),\n+\tPINCTRL_PIN(4, \"spi_cs0\"),\n+\tPINCTRL_PIN(5, \"spi_clk\"),\n+\tPINCTRL_PIN(6, \"spi_mosi\"),\n+\tPINCTRL_PIN(7, \"spi_miso\"),\n+\tPINCTRL_PIN(13, \"gpio0\"),\n+\tPINCTRL_PIN(14, \"gpio1\"),\n+\tPINCTRL_PIN(15, \"gpio2\"),\n+\tPINCTRL_PIN(16, \"gpio3\"),\n+\tPINCTRL_PIN(17, \"gpio4\"),\n+\tPINCTRL_PIN(18, \"gpio5\"),\n+\tPINCTRL_PIN(19, \"gpio6\"),\n+\tPINCTRL_PIN(20, \"gpio7\"),\n+\tPINCTRL_PIN(21, \"gpio8\"),\n+\tPINCTRL_PIN(22, \"gpio9\"),\n+\tPINCTRL_PIN(23, \"gpio10\"),\n+\tPINCTRL_PIN(24, \"gpio11\"),\n+\tPINCTRL_PIN(25, \"gpio12\"),\n+\tPINCTRL_PIN(26, \"gpio13\"),\n+\tPINCTRL_PIN(27, \"gpio14\"),\n+\tPINCTRL_PIN(28, \"gpio15\"),\n+\tPINCTRL_PIN(29, \"gpio16\"),\n+\tPINCTRL_PIN(30, \"gpio17\"),\n+\tPINCTRL_PIN(31, \"gpio18\"),\n+\tPINCTRL_PIN(32, \"gpio19\"),\n+\tPINCTRL_PIN(33, \"gpio20\"),\n+\tPINCTRL_PIN(34, \"gpio21\"),\n+\tPINCTRL_PIN(35, \"gpio22\"),\n+\tPINCTRL_PIN(36, \"gpio23\"),\n+\tPINCTRL_PIN(37, \"gpio24\"),\n+\tPINCTRL_PIN(38, \"gpio25\"),\n+\tPINCTRL_PIN(39, \"gpio26\"),\n+\tPINCTRL_PIN(40, \"gpio27\"),\n+\tPINCTRL_PIN(41, \"gpio28\"),\n+\tPINCTRL_PIN(42, \"gpio29\"),\n+\tPINCTRL_PIN(43, \"gpio30\"),\n+\tPINCTRL_PIN(44, \"gpio31\"),\n+\tPINCTRL_PIN(45, \"gpio32\"),\n+\tPINCTRL_PIN(46, \"gpio33\"),\n+\tPINCTRL_PIN(47, \"gpio34\"),\n+\tPINCTRL_PIN(48, \"gpio35\"),\n+\tPINCTRL_PIN(49, \"gpio36\"),\n+\tPINCTRL_PIN(50, \"gpio37\"),\n+\tPINCTRL_PIN(51, \"gpio38\"),\n+\tPINCTRL_PIN(52, \"gpio39\"),\n+\tPINCTRL_PIN(53, \"gpio40\"),\n+\tPINCTRL_PIN(54, \"gpio41\"),\n+\tPINCTRL_PIN(55, \"gpio42\"),\n+\tPINCTRL_PIN(56, \"gpio43\"),\n+\tPINCTRL_PIN(57, \"gpio44\"),\n+\tPINCTRL_PIN(58, \"gpio45\"),\n+\tPINCTRL_PIN(59, \"gpio46\"),\n+\tPINCTRL_PIN(61, \"pcie_reset0\"),\n+\tPINCTRL_PIN(62, \"pcie_reset1\"),\n+\tPINCTRL_PIN(63, \"pcie_reset2\"),\n+};\n+\n+static const char *const pon_groups[] = { \"pon\" };\n+static const char *const tod_1pps_groups[] = { \"pon_tod_1pps\", \"gsw_tod_1pps\" };\n+static const char *const sipo_groups[] = { \"sipo\", \"sipo_rclk\" };\n+static const char *const mdio_groups[] = { \"mdio\" };\n+\n+static const char *const uart_groups[] = { \"uart2\",  \"uart2_cts_rts\",\n+\t\t\t\t\t   \"hsuart\", \"hsuart_cts_rts\",\n+\t\t\t\t\t   \"uart4\",  \"uart5\" };\n+static const char *const i2c_groups[] = { \"i2c1\" };\n+static const char *const jtag_groups[] = { \"jtag_udi\", \"jtag_dfd\" };\n+static const char *const pcm_groups[] = { \"pcm1\", \"pcm2\" };\n+static const char *const spi_groups[] = { \"spi_quad\", \"spi_cs1\" };\n+static const char *const pcm_spi_groups[] = {\n+\t\"pcm_spi\",\t    \"pcm_spi_int\",\t\"pcm_spi_rst\", \"pcm_spi_cs1\",\n+\t\"pcm_spi_cs2_p156\", \"pcm_spi_cs2_p128\", \"pcm_spi_cs3\", \"pcm_spi_cs4\"\n+};\n+\n+static const char *const i2s_groups[] = { \"i2s\" };\n+static const char *const emmc_groups[] = { \"emmc\" };\n+static const char *const pnand_groups[] = { \"pnand\" };\n+static const char *const pcie_reset_groups[] = { \"pcie_reset0\", \"pcie_reset1\",\n+\t\t\t\t\t\t \"pcie_reset2\" };\n+\n+static const char *const pwm_groups[] = {\n+\t\"gpio0\",  \"gpio1\",  \"gpio2\",  \"gpio3\",\t\"gpio4\",  \"gpio5\",  \"gpio6\",\n+\t\"gpio7\",  \"gpio8\",  \"gpio9\",  \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\",\n+\t\"gpio21\", \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n+\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio36\", \"gpio37\", \"gpio38\",\n+\t\"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\"gpio46\", \"gpio47\"\n+};\n+static const char *const phy1_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n+static const char *const phy2_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n+static const char *const phy3_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n+static const char *const phy4_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n+static const char *const phy1_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\t\t\t\t\t\"gpio46\" };\n+static const char *const phy2_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\t\t\t\t\t\"gpio46\" };\n+static const char *const phy3_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\t\t\t\t\t\"gpio46\" };\n+static const char *const phy4_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\t\t\t\t\t\"gpio46\" };\n+\n+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),\n+\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),\n+\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),\n+\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),\n+\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),\n+\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),\n+\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),\n+\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),\n+\tPINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),\n+\tPINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),\n+\tPINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),\n+\tPINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),\n+\tPINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),\n+\tPINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),\n+\tPINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),\n+\tPINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),\n+\tPINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),\n+\tPINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),\n+\tPINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),\n+\tPINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),\n+\tPINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),\n+\tPINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),\n+\tPINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),\n+\tPINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),\n+\tPINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),\n+\tPINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),\n+\tPINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),\n+\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),\n+\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),\n+\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),\n+\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),\n+\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),\n+\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),\n+\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),\n+\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),\n+\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),\n+\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),\n+\tPINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),\n+\tPINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),\n+\tPINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),\n+\tPINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),\n+\tPINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),\n+\tPINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),\n+\tPINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),\n+\tPINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),\n+\tPINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),\n+\tPINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),\n+\tPINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),\n+\tPINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),\n+\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),\n+\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),\n+\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {\n+\tPINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),\n+\tPINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),\n+\tPINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_func_group pon_func_group[] = {\n+\t{\n+\t\t.name = \"pon\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_PON_MODE_MASK, GPIO_PON_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {\n+\t{\n+\t\t.name = \"pon_tod_1pps\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t       PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"gsw_tod_1pps\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t       GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group sipo_func_group[] = {\n+\t{\n+\t\t.name = \"sipo\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,\n+\t\t\t       GPIO_SIPO_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"sipo_rclk\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,\n+\t\t\t       GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group mdio_func_group[] = {\n+\t{\n+\t\t.name = \"mdio\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t       GPIO_MDC_IO_MASTER_MODE_MODE,\n+\t\t\t       GPIO_MDC_IO_MASTER_MODE_MODE },\n+\t\t.regmap[1] = { AIROHA_FUNC_MUX, REG_FORCE_GPIO_EN,\n+\t\t\t       FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),\n+\t\t\t       FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) },\n+\t\t.regmap_size = 2,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group uart_func_group[] = {\n+\t{\n+\t\t.name = \"uart2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart2_cts_rts\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_UART2_MODE_MASK |\n+\t\t\t\t       GPIO_UART2_CTS_RTS_MODE_MASK,\n+\t\t\t       GPIO_UART2_MODE_MASK |\n+\t\t\t\t       GPIO_UART2_CTS_RTS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"hsuart\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_HSUART_MODE_MASK |\n+\t\t\t\t       GPIO_HSUART_CTS_RTS_MODE_MASK,\n+\t\t\t       GPIO_HSUART_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"hsuart_cts_rts\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_HSUART_MODE_MASK |\n+\t\t\t\t       GPIO_HSUART_CTS_RTS_MODE_MASK,\n+\t\t\t       GPIO_HSUART_MODE_MASK |\n+\t\t\t\t       GPIO_HSUART_CTS_RTS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_UART4_MODE_MASK, GPIO_UART4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart5\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_UART5_MODE_MASK, GPIO_UART5_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group i2c_func_group[] = {\n+\t{\n+\t\t.name = \"i2c1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t       GPIO_2ND_I2C_MODE_MASK, GPIO_2ND_I2C_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group jtag_func_group[] = {\n+\t{\n+\t\t.name = \"jtag_udi\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN,\n+\t\t\t       JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"jtag_dfd\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN,\n+\t\t\t       JTAG_DFD_EN_MASK, JTAG_DFD_EN_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pcm_func_group[] = {\n+\t{\n+\t\t.name = \"pcm1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group spi_func_group[] = {\n+\t{\n+\t\t.name = \"spi_quad\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_SPI_QUAD_MODE_MASK,\n+\t\t\t       GPIO_SPI_QUAD_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs3\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {\n+\t{\n+\t\t.name = \"pcm_spi\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_MODE_MASK, GPIO_PCM_SPI_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_int\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_rst\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_RESET_MODE_MASK,\n+\t\t\t       GPIO_PCM_RESET_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_CS1_MODE_MASK,\n+\t\t\t       GPIO_PCM_SPI_CS1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs2_p128\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_CS2_MODE_P128_MASK,\n+\t\t\t       GPIO_PCM_SPI_CS2_MODE_P128_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs2_p156\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_CS2_MODE_P156_MASK,\n+\t\t\t       GPIO_PCM_SPI_CS2_MODE_P156_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs3\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_CS3_MODE_MASK,\n+\t\t\t       GPIO_PCM_SPI_CS3_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t       GPIO_PCM_SPI_CS4_MODE_MASK,\n+\t\t\t       GPIO_PCM_SPI_CS4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group i2s_func_group[] = {\n+\t{\n+\t\t.name = \"i2s\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t       GPIO_I2S_MODE_MASK, GPIO_I2S_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group emmc_func_group[] = {\n+\t{\n+\t\t.name = \"emmc\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_EMMC_MODE_MASK, GPIO_EMMC_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pnand_func_group[] = {\n+\t{\n+\t\t.name = \"pnand\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_PARALLEL_NAND_MODE_MASK,\n+\t\t\t       GPIO_PARALLEL_NAND_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {\n+\t{\n+\t\t.name = \"pcie_reset0\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcie_reset1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcie_reset2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t       GPIO_PCIE_RESET2_MASK, GPIO_PCIE_RESET2_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pwm_func_group[] = {\n+\tAIROHA_PINCTRL_PWM(\"gpio0\", GPIO0_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio1\", GPIO1_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio2\", GPIO2_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio3\", GPIO3_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio4\", GPIO4_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio5\", GPIO5_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio6\", GPIO6_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio7\", GPIO7_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio8\", GPIO8_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio9\", GPIO9_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio10\", GPIO10_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio11\", GPIO11_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio12\", GPIO12_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio13\", GPIO13_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio14\", GPIO14_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio15\", GPIO15_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio16\", GPIO16_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio17\", GPIO17_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio18\", GPIO18_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio19\", GPIO19_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio20\", GPIO20_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio21\", GPIO21_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio22\", GPIO22_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio23\", GPIO23_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio24\", GPIO24_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio25\", GPIO25_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio26\", GPIO26_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio27\", GPIO27_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio28\", GPIO28_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio29\", GPIO29_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio30\", GPIO30_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio31\", GPIO31_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio36\", GPIO36_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio37\", GPIO37_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio38\", GPIO38_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio39\", GPIO39_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio40\", GPIO40_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio41\", GPIO41_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio42\", GPIO42_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio43\", GPIO43_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio44\", GPIO44_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio45\", GPIO45_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio46\", GPIO46_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio47\", GPIO47_FLASH_MODE_CFG),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio33\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio34\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio35\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio42\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio43\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio44\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio45\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio46\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio33\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio34\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio35\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio42\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio43\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio44\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio45\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio46\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio33\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio34\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio35\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio42\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio43\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio44\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio45\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio46\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio33\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio34\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio35\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio42\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio43\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio44\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio45\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio46\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio43\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio44\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio45\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio46\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio43\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio44\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio45\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio46\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio43\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio44\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio45\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio46\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio43\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio44\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio45\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio46\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct pingroup en7581_pinctrl_groups[] = {\n+\tPINCTRL_PIN_GROUP(\"pon\", en7581_pon),\n+\tPINCTRL_PIN_GROUP(\"pon_tod_1pps\", en7581_pon_tod_1pps),\n+\tPINCTRL_PIN_GROUP(\"gsw_tod_1pps\", en7581_gsw_tod_1pps),\n+\tPINCTRL_PIN_GROUP(\"sipo\", en7581_sipo),\n+\tPINCTRL_PIN_GROUP(\"sipo_rclk\", en7581_sipo_rclk),\n+\tPINCTRL_PIN_GROUP(\"mdio\", en7581_mdio),\n+\tPINCTRL_PIN_GROUP(\"uart2\", en7581_uart2),\n+\tPINCTRL_PIN_GROUP(\"uart2_cts_rts\", en7581_uart2_cts_rts),\n+\tPINCTRL_PIN_GROUP(\"hsuart\", en7581_hsuart),\n+\tPINCTRL_PIN_GROUP(\"hsuart_cts_rts\", en7581_hsuart_cts_rts),\n+\tPINCTRL_PIN_GROUP(\"uart4\", en7581_uart4),\n+\tPINCTRL_PIN_GROUP(\"uart5\", en7581_uart5),\n+\tPINCTRL_PIN_GROUP(\"i2c0\", en7581_i2c0),\n+\tPINCTRL_PIN_GROUP(\"i2c1\", en7581_i2c1),\n+\tPINCTRL_PIN_GROUP(\"jtag_udi\", en7581_jtag_udi),\n+\tPINCTRL_PIN_GROUP(\"jtag_dfd\", en7581_jtag_dfd),\n+\tPINCTRL_PIN_GROUP(\"i2s\", en7581_i2s),\n+\tPINCTRL_PIN_GROUP(\"pcm1\", en7581_pcm1),\n+\tPINCTRL_PIN_GROUP(\"pcm2\", en7581_pcm2),\n+\tPINCTRL_PIN_GROUP(\"spi\", en7581_spi),\n+\tPINCTRL_PIN_GROUP(\"spi_quad\", en7581_spi_quad),\n+\tPINCTRL_PIN_GROUP(\"spi_cs1\", en7581_spi_cs1),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi\", en7581_pcm_spi),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_int\", en7581_pcm_spi_int),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_rst\", en7581_pcm_spi_rst),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs1\", en7581_pcm_spi_cs1),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs2_p128\", en7581_pcm_spi_cs2_p128),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs2_p156\", en7581_pcm_spi_cs2_p156),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs2\", en7581_pcm_spi_cs2),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs3\", en7581_pcm_spi_cs3),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs4\", en7581_pcm_spi_cs4),\n+\tPINCTRL_PIN_GROUP(\"emmc\", en7581_emmc),\n+\tPINCTRL_PIN_GROUP(\"pnand\", en7581_pnand),\n+\tPINCTRL_PIN_GROUP(\"gpio0\", en7581_gpio0),\n+\tPINCTRL_PIN_GROUP(\"gpio1\", en7581_gpio1),\n+\tPINCTRL_PIN_GROUP(\"gpio2\", en7581_gpio2),\n+\tPINCTRL_PIN_GROUP(\"gpio3\", en7581_gpio3),\n+\tPINCTRL_PIN_GROUP(\"gpio4\", en7581_gpio4),\n+\tPINCTRL_PIN_GROUP(\"gpio5\", en7581_gpio5),\n+\tPINCTRL_PIN_GROUP(\"gpio6\", en7581_gpio6),\n+\tPINCTRL_PIN_GROUP(\"gpio7\", en7581_gpio7),\n+\tPINCTRL_PIN_GROUP(\"gpio8\", en7581_gpio8),\n+\tPINCTRL_PIN_GROUP(\"gpio9\", en7581_gpio9),\n+\tPINCTRL_PIN_GROUP(\"gpio10\", en7581_gpio10),\n+\tPINCTRL_PIN_GROUP(\"gpio11\", en7581_gpio11),\n+\tPINCTRL_PIN_GROUP(\"gpio12\", en7581_gpio12),\n+\tPINCTRL_PIN_GROUP(\"gpio13\", en7581_gpio13),\n+\tPINCTRL_PIN_GROUP(\"gpio14\", en7581_gpio14),\n+\tPINCTRL_PIN_GROUP(\"gpio15\", en7581_gpio15),\n+\tPINCTRL_PIN_GROUP(\"gpio16\", en7581_gpio16),\n+\tPINCTRL_PIN_GROUP(\"gpio17\", en7581_gpio17),\n+\tPINCTRL_PIN_GROUP(\"gpio18\", en7581_gpio18),\n+\tPINCTRL_PIN_GROUP(\"gpio19\", en7581_gpio19),\n+\tPINCTRL_PIN_GROUP(\"gpio20\", en7581_gpio20),\n+\tPINCTRL_PIN_GROUP(\"gpio21\", en7581_gpio21),\n+\tPINCTRL_PIN_GROUP(\"gpio22\", en7581_gpio22),\n+\tPINCTRL_PIN_GROUP(\"gpio23\", en7581_gpio23),\n+\tPINCTRL_PIN_GROUP(\"gpio24\", en7581_gpio24),\n+\tPINCTRL_PIN_GROUP(\"gpio25\", en7581_gpio25),\n+\tPINCTRL_PIN_GROUP(\"gpio26\", en7581_gpio26),\n+\tPINCTRL_PIN_GROUP(\"gpio27\", en7581_gpio27),\n+\tPINCTRL_PIN_GROUP(\"gpio28\", en7581_gpio28),\n+\tPINCTRL_PIN_GROUP(\"gpio29\", en7581_gpio29),\n+\tPINCTRL_PIN_GROUP(\"gpio30\", en7581_gpio30),\n+\tPINCTRL_PIN_GROUP(\"gpio31\", en7581_gpio31),\n+\tPINCTRL_PIN_GROUP(\"gpio33\", en7581_gpio33),\n+\tPINCTRL_PIN_GROUP(\"gpio34\", en7581_gpio34),\n+\tPINCTRL_PIN_GROUP(\"gpio35\", en7581_gpio35),\n+\tPINCTRL_PIN_GROUP(\"gpio36\", en7581_gpio36),\n+\tPINCTRL_PIN_GROUP(\"gpio37\", en7581_gpio37),\n+\tPINCTRL_PIN_GROUP(\"gpio38\", en7581_gpio38),\n+\tPINCTRL_PIN_GROUP(\"gpio39\", en7581_gpio39),\n+\tPINCTRL_PIN_GROUP(\"gpio40\", en7581_gpio40),\n+\tPINCTRL_PIN_GROUP(\"gpio41\", en7581_gpio41),\n+\tPINCTRL_PIN_GROUP(\"gpio42\", en7581_gpio42),\n+\tPINCTRL_PIN_GROUP(\"gpio43\", en7581_gpio43),\n+\tPINCTRL_PIN_GROUP(\"gpio44\", en7581_gpio44),\n+\tPINCTRL_PIN_GROUP(\"gpio45\", en7581_gpio45),\n+\tPINCTRL_PIN_GROUP(\"gpio46\", en7581_gpio46),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset0\", en7581_pcie_reset0),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset1\", en7581_pcie_reset1),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset2\", en7581_pcie_reset2),\n+};\n+\n+static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {\n+\tPINCTRL_FUNC_DESC(\"pon\", pon),\n+\tPINCTRL_FUNC_DESC(\"tod_1pps\", tod_1pps),\n+\tPINCTRL_FUNC_DESC(\"sipo\", sipo),\n+\tPINCTRL_FUNC_DESC(\"mdio\", mdio),\n+\tPINCTRL_FUNC_DESC(\"uart\", uart),\n+\tPINCTRL_FUNC_DESC(\"i2c\", i2c),\n+\tPINCTRL_FUNC_DESC(\"jtag\", jtag),\n+\tPINCTRL_FUNC_DESC(\"pcm\", pcm),\n+\tPINCTRL_FUNC_DESC(\"spi\", spi),\n+\tPINCTRL_FUNC_DESC(\"pcm_spi\", pcm_spi),\n+\tPINCTRL_FUNC_DESC(\"i2s\", i2s),\n+\tPINCTRL_FUNC_DESC(\"emmc\", emmc),\n+\tPINCTRL_FUNC_DESC(\"pnand\", pnand),\n+\tPINCTRL_FUNC_DESC(\"pcie_reset\", pcie_reset),\n+\tPINCTRL_FUNC_DESC(\"pwm\", pwm),\n+\tPINCTRL_FUNC_DESC(\"phy1_led0\", phy1_led0),\n+\tPINCTRL_FUNC_DESC(\"phy2_led0\", phy2_led0),\n+\tPINCTRL_FUNC_DESC(\"phy3_led0\", phy3_led0),\n+\tPINCTRL_FUNC_DESC(\"phy4_led0\", phy4_led0),\n+\tPINCTRL_FUNC_DESC(\"phy1_led1\", phy1_led1),\n+\tPINCTRL_FUNC_DESC(\"phy2_led1\", phy2_led1),\n+\tPINCTRL_FUNC_DESC(\"phy3_led1\", phy3_led1),\n+\tPINCTRL_FUNC_DESC(\"phy4_led1\", phy4_led1),\n+};\n+\n+static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),\n+\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),\n+\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),\n+\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),\n+\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),\n+\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),\n+\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),\n+\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),\n+\tPINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),\n+\tPINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),\n+\tPINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),\n+\tPINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),\n+\tPINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),\n+\tPINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),\n+\tPINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),\n+\tPINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),\n+\tPINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),\n+\tPINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),\n+\tPINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),\n+\tPINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),\n+\tPINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),\n+\tPINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),\n+\tPINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),\n+\tPINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),\n+\tPINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),\n+\tPINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),\n+\tPINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),\n+\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),\n+\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),\n+\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),\n+\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),\n+\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),\n+\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),\n+\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),\n+\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),\n+\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),\n+\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),\n+\tPINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),\n+\tPINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),\n+\tPINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),\n+\tPINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),\n+\tPINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),\n+\tPINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),\n+\tPINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),\n+\tPINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),\n+\tPINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),\n+\tPINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),\n+\tPINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),\n+\tPINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),\n+\tPINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),\n+\tPINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),\n+\tPINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),\n+\tPINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),\n+\tPINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),\n+\tPINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),\n+\tPINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),\n+\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),\n+\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),\n+\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {\n+\t.gpio_offs = 13,\n+\t.gpio_pin_cnt = 47,\n+\t.pins = en7581_pinctrl_pins,\n+\t.num_pins = ARRAY_SIZE(en7581_pinctrl_pins),\n+\t.grps = en7581_pinctrl_groups,\n+\t.num_grps = ARRAY_SIZE(en7581_pinctrl_groups),\n+\t.funcs = en7581_pinctrl_funcs,\n+\t.num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),\n+\t.confs_info = {\n+\t\t[AIROHA_PINCTRL_CONFS_PULLUP] = {\n+\t\t\t.confs = en7581_pinctrl_pullup_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PULLDOWN] = {\n+\t\t\t.confs = en7581_pinctrl_pulldown_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {\n+\t\t\t.confs = en7581_pinctrl_drive_e2_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {\n+\t\t\t.confs = en7581_pinctrl_drive_e4_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {\n+\t\t\t.confs = en7581_pinctrl_pcie_rst_od_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),\n+\t\t},\n+\t},\n+};\n+\n+static const struct udevice_id airoha_pinctrl_of_match[] = {\n+\t{ .compatible = \"airoha,en7581-pinctrl\",\n+\t  .data = (uintptr_t)&en7581_pinctrl_match_data },\n+\t{ /* sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(airoha_pinctrl) = {\n+\t.name = \"airoha-an7581-pinctrl\",\n+\t.id = UCLASS_PINCTRL,\n+\t.of_match = of_match_ptr(airoha_pinctrl_of_match),\n+\t.probe = airoha_pinctrl_probe,\n+\t.bind = airoha_pinctrl_bind,\n+\t.priv_auto = sizeof(struct airoha_pinctrl),\n+\t.ops = &airoha_pinctrl_ops,\n+};\n",
    "prefixes": [
        "v2",
        "2/6"
    ]
}