[{"id":3683708,"web_url":"http://patchwork.ozlabs.org/comment/3683708/","msgid":"<5f524c23-d21f-49f6-8b26-778654c41a42@baylibre.com>","list_archive_url":null,"date":"2026-04-28T20:42:31","subject":"Re: [PATCH v2 2/6] pinctrl: airoha: add pin controller and gpio\n driver for AN7581 SoC","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/people/87228/","name":"David Lechner","email":"dlechner@baylibre.com"},"content":"On 4/28/26 10:34 AM, Mikhail Kshevetskiy wrote:\n> The driver based on official linux airoha pinctrl and gpio driver with\n> Matheus Sampaio Queiroga changes.\n> The changes:\n> * Separate code for each SoC and keep some of the functions in\n> common between them,\n> * Add pinctrl driver for EN7523 SoC.\n\nThese comments above seem more approiate for the cover letter.\nI can keep the cover letter in the git history when I pick this up if\nwe think that is important.\n\n> \n> The original Matheus Sampaio Queiroga driver can be taken from the repo:\n> https://sirherobrine23.com.br/airoha_an7523/kernel/commits/branch/airoha_an7523_pinctrl\n> \n> This patch adds U-Boot pin controller and gpio driver for Airoha AN7581 SoC.\n> \n> Signed-off-by: Mikhail Kshevetskiy \n> ---\n> drivers/pinctrl/Kconfig | 1 +\n> drivers/pinctrl/Makefile | 1 +\n> drivers/pinctrl/airoha/Kconfig | 16 +\n> drivers/pinctrl/airoha/Makefile | 5 +\n> drivers/pinctrl/airoha/airoha-common.h | 513 +++++++++++\n> drivers/pinctrl/airoha/pinctrl-airoha.c | 691 +++++++++++++++\n> drivers/pinctrl/airoha/pinctrl-an7581.c | 1060 +++++++++++++++++++++++\n\nLet's split out an7581 support into a separate patch too and have\nthis patch just be the core/shared code.\n\n> 7 files changed, 2287 insertions(+)\n> create mode 100644 drivers/pinctrl/airoha/Kconfig\n> create mode 100644 drivers/pinctrl/airoha/Makefile\n> create mode 100644 drivers/pinctrl/airoha/airoha-common.h\n> create mode 100644 drivers/pinctrl/airoha/pinctrl-airoha.c\n> create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c\n> \n> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig\n> index 578edbf8168..46a95a1ab6b 100644\n> --- a/drivers/pinctrl/Kconfig\n> +++ b/drivers/pinctrl/Kconfig\n> @@ -405,6 +405,7 @@ config SPL_PINCTRL_ZYNQMP\n> \n> endif\n> \n> +source \"drivers/pinctrl/airoha/Kconfig\"\n> source \"drivers/pinctrl/broadcom/Kconfig\"\n> source \"drivers/pinctrl/exynos/Kconfig\"\n> source \"drivers/pinctrl/intel/Kconfig\"\n> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile\n> index 29fb9b484d0..b03e838ab39 100644\n> --- a/drivers/pinctrl/Makefile\n> +++ b/drivers/pinctrl/Makefile\n> @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_PIC32)\t+= pinctrl_pic32.o\n> obj-$(CONFIG_PINCTRL_EXYNOS)\t+= exynos/\n> obj-$(CONFIG_PINCTRL_K210)\t+= pinctrl-k210.o\n> obj-$(CONFIG_PINCTRL_MESON)\t+= meson/\n> +obj-$(CONFIG_PINCTRL_AIROHA)\t+= airoha/\n\nAlphabetical order?\n\n> obj-$(CONFIG_PINCTRL_MTK)\t+= mediatek/\n> obj-$(CONFIG_PINCTRL_MSCC)\t+= mscc/\n> obj-$(CONFIG_ARCH_MVEBU)\t+= mvebu/\n> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig\n> new file mode 100644\n> index 00000000000..986d23c2e3d\n> --- /dev/null\n> +++ b/drivers/pinctrl/airoha/Kconfig\n> @@ -0,0 +1,16 @@\n> +# SPDX-License-Identifier: GPL-2.0-only\n> +\n> +config PINCTRL_AIROHA\n> +\tdepends on ARCH_AIROHA\n> +\tselect PINCTRL_FULL\n> +\tselect PINCTRL_GENERIC\n> +\tselect PINMUX\n> +\tselect PINCONF\n> +\tselect REGMAP\n> +\tselect SYSCON\n> +\tbool\n> +\n> +config PINCTRL_AIROHA_AN7581\n> +\ttristate \"AN7581 pin controller and gpio driver\"\n> +\tdepends on TARGET_AN7581\n> +\tselect PINCTRL_AIROHA\n> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile\n> new file mode 100644\n> index 00000000000..909bd9a04d9\n> --- /dev/null\n> +++ b/drivers/pinctrl/airoha/Makefile\n> @@ -0,0 +1,5 @@\n> +# SPDX-License-Identifier: GPL-2.0\n> +\n> +obj-$(CONFIG_PINCTRL_AIROHA)\t\t+= pinctrl-airoha.o\n> +\n> +obj-$(CONFIG_PINCTRL_AIROHA_AN7581)\t+= pinctrl-an7581.o\n> diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h\n> new file mode 100644\n> index 00000000000..21bc9f50083\n> --- /dev/null\n> +++ b/drivers/pinctrl/airoha/airoha-common.h\n> @@ -0,0 +1,513 @@\n\n\n...\n\n> +#define AIROHA_PINCTRL_PHY_LED0(variant, gpio, mux_val, map_mask, map_val)\t\\\n\nMight look nicer to just use space instead of tab before \\ on this first line.\n\n> +\t{\t\t\t\t\t\t\t\t\\\n> +\t\t.name = (gpio),\t\t\t\t\t\t\\\n> +\t\t.regmap[0] = {\t\t\t\t\t\t\\\n> +\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n> +\t\t\tvariant##_REG_GPIO_2ND_I2C_MODE,\t\t\t\t\\\n\nIndent of \\ seems off on this one.\n\n> +\t\t\t(mux_val),\t\t\t\t\t\\\n> +\t\t\t(mux_val),\t\t\t\t\t\\\n> +\t\t},\t\t\t\t\t\t\t\\\n> +\t\t.regmap[1] = {\t\t\t\t\t\t\\\n> +\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n> +\t\t\tREG_LAN_LED0_MAPPING,\t\t\t\t\\\n> +\t\t\t(map_mask),\t\t\t\t\t\\\n> +\t\t\t(map_val),\t\t\t\t\t\\\n> +\t\t},\t\t\t\t\t\t\t\\\n> +\t\t.regmap_size = 2,\t\t\t\t\t\\\n> +\t}\n> +\n> +#define AIROHA_PINCTRL_PHY_LED1(variant, gpio, mux_val, map_mask, map_val)\t\\\n> +\t{\t\t\t\t\t\t\t\t\\\n> +\t\t.name = (gpio),\t\t\t\t\t\t\\\n> +\t\t.regmap[0] = {\t\t\t\t\t\t\\\n> +\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n> +\t\t\tvariant##_REG_GPIO_2ND_I2C_MODE,\t\t\t\t\\\n\nSame as 2 comments above.\n\n> +\t\t\t(mux_val),\t\t\t\t\t\\\n> +\t\t\t(mux_val),\t\t\t\t\t\\\n> +\t\t},\t\t\t\t\t\t\t\\\n> +\t\t.regmap[1] = {\t\t\t\t\t\t\\\n> +\t\t\tAIROHA_FUNC_MUX,\t\t\t\t\\\n> +\t\t\tREG_LAN_LED1_MAPPING,\t\t\t\t\\\n> +\t\t\t(map_mask),\t\t\t\t\t\\\n> +\t\t\t(map_val),\t\t\t\t\t\\\n> +\t\t},\t\t\t\t\t\t\t\\\n> +\t\t.regmap_size = 2,\t\t\t\t\t\\\n> +\t}\n> +\n\n...\n\n> +enum airoha_pinctrl_confs_type {\n> +\tAIROHA_PINCTRL_CONFS_PULLUP,\n> +\tAIROHA_PINCTRL_CONFS_PULLDOWN,\n> +\tAIROHA_PINCTRL_CONFS_DRIVE_E2,\n> +\tAIROHA_PINCTRL_CONFS_DRIVE_E4,\n> +\tAIROHA_PINCTRL_CONFS_PCIE_RST_OD,\n> +\n> +\tAIROHA_PINCTRL_CONFS_MAX,\n\nNo comma on this one since it must always be last.\n\n> +};\n> +\n> +struct airoha_pinctrl {\n> +\tstruct udevice *dev;\n> +\tstruct airoha_pinctrl_match_data *data;\n> +\n> +\tstruct regmap *chip_scu;\n> +\tstruct regmap *regmap;\n> +\n> +\tstruct airoha_pinctrl_gpiochip gpiochip;\n> +};\n> +\n> +struct airoha_pinctrl_match_data {\n> +\tconst int gpio_offs;\n> +\tconst int gpio_pin_cnt;\n> +\tconst struct pinctrl_pin_desc *pins;\n> +\tconst unsigned int num_pins;\n> +\tconst struct pingroup *grps;\n> +\tconst unsigned int num_grps;\n> +\tconst struct airoha_pinctrl_func *funcs;\n> +\tconst unsigned int num_funcs;\n> +\tconst struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];\n> +};\n> +\n> +extern const struct pinctrl_ops airoha_pinctrl_ops;\n> +\n> +int airoha_pinctrl_probe(struct udevice *dev);\n> +int airoha_pinctrl_bind(struct udevice *dev);\n> +\n> +#endif\n> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c\n> new file mode 100644\n> index 00000000000..c8a22792d51\n> --- /dev/null\n> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c\n> @@ -0,0 +1,691 @@\n> +// SPDX-License-Identifier: GPL-2.0-only\n> +/*\n> + * Author: Lorenzo Bianconi \n> + * Author: Benjamin Larsson \n> + * Author: Markus Gothe \n> + * Author: Mikhail Kshevetskiy \n> + */\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +#include \n> +\n> +#include \"airoha-common.h\"\n> +\n> +//#define PINCTRL_GET_STATE\n> +\n\nDrop commented/dead code. If there is a good reason to keep\nairoha_pinctrl_get_conf(), the make a comment there, otherwise\ndrop it.\n\n\n> +static int airoha_gpiochip_register(struct udevice *parent)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl;\n> +\tstruct uclass_driver *drv;\n> +\tstruct udevice *dev;\n> +\tint ret;\n> +\tofnode node;\n> +\n> +\tdrv = lists_uclass_lookup(UCLASS_GPIO);\n> +\tif (!drv)\n> +\t\treturn -ENOENT;\n> +\n> +\t/*\n> +\t * Support upstream linux DTSI that define gpio-controller\n> +\t * in the root node (instead of a dedicated subnode)\n> +\t */\n> +\tif (dev_read_bool(parent, \"gpio-controller\")) {\n> +\t\tnode = dev_ofnode(parent);\n> +\t\tgoto bind;\n\nWhy do we need goto instead of moving the code below into the if\nstatement?\n\n> +\t}\n> +\n> +\tret = -ENOENT;\n> +\tdev_for_each_subnode(node, parent)\n> +\t\tif (ofnode_read_bool(node, \"gpio-controller\")) {\n> +\t\t\tret = 0;\n> +\t\t\tbreak;\n> +\t\t}\n> +\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +bind:\n> +\tret = device_bind_with_driver_data(parent, &airoha_pinctrl_gpio_driver,\n> +\t\t\t\t\t \"airoha_pinctrl_gpio\", 0, node,\n> +\t\t\t\t\t &dev);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tpinctrl = dev_get_priv(parent);\n> +\tpinctrl->gpiochip.dev = dev;\n> +\n> +\treturn 0;\n> +}\n> +\n\n...\n\n> +#if defined(PINCTRL_GET_STATE)\n> +static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,\n> +\t\t\t\t enum airoha_pinctrl_confs_type conf_type,\n> +\t\t\t\t int pin, u32 *val)\n> +{\n> +\tconst struct airoha_pinctrl_confs_info *confs_info;\n> +\tconst struct airoha_pinctrl_reg *reg;\n> +\n> +\tconfs_info = &pinctrl->data->confs_info[conf_type];\n> +\n> +\treg = airoha_pinctrl_get_conf_reg(confs_info->confs,\n> +\t\t\t\t\t confs_info->num_confs,\n> +\t\t\t\t\t pin);\n> +\tif (!reg)\n> +\t\treturn -EINVAL;\n> +\n> +\tif (regmap_read(pinctrl->chip_scu, reg->offset, val))\n> +\t\treturn -EINVAL;\n> +\n> +\t*val = (*val & reg->mask) >> __ffs(reg->mask);\n\nLinux recently got field_get() that is like FIELD_GET() but allows\nnon-constant mask. Maybe time to bring that to U-Boot?\n\n\n> +\n> +\treturn 0;\n> +}\n> +#endif\n> +\n> +static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,\n> +\t\t\t\t enum airoha_pinctrl_confs_type conf_type,\n> +\t\t\t\t int pin, u32 val)\n> +{\n> +\tconst struct airoha_pinctrl_confs_info *confs_info;\n> +\tconst struct airoha_pinctrl_reg *reg = NULL;\n> +\n> +\tconfs_info = &pinctrl->data->confs_info[conf_type];\n> +\n> +\treg = airoha_pinctrl_get_conf_reg(confs_info->confs,\n> +\t\t\t\t\t confs_info->num_confs,\n> +\t\t\t\t\t pin);\n> +\tif (!reg)\n> +\t\treturn -EINVAL;\n> +\n> +\tif (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,\n> +\t\t\t val << __ffs(reg->mask)))\n\nSimilar here, field_prep().\n\nThere are already 2 other drivers that locally #define field_prep() that\ncould benifit.\n\n> +\t\treturn -EINVAL;\n> +\n> +\treturn 0;\n> +}\n> +\n\n\n\n> +static int airoha_pinmux_group_set(struct udevice *dev, unsigned group_selector,\n> +\t\t\t\t unsigned func_selector)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n> +\n> +\tdev_info(dev, \"enabling %s function for pin group %s\\n\",\n\ndev_info() seems a bit verbose for this. Should this (and all others) be\ndev_dbg() instead?\n\n> +\t\tairoha_get_func_name(dev, func_selector),\n> +\t\tairoha_get_group_name(dev, group_selector));\n> +\n> +\treturn airoha_pinmux_set_mux(pinctrl, func_selector, group_selector);\n> +}\n> +\n> +static int airoha_pinmux_set(struct udevice *dev, unsigned pin_selector,\n> +\t\t\t unsigned func_selector)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n> +\tconst struct airoha_pinctrl_match_data *data = pinctrl->data;\n> +\tconst char *pin_name;\n> +\tunsigned selector;\n> +\n> +\tpin_name = data->pins[pin_selector].name;\n> +\n> +\t/* find group matching the pin_name */\n> +\tfor (selector = 0; selector < data->num_grps; selector++) {\n> +\t\tif (!strcmp(pin_name, data->grps[selector].name))\n> +\t\t\treturn airoha_pinmux_group_set(dev, selector,\n> +\t\t\t\t\t\t func_selector);\n> +\t}\n> +\n> +\treturn -ENOENT;\n> +}\n> +\n> +static const struct pinconf_param airoha_pinconf_params[] = {\n> +\t{ \"bias-disable\", PIN_CONFIG_BIAS_DISABLE, 0 },\n> +\t{ \"bias-pull-up\", PIN_CONFIG_BIAS_PULL_UP, 1 },\n> +\t{ \"bias-pull-down\", PIN_CONFIG_BIAS_PULL_DOWN, 1 },\n> +\t{ \"drive-strength\", PIN_CONFIG_DRIVE_STRENGTH, 0 },\n> +\t{ \"drive-open-drain\", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },\n> +\t{ \"output-enable\", PIN_CONFIG_OUTPUT_ENABLE, 1 },\n> +\t{ \"input-enable\", PIN_CONFIG_INPUT_ENABLE, 1 },\n> +};\n> +\n> +static int airoha_pinconf_set_handler(struct udevice *dev, unsigned pin_selector,\n> +\t\t\t\t unsigned param, unsigned argument)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n> +\tunsigned long configs[1] = { param };\n> +\tunsigned int pin = pinctrl->data->pins[pin_selector].number;\n\nCan we be sure that pin_selector is not out of bounds?\n\n> +\n> +\tdev_info(dev, \"enabling %s=%d property for pin %s\\n\",\n> +\t\tairoha_pinconf_params[param].property, argument,\n> +\t\tairoha_get_pin_name(dev, pin_selector));\n\nIs this supposed to do something with `argument`? Strange to print it\nbut not pass it to airoha_pinconf_set().\n\n> +\n> +\treturn airoha_pinconf_set(pinctrl, pin, configs, 1);\n\nBetter would be ARRAY_SIZE(configs) instead of 1.\n\nOr change the type of `param` and pass ¶m instead.\n\n> +}\n> +\n> +static int airoha_pinconf_group_set_handler(struct udevice *dev, unsigned group_selector,\n> +\t\t\t\t\t unsigned param, unsigned argument)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n> +\tunsigned long configs[1] = { param };\n> +\n> +\tdev_info(dev, \"enabling %s=%d property for pin group %s\\n\",\n> +\t\tairoha_pinconf_params[param].property, argument,\n> +\t\tairoha_get_group_name(dev, group_selector));\n> +\n> +\treturn airoha_pinconf_group_set(pinctrl, group_selector, configs, 1);\n> +}\n> +\n> +const struct pinctrl_ops airoha_pinctrl_ops = {\n> +\t.get_pins_count\t\t= airoha_get_pins_count,\n> +\t.get_pin_name\t\t= airoha_get_pin_name,\n> +\t.get_groups_count\t= airoha_get_groups_count,\n> +\t.get_group_name\t\t= airoha_get_group_name,\n> +\t.get_functions_count\t= airoha_get_funcs_count,\n> +\t.get_function_name\t= airoha_get_func_name,\n> +\t.pinmux_set\t\t= airoha_pinmux_set,\n> +\t.pinmux_group_set\t= airoha_pinmux_group_set,\n> +\n> +\t.pinconf_num_params\t= ARRAY_SIZE(airoha_pinconf_params),\n> +\t.pinconf_params\t\t= airoha_pinconf_params,\n> +\t.pinconf_set\t\t= airoha_pinconf_set_handler,\n> +\t.pinconf_group_set\t= airoha_pinconf_group_set_handler,\n> +\n> +\t.set_state\t\t= pinctrl_generic_set_state,\n> +};\n> +\n> +int airoha_pinctrl_probe(struct udevice *dev)\n> +{\n> +\tstruct airoha_pinctrl *pinctrl = dev_get_priv(dev);\n> +\n> +\tpinctrl->dev = dev;\n> +\tpinctrl->data = (struct airoha_pinctrl_match_data *)dev_get_driver_data(dev);\n\nnit: casting isn't needed here (leaving it out makes it more readable)\n\n> +\n> +\tpinctrl->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));\n> +\tif (IS_ERR(pinctrl->regmap))\n> +\t\treturn PTR_ERR(pinctrl->regmap);\n> +\n> +\tpinctrl->chip_scu = airoha_get_chip_scu_regmap();\n> +\tif (IS_ERR(pinctrl->chip_scu))\n> +\t\treturn PTR_ERR(pinctrl->chip_scu);\n> +\n> +\tpinctrl->gpiochip.data = gpio_data_regs;\n> +\tpinctrl->gpiochip.dir = gpio_dir_regs;\n> +\tpinctrl->gpiochip.out = gpio_out_regs;\n> +\tpinctrl->gpiochip.status = irq_status_regs;\n> +\tpinctrl->gpiochip.level = irq_level_regs;\n> +\tpinctrl->gpiochip.edge = irq_edge_regs;\n> +\n> +\treturn 0;\n> +}\n> +\n> +int airoha_pinctrl_bind(struct udevice *dev)\n> +{\n> +\t/*\n> +\t * Make sure that the pinctrl driver gets probed after binding\n> +\t * as on EN7523/AN7581/AN7583 the pinctrl driver is the one that\n> +\t * is also registering the GPIO one during probe, so if its not\n> +\t * probed GPIO-s are not registered as well.\n\ns/GPIO-s/GPIOs/\n\n> +\t */\n> +\tdev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);\n> +\n> +\treturn airoha_gpiochip_register(dev);\n> +}\n> diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c\n> new file mode 100644\n> index 00000000000..c70952e9ba8\n> --- /dev/null\n> +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c\n> @@ -0,0 +1,1060 @@\n> +// SPDX-License-Identifier: GPL-2.0-only\n> +/*\n> + * Author: Lorenzo Bianconi \n> + * Author: Benjamin Larsson \n> + * Author: Markus Gothe \n> + */\n> +#include \"airoha-common.h\"\n> +\n> +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };\n> +static const int en7581_pon_tod_1pps_pins[] = { 46 };\n> +static const int en7581_gsw_tod_1pps_pins[] = { 46 };\n> +static const int en7581_sipo_pins[] = { 16, 17 };\n> +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };\n> +static const int en7581_mdio_pins[] = { 14, 15 };\n> +static const int en7581_uart2_pins[] = { 48, 55 };\n> +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };\n> +static const int en7581_hsuart_pins[] = { 28, 29 };\n> +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };\n> +static const int en7581_uart4_pins[] = { 38, 39 };\n> +static const int en7581_uart5_pins[] = { 18, 19 };\n> +static const int en7581_i2c0_pins[] = { 2, 3 };\n> +static const int en7581_i2c1_pins[] = { 14, 15 };\n> +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };\n> +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };\n> +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };\n> +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };\n> +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };\n> +static const int en7581_spi_quad_pins[] = { 32, 33 };\n> +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };\n> +static const int en7581_spi_cs1_pins[] = { 34 };\n> +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };\n> +static const int en7581_pcm_spi_int_pins[] = { 14 };\n> +static const int en7581_pcm_spi_rst_pins[] = { 15 };\n> +static const int en7581_pcm_spi_cs1_pins[] = { 43 };\n> +static const int en7581_pcm_spi_cs2_pins[] = { 40 };\n> +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };\n> +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };\n> +static const int en7581_pcm_spi_cs3_pins[] = { 41 };\n> +static const int en7581_pcm_spi_cs4_pins[] = { 42 };\n> +static const int en7581_emmc_pins[] = {\n> +\t4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37\n> +};\n> +static const int en7581_pnand_pins[] = { 4, 5,\t 6, 7,\t 30, 31, 32, 33, 34,\n> +\t\t\t\t\t 35, 36, 37, 38, 39, 40, 41, 42 };\n...\n\n> +static const char *const pon_groups[] = { \"pon\" };\n> +static const char *const tod_1pps_groups[] = { \"pon_tod_1pps\", \"gsw_tod_1pps\" };\n> +static const char *const sipo_groups[] = { \"sipo\", \"sipo_rclk\" };\n> +static const char *const mdio_groups[] = { \"mdio\" };\n> +\n> +static const char *const uart_groups[] = { \"uart2\", \"uart2_cts_rts\",\n> +\t\t\t\t\t \"hsuart\", \"hsuart_cts_rts\",\n> +\t\t\t\t\t \"uart4\", \"uart5\" };\n> +static const char *const i2c_groups[] = { \"i2c1\" };\n> +static const char *const jtag_groups[] = { \"jtag_udi\", \"jtag_dfd\" };\n> +static const char *const pcm_groups[] = { \"pcm1\", \"pcm2\" };\n> +static const char *const spi_groups[] = { \"spi_quad\", \"spi_cs1\" };\n> +static const char *const pcm_spi_groups[] = {\n> +\t\"pcm_spi\",\t \"pcm_spi_int\",\t\"pcm_spi_rst\", \"pcm_spi_cs1\",\n> +\t\"pcm_spi_cs2_p156\", \"pcm_spi_cs2_p128\", \"pcm_spi_cs3\", \"pcm_spi_cs4\"\n> +};\n> +\n> +static const char *const i2s_groups[] = { \"i2s\" };\n> +static const char *const emmc_groups[] = { \"emmc\" };\n> +static const char *const pnand_groups[] = { \"pnand\" };\n> +static const char *const pcie_reset_groups[] = { \"pcie_reset0\", \"pcie_reset1\",\n> +\t\t\t\t\t\t \"pcie_reset2\" };\n> +\n> +static const char *const pwm_groups[] = {\n> +\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\t\"gpio4\", \"gpio5\", \"gpio6\",\n> +\t\"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n> +\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\",\n> +\t\"gpio21\", \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n> +\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio36\", \"gpio37\", \"gpio38\",\n> +\t\"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n> +\t\"gpio46\", \"gpio47\"\n> +};\n> +static const char *const phy1_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n> +\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n> +static const char *const phy2_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n> +\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n> +static const char *const phy3_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n> +\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n> +static const char *const phy4_led0_groups[] = { \"gpio33\", \"gpio34\", \"gpio35\",\n> +\t\t\t\t\t\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\" };\n> +static const char *const phy1_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n> +\t\t\t\t\t\t\"gpio46\" };\n> +static const char *const phy2_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n> +\t\t\t\t\t\t\"gpio46\" };\n> +static const char *const phy3_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n> +\t\t\t\t\t\t\"gpio46\" };\n> +static const char *const phy4_led1_groups[] = { \"gpio43\", \"gpio44\", \"gpio45\",\n> +\t\t\t\t\t\t\"gpio46\" };\n\nI would wrap these like this to be more readable:\n\nstatic const char *const phy4_led1_groups[] = {\n\t\"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\"\n};\n\nSame applies to other stuff above like uart_groups.\n\n> +\n> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {\n> +\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),\n> +\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),\n> +\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),\n> +\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),\n> +\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),\n> +\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),\n> +\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),\n> +\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),\n> +\tPINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),\n> +\tPINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),\n> +\tPINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),\n> +\tPINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),\n> +\tPINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),\n> +\tPINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),\n> +\tPINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),\n> +\tPINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),\n> +\tPINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),\n> +\tPINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),\n> +\tPINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),\n> +\tPINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),\n> +\tPINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),\n> +\tPINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),\n> +\tPINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),\n> +\tPINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),\n> +\tPINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),\n> +\tPINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),\n> +\tPINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),\n> +\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),\n> +\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),\n> +\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),\n> +};\n> +\n> +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {\n> +\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),\n> +\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),\n> +\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),\n> +\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),\n> +\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),\n> +\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),\n> +\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),\n> +\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),\n> +\tPINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),\n> +\tPINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),\n> +\tPINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),\n> +\tPINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),\n> +\tPINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),\n> +\tPINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),\n> +\tPINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),\n> +\tPINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),\n> +\tPINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),\n> +\tPINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),\n> +\tPINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),\n> +\tPINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),\n> +\tPINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),\n> +\tPINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),\n> +\tPINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),\n> +\tPINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),\n> +\tPINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),\n> +\tPINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),\n> +\tPINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),\n> +\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),\n> +\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),\n> +\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),\n> +};\n> +\n\n...\n\n> +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio43\", GPIO_LAN0_LED1_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio44\", GPIO_LAN1_LED1_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio45\", GPIO_LAN2_LED1_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio46\", GPIO_LAN3_LED1_MODE_MASK,\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n> +};\n\nShould these be LANX_PHY_LED_MAP(3) instead of 2?\n\n> +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {\n> +\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),\n> +\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),\n> +\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),\n> +\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),\n> +\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),\n> +\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),\n> +\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),\n> +\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),\n> +\tPINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),\n> +\tPINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),\n> +\tPINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),\n> +\tPINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),\n> +\tPINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),\n> +\tPINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),\n> +\tPINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),\n> +\tPINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),\n> +\tPINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),\n> +\tPINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),\n> +\tPINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),\n> +\tPINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),\n> +\tPINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),\n> +\tPINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),\n> +\tPINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),\n> +\tPINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),\n> +\tPINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),\n> +\tPINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),\n> +\tPINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),\n> +\tPINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),\n> +\tPINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),\n> +\tPINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),\n> +};\n> +\n> +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {\n> +\tPINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),\n> +\tPINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),\n> +\tPINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),\n> +\tPINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),\n> +\tPINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),\n> +\tPINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),\n> +\tPINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),\n> +\tPINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),\n\n\n...\n\n> +U_BOOT_DRIVER(airoha_pinctrl) = {\n\nWe are aiming to be able to compile all drivers at the same time for static\nanalysis, so include an7581 in the driver identifier (airoha_an7581_pinctrl).\n\n> +\t.name = \"airoha-an7581-pinctrl\",\n> +\t.id = UCLASS_PINCTRL,\n> +\t.of_match = of_match_ptr(airoha_pinctrl_of_match),\n> +\t.probe = airoha_pinctrl_probe,\n> +\t.bind = airoha_pinctrl_bind,\n> +\t.priv_auto = sizeof(struct airoha_pinctrl),\n> +\t.ops = &airoha_pinctrl_ops,\n> +};","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20251104.gappssmtp.com\n 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