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GET /api/1.1/patches/2229668/?format=api
{ "id": 2229668, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229668/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-5-mikhail.kshevetskiy@iopsys.eu/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428153448.980150-5-mikhail.kshevetskiy@iopsys.eu>", "date": "2026-04-28T15:34:46", "name": "[v2,4/6] pinctrl: airoha: add pin controller and gpio driver for EN7523 SoC", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "9851cc064b9eaea36064285ffe5b912491167111", "submitter": { "id": 84987, "url": "http://patchwork.ozlabs.org/api/1.1/people/84987/?format=api", "name": "Mikhail Kshevetskiy", "email": "mikhail.kshevetskiy@iopsys.eu" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-5-mikhail.kshevetskiy@iopsys.eu/mbox/", "series": [ { "id": 501878, "url": "http://patchwork.ozlabs.org/api/1.1/series/501878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501878", "date": "2026-04-28T15:34:43", "name": "pinctrl: add support of Airoha SoCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229668/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229668/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=iopsys.eu header.i=@iopsys.eu header.a=rsa-sha256\n header.s=selector1 header.b=f5kZ13kK;\n\tdkim-atps=neutral", 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b=f5kZ13kKGoz0EIiHa/e6c8C4faMuuj0TeYcv4EIRmuhba99579ajoVbMiajnNiLTcRlHC4uJ7fDZcrbLeCCRsdnIL/odtayYHWcMus95GKmDPNn++YUjQs2zjbueoDBBEL1dCMxWe7t8Vvahq2tqut40Qqjl0dVAKeAWZVNqex/zwpoVKoXsdp6GCV4pULnj7gTmdDkmyHyRMttStMK+cK8NqsT6kSBD3DkOfHpPkSEGntr3FYK4T9q7VGSYBh/42VmHql1Ao4Sy3/BmZCGuSo/j3+FHkwxHtsr6kF7nEwc3Bgw2eIlxAqQT3iKbSE+UqVHD92aIAHHV06IY2mo6Nw==", "From": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>", "To": "Tom Rini <trini@konsulko.com>, Christian Marangi <ansuelsmth@gmail.com>,\n Simon Glass <sjg@chromium.org>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>, Peng Fan <peng.fan@nxp.com>,\n Sean Anderson <sean.anderson@linux.dev>, Yao Zi <me@ziyao.cc>,\n Michal Simek <michal.simek@amd.com>, Anis Chali <chalianis1@gmail.com>,\n u-boot@lists.denx.de, Lorenzo Bianconi <lorenzo@kernel.org>,\n Markus Gothe <markus.gothe@genexis.eu>,\n Matheus Sampaio Queiroga <srherobrine20@gmail.com>,\n Benjamin Larsson <benjamin.larsson@genexis.eu>,\n David Lechner <dlechner@baylibre.com>", "Cc": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>", "Subject": "[PATCH v2 4/6] pinctrl: airoha: add pin controller and gpio driver\n for EN7523 SoC", "Date": "Tue, 28 Apr 2026 18:34:46 +0300", "Message-ID": "<20260428153448.980150-5-mikhail.kshevetskiy@iopsys.eu>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260428153448.980150-1-mikhail.kshevetskiy@iopsys.eu>", "References": "<20260428153448.980150-1-mikhail.kshevetskiy@iopsys.eu>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "FR0P281CA0078.DEUP281.PROD.OUTLOOK.COM\n (2603:10a6:d10:1e::17) To DU2PR08MB10037.eurprd08.prod.outlook.com\n (2603:10a6:10:49a::20)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DU2PR08MB10037:EE_|GV1PR08MB8715:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e545a3d3-a1ec-4981-6714-08dea53bb69e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n 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KbVdvvof31cuKCSuhJ3Ut9kMF3cYg4KoG17Adim3lNoNCMZ6ShCy12tSEXnb5aaFx3fOFy7LYLHt5NqzJvaDvu9fEUrmvJDY5adVGNDf2rqzooUFOtrk8YaQO7EDvSN9pqYdY98zCPujCwt1vp4KRG/17duQ+fZ1Whyl24h8s9Ab+r19ynTsPKUG5jm3XSMFpjRX/2Nlr1bZoBMKDb63zhhnK5kTPijTNYAdeXt8UzWgc0cR1WMCENPlbJhpmBbcNTxQw2nJGUQoI5YI6HAxafRml+lpEc0LHF8f/oYVBtDHe3Gv3hLQg/XF4ALiyAJvKu5l86OYjN1B+hFStYfe+Wkd2p7g0fUVdjrsnfWesA/MU/ksmJ6shTmxtMYSkRqTrspKM/e6s1k72/ub7f4TJBcXbgMOCrOfGkSbcWZZndIuwBG62sitrgM87a2Xm2bYnkMtx9D/praBSjmxUUkymiRuWoMqq3hjDvZyqGhc6ewZnbbx3uVCpf8huhUtTWFecY5Pg52BxI+x1d1Uw3ong8yKsmvsKjQcNBZpQMH6vFmE3T33VHOOUCef3tGIsHPOK2dDHKJQVvmphgN3H0UA0B1hqM5V32P55uTsHm0v9n/vMMyvhv+/NHVg2sM3xz29CVOumBtBTS/eAPYJHe9Aj/DI3dvwMXDUwRLMXSXjjufECrrLzJOzUbd1izikyBxkJDiacmbh+5oIeUTGkvlSRSOiGCMP+JEEKaShcTbZRlkoJW3TIl5G3hVFGoVmjJ0H8cf7xFv/CP0uYP61IZpZAco7GjShpcc/OrfaJ1CHKKu/GpmqFOzjHwtpZFTdSYQOZKNUsaIvAGQFIu/6FIbJuMMfvq+KVhp4ChUD2XjnHGky/TcMJdtkFC9LtcxVjXqFDtjmiwiaQPSfOAmo78rH0TaW6JtneSuFZRDTKDyPtwbr6Ay+jeSiKC9VmTvh69WLitmJOSIi7O9ieEums2dKxM8EYvRVWGkoBHMqcjG1Rekyoj4AB8/ms6qCN3HckcYi8p1qzBf9C6HMQdaFcHdjE7a/+qIXKwBynOO6v+lyJnuOPJbYWgIj4widzKzIQNOHzASKVCw0b9gnV6kmBvZ4h9HsLDF12KwYeUwSbMBp2YT1PxAITt/2x42wWVoqFH3o7rZ0kt0f7BMtfpVvk/4kDI2cwSMuBBW/TdzkuumQFUErQWqpJXN+8QP6kFYe0cEUxhgBNCL+sIoPAUGIthQr+cu2CkBFDUsuqNCr+cTZSkAF0iNM3QWSW0XJ0wlcayonF2WlKW3Iz/R9H+4kCK2DRXMQJOEzhQM43MluUYHoyJLDQzfn4gBXeIWTriStFXEXQvGAWPdmT/XoMZ3Y93nLI138BbJXBKtLYN4no3GStWt6li/rzISmbeSkVhc2/aOaIHe2MIDQiusvNdjX0WiCp/tnzpymSr4/xH/DyCu7kriawkpvftESsAH5R9a4JbvudLGmrkd7rre9trriiy9LxHROMiFq2KOQAsKplVNqVh6rRYAfRzuIuWIvJq481HNI2m6LJA61Sdwv8GAxucz15o6xhMdZj+3l7ja1S1y5IoWrk0UHgdNmhzWQaLV/VH+dIiVlilthWJyvTlmBgS52JBuvmjGD39LZibodTo2p8DJGp+LNfIGFxc9X8w2NnSiVQWWSqqHVDVvHdUTdNUJ6N2Y5TxtMHtzdzj23UG0FEw/ZB7Cyo6EkoB5hUVgMg6JpZyDzPC3p0i3uGnXsFYrjIQFOaNo9r+RK5A0hqxMdpU4=", "X-OriginatorOrg": "iopsys.eu", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e545a3d3-a1ec-4981-6714-08dea53bb69e", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR08MB10037.eurprd08.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Apr 2026 15:35:02.1165 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "8d891be1-7bce-4216-9a99-bee9de02ba58", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n FXcdQ4MwFv4kZ7j5PkzO2MVeaVVXNcyf/v8irYBA+Y07p0st337cj8/C9crLaGxIiEbCgslkLlSSNmzZCkexLdKA9sgwN5PTOHDK+ALnjpM=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "GV1PR08MB8715", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The driver based on official linux airoha pinctrl and gpio driver with\nMatheus Sampaio Queiroga <srherobrine20@gmail.com> changes.\nThe changes:\n * Separate code for each SoC and keep some of the functions in\n common between them,\n * Add pinctrl driver for EN7523 SoC.\n\nThe original Matheus Sampaio Queiroga driver can be taken from the repo:\n https://sirherobrine23.com.br/airoha_an7523/kernel/commits/branch/airoha_an7523_pinctrl\n\nThis patch adds U-Boot pin controller and gpio driver for Airoha EN7523 SoC.\n\nSigned-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>\n---\n drivers/pinctrl/airoha/Kconfig | 5 +\n drivers/pinctrl/airoha/Makefile | 1 +\n drivers/pinctrl/airoha/pinctrl-en7523.c | 627 ++++++++++++++++++++++++\n 3 files changed, 633 insertions(+)\n create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c", "diff": "diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig\nindex d9df89b20b7..cb4a7ab0b0a 100644\n--- a/drivers/pinctrl/airoha/Kconfig\n+++ b/drivers/pinctrl/airoha/Kconfig\n@@ -10,6 +10,11 @@ config PINCTRL_AIROHA\n \tselect SYSCON\n \tbool\n \n+config PINCTRL_AIROHA_EN7523\n+\tbool \"Airoha EN7523 pin controller and gpio driver\"\n+\tdepends on TARGET_EN7523\n+\tselect PINCTRL_AIROHA\n+\n config PINCTRL_AIROHA_AN7581\n \ttristate \"AN7581 pin controller and gpio driver\"\n \tdepends on TARGET_AN7581\ndiff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile\nindex c8c99dd22f8..b90bd180591 100644\n--- a/drivers/pinctrl/airoha/Makefile\n+++ b/drivers/pinctrl/airoha/Makefile\n@@ -2,5 +2,6 @@\n \n obj-$(CONFIG_PINCTRL_AIROHA)\t\t+= pinctrl-airoha.o\n \n+obj-$(CONFIG_PINCTRL_AIROHA_EN7523)\t+= pinctrl-en7523.o\n obj-$(CONFIG_PINCTRL_AIROHA_AN7581)\t+= pinctrl-an7581.o\n obj-$(CONFIG_PINCTRL_AIROHA_AN7583)\t+= pinctrl-an7583.o\ndiff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c\nnew file mode 100644\nindex 00000000000..50075a51be6\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c\n@@ -0,0 +1,627 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>\n+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>\n+ * Author: Markus Gothe <markus.gothe@genexis.eu>\n+ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>\n+ */\n+#include \"airoha-common.h\"\n+\n+static const int en7523_uart2_pins[] = { 8, 9 };\n+static const int en7523_smi_mdio_pins[] = { 8, 9 };\n+static const int en7523_i2c_slave_pins[] = { 2, 3 };\n+static const int en7523_jtag_pins[] = { 22, 23, 24, 25, 26 };\n+static const int en7523_sipo_pins[] = { 1, 18, 26 };\n+static const int en7523_pcm1_pins[] = { 12, 13, 14, 15 };\n+static const int en7523_pcm2_pins[] = { 4, 5, 6, 7 };\n+static const int en7523_pcm_rst_pins[] = { 2 };\n+static const int en7523_pcm_int_pins[] = { 3 };\n+static const int en7523_slic_spi_cs1_pins[] = { 10 };\n+static const int en7523_slic_spi_cs2_pins[] = { 27 };\n+static const int en7523_slic_spi_cs3_pins[] = { 8 };\n+static const int en7523_slic_spi_cs4_pins[] = { 11 };\n+static const int en7523_pcie_reset0_pins[] = { 28 };\n+static const int en7523_pcie_reset1_pins[] = { 29 };\n+static const int en7523_gpio0_pins[] = { 0 };\n+static const int en7523_gpio1_pins[] = { 1 };\n+static const int en7523_gpio2_pins[] = { 2 };\n+static const int en7523_gpio3_pins[] = { 3 };\n+static const int en7523_gpio4_pins[] = { 4 };\n+static const int en7523_gpio5_pins[] = { 5 };\n+static const int en7523_gpio6_pins[] = { 6 };\n+static const int en7523_gpio7_pins[] = { 7 };\n+static const int en7523_gpio8_pins[] = { 8 };\n+static const int en7523_gpio9_pins[] = { 9 };\n+static const int en7523_gpio10_pins[] = { 10 };\n+static const int en7523_gpio11_pins[] = { 11 };\n+static const int en7523_gpio12_pins[] = { 12 };\n+static const int en7523_gpio13_pins[] = { 13 };\n+static const int en7523_gpio14_pins[] = { 14 };\n+static const int en7523_gpio15_pins[] = { 15 };\n+static const int en7523_gpio16_pins[] = { 16 };\n+static const int en7523_gpio17_pins[] = { 17 };\n+static const int en7523_gpio18_pins[] = { 18 };\n+static const int en7523_gpio19_pins[] = { 19 };\n+static const int en7523_gpio20_pins[] = { 20 };\n+static const int en7523_gpio21_pins[] = { 21 };\n+static const int en7523_gpio22_pins[] = { 22 };\n+static const int en7523_gpio23_pins[] = { 23 };\n+static const int en7523_gpio24_pins[] = { 24 };\n+static const int en7523_gpio25_pins[] = { 25 };\n+static const int en7523_gpio26_pins[] = { 26 };\n+static const int en7523_gpio27_pins[] = { 27 };\n+static const int en7523_gpio28_pins[] = { 28 };\n+static const int en7523_gpio29_pins[] = { 29 };\n+\n+static struct pinctrl_pin_desc en7523_pinctrl_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"zsync\"),\n+\tPINCTRL_PIN(13, \"zclk\"),\n+\tPINCTRL_PIN(14, \"zmosi\"),\n+\tPINCTRL_PIN(15, \"zmiso\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"pcie_reset0\"),\n+\tPINCTRL_PIN(29, \"pcie_reset1\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+\tPINCTRL_PIN(48, \"gpio48\"),\n+\tPINCTRL_PIN(49, \"gpio49\"),\n+\tPINCTRL_PIN(50, \"gpio50\"),\n+\tPINCTRL_PIN(51, \"gpio51\"),\n+\tPINCTRL_PIN(52, \"gpio52\"),\n+\tPINCTRL_PIN(53, \"gpio53\"),\n+\tPINCTRL_PIN(54, \"gpio54\"),\n+\tPINCTRL_PIN(55, \"gpio55\"),\n+\tPINCTRL_PIN(56, \"gpio56\"),\n+\tPINCTRL_PIN(57, \"gpio57\"),\n+};\n+\n+static const char *const en7523_uart2_groups[] = { \"uart2\" };\n+static const char *const en7523_smi_mdio_groups[] = { \"mdio\" };\n+static const char *const en7523_i2c_slave_groups[] = { \"i2c_slave\" };\n+static const char *const en7523_jtag_groups[] = { \"jtag\" };\n+static const char *const en7523_pcie_reset_groups[] = { \"pcie_reset0\", \"pcie_reset1\" };\n+static const char *const en7523_sipo_groups[] = { \"sipo\" };\n+static const char *const en7523_pcm_groups[] = { \"pcm1\", \"pcm2\", \"pcm_rst\", \"pcm_int\" };\n+static const char *const en7523_slic_spi_groups[] = { \"slic_spi_cs1\", \"slic_spi_cs2\",\n+\t\t\t\t\t\t \"slic_spi_cs3\", \"slic_spi_cs4\" };\n+static const char *const en7523_pwm_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\t\"gpio4\", \"gpio5\", \"gpio6\",\n+\t\"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\",\n+\t\"gpio21\", \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n+\t\"gpio28\", \"gpio29\",\n+};\n+static const char *const en7523_phy1_led0_groups[] = { \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\" };\n+static const char *const en7523_phy2_led0_groups[] = { \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\" };\n+static const char *const en7523_phy3_led0_groups[] = { \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\" };\n+static const char *const en7523_phy4_led0_groups[] = { \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\" };\n+static const char *const en7523_phy1_led1_groups[] = { \"gpio7\", \"gpio6\", \"gpio5\", \"gpio4\" };\n+static const char *const en7523_phy2_led1_groups[] = { \"gpio7\", \"gpio6\", \"gpio5\", \"gpio4\" };\n+static const char *const en7523_phy3_led1_groups[] = { \"gpio7\", \"gpio6\", \"gpio5\", \"gpio4\" };\n+static const char *const en7523_phy4_led1_groups[] = { \"gpio7\", \"gpio6\", \"gpio5\", \"gpio4\" };\n+\n+static const struct airoha_pinctrl_func_group en7523_uart2_func_group[] = {\n+\t{\n+\t\t.name = \"uart2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,\n+\t\t\t GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_smi_mdio_func_group[] = {\n+\t{\n+\t\t.name = \"mdio\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t GPIO_MDC_IO_MASTER_MODE_MODE,\n+\t\t\t GPIO_MDC_IO_MASTER_MODE_MODE },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_i2c_slave_func_group[] = {\n+\t{\n+\t\t.name = \"i2c_slave\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t GPIO_I2C_SLAVE_MODE_MODE,\n+\t\t\t GPIO_I2C_SLAVE_MODE_MODE },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_jtag_func_group[] = {\n+\t{\n+\t\t.name = \"jtag\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_NPU_UART_EN,\n+\t\t\t JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_pcie_reset_func_group[] = {\n+\t{\n+\t\t.name = \"pcie_reset0\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcie_reset1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_sipo_func_group[] = {\n+\t{\n+\t\t.name = \"sipo\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_PON_MODE,\n+\t\t\t GPIO_SIPO_MODE_MASK, GPIO_SIPO_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_pcm_func_group[] = {\n+\t{\n+\t\t.name = \"pcm1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_rst\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_RESET_MODE_MASK, GPIO_PCM_RESET_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_int\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_slic_spi_func_group[] = {\n+\t{\n+\t\t.name = \"slic_spi_cs1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS1_MODE_MASK, GPIO_PCM_SPI_CS1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"slic_spi_cs2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS2_MODE_P128_MASK,\n+\t\t\t GPIO_PCM_SPI_CS2_MODE_P128_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"slic_spi_cs3\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS3_MODE_MASK, GPIO_PCM_SPI_CS3_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"slic_spi_cs4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, EN7523_REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS4_MODE_MASK, GPIO_PCM_SPI_CS4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_pwm_func_group[] = {\n+\tAIROHA_PINCTRL_PWM(\"gpio0\", GPIO0_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio1\", GPIO1_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio2\", GPIO2_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio3\", GPIO3_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio4\", GPIO4_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio5\", GPIO5_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio6\", GPIO6_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio7\", GPIO7_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio8\", GPIO8_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio9\", GPIO9_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio10\", GPIO10_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio11\", GPIO11_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio12\", GPIO12_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio13\", GPIO13_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio14\", GPIO14_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio15\", GPIO15_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio16\", GPIO16_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio17\", GPIO17_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio18\", GPIO18_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio19\", GPIO19_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio20\", GPIO20_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio21\", GPIO21_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio22\", GPIO22_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio23\", GPIO23_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio24\", GPIO24_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio25\", GPIO25_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio26\", GPIO26_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio27\", GPIO27_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio28\", GPIO28_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio29\", GPIO29_FLASH_MODE_CFG),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy1_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio22\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio23\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio24\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio25\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy2_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio22\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio23\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio24\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio25\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy3_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio22\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio23\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio24\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio25\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy4_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio22\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio23\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio24\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(EN7523, \"gpio25\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy1_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio7\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio6\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio5\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio4\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy2_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio7\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio6\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio5\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio4\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy3_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio7\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio6\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio5\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio4\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group en7523_phy4_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio7\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio6\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio5\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(EN7523, \"gpio4\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct pingroup en7523_pinctrl_groups[] = {\n+\tPINCTRL_PIN_GROUP(\"uart2\", en7523_uart2),\n+\tPINCTRL_PIN_GROUP(\"mdio\", en7523_smi_mdio),\n+\tPINCTRL_PIN_GROUP(\"i2c_slave\", en7523_i2c_slave),\n+\tPINCTRL_PIN_GROUP(\"jtag\", en7523_jtag),\n+\tPINCTRL_PIN_GROUP(\"sipo\", en7523_sipo),\n+\tPINCTRL_PIN_GROUP(\"pcm1\", en7523_pcm1),\n+\tPINCTRL_PIN_GROUP(\"pcm2\", en7523_pcm2),\n+\tPINCTRL_PIN_GROUP(\"pcm_rst\", en7523_pcm_rst),\n+\tPINCTRL_PIN_GROUP(\"pcm_int\", en7523_pcm_int),\n+\tPINCTRL_PIN_GROUP(\"slic_spi_cs1\", en7523_slic_spi_cs1),\n+\tPINCTRL_PIN_GROUP(\"slic_spi_cs2\", en7523_slic_spi_cs2),\n+\tPINCTRL_PIN_GROUP(\"slic_spi_cs3\", en7523_slic_spi_cs3),\n+\tPINCTRL_PIN_GROUP(\"slic_spi_cs4\", en7523_slic_spi_cs4),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset0\", en7523_pcie_reset0),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset1\", en7523_pcie_reset1),\n+\tPINCTRL_PIN_GROUP(\"gpio0\", en7523_gpio0),\n+\tPINCTRL_PIN_GROUP(\"gpio1\", en7523_gpio1),\n+\tPINCTRL_PIN_GROUP(\"gpio2\", en7523_gpio2),\n+\tPINCTRL_PIN_GROUP(\"gpio3\", en7523_gpio3),\n+\tPINCTRL_PIN_GROUP(\"gpio4\", en7523_gpio4),\n+\tPINCTRL_PIN_GROUP(\"gpio5\", en7523_gpio5),\n+\tPINCTRL_PIN_GROUP(\"gpio6\", en7523_gpio6),\n+\tPINCTRL_PIN_GROUP(\"gpio7\", en7523_gpio7),\n+\tPINCTRL_PIN_GROUP(\"gpio8\", en7523_gpio8),\n+\tPINCTRL_PIN_GROUP(\"gpio9\", en7523_gpio9),\n+\tPINCTRL_PIN_GROUP(\"gpio10\", en7523_gpio10),\n+\tPINCTRL_PIN_GROUP(\"gpio11\", en7523_gpio11),\n+\tPINCTRL_PIN_GROUP(\"gpio12\", en7523_gpio12),\n+\tPINCTRL_PIN_GROUP(\"gpio13\", en7523_gpio13),\n+\tPINCTRL_PIN_GROUP(\"gpio14\", en7523_gpio14),\n+\tPINCTRL_PIN_GROUP(\"gpio15\", en7523_gpio15),\n+\tPINCTRL_PIN_GROUP(\"gpio16\", en7523_gpio16),\n+\tPINCTRL_PIN_GROUP(\"gpio17\", en7523_gpio17),\n+\tPINCTRL_PIN_GROUP(\"gpio18\", en7523_gpio18),\n+\tPINCTRL_PIN_GROUP(\"gpio19\", en7523_gpio19),\n+\tPINCTRL_PIN_GROUP(\"gpio20\", en7523_gpio20),\n+\tPINCTRL_PIN_GROUP(\"gpio21\", en7523_gpio21),\n+\tPINCTRL_PIN_GROUP(\"gpio22\", en7523_gpio22),\n+\tPINCTRL_PIN_GROUP(\"gpio23\", en7523_gpio23),\n+\tPINCTRL_PIN_GROUP(\"gpio24\", en7523_gpio24),\n+\tPINCTRL_PIN_GROUP(\"gpio25\", en7523_gpio25),\n+\tPINCTRL_PIN_GROUP(\"gpio26\", en7523_gpio26),\n+\tPINCTRL_PIN_GROUP(\"gpio27\", en7523_gpio27),\n+\tPINCTRL_PIN_GROUP(\"gpio28\", en7523_gpio28),\n+\tPINCTRL_PIN_GROUP(\"gpio29\", en7523_gpio29),\n+};\n+\n+static const struct airoha_pinctrl_func en7523_pinctrl_funcs[] = {\n+\tPINCTRL_FUNC_DESC(\"uart\", en7523_uart2),\n+\tPINCTRL_FUNC_DESC(\"mdio\", en7523_smi_mdio),\n+\tPINCTRL_FUNC_DESC(\"i2c\", en7523_i2c_slave),\n+\tPINCTRL_FUNC_DESC(\"jtag\", en7523_jtag),\n+\tPINCTRL_FUNC_DESC(\"pcie_reset\", en7523_pcie_reset),\n+\tPINCTRL_FUNC_DESC(\"sipo\", en7523_sipo),\n+\tPINCTRL_FUNC_DESC(\"pcm\", en7523_pcm),\n+\tPINCTRL_FUNC_DESC(\"slic_spi\", en7523_slic_spi),\n+\tPINCTRL_FUNC_DESC(\"pwm\", en7523_pwm),\n+\tPINCTRL_FUNC_DESC(\"phy1_led0\", en7523_phy1_led0),\n+\tPINCTRL_FUNC_DESC(\"phy1_led1\", en7523_phy1_led1),\n+\tPINCTRL_FUNC_DESC(\"phy2_led0\", en7523_phy2_led0),\n+\tPINCTRL_FUNC_DESC(\"phy2_led1\", en7523_phy2_led1),\n+\tPINCTRL_FUNC_DESC(\"phy3_led0\", en7523_phy3_led0),\n+\tPINCTRL_FUNC_DESC(\"phy3_led1\", en7523_phy3_led1),\n+\tPINCTRL_FUNC_DESC(\"phy4_led0\", en7523_phy4_led0),\n+\tPINCTRL_FUNC_DESC(\"phy4_led1\", en7523_phy4_led1),\n+};\n+\n+static const struct airoha_pinctrl_conf en7523_pinctrl_pullup_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_GPIO_L_PU, BIT(0)),\n+\tPINCTRL_CONF_DESC(1, REG_GPIO_L_PU, BIT(1)),\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(2)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(3)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(4)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(5)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(6)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(7)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(8)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(9)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(10)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(11)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(12)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(13)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(14)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(15)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(16)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(17)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(18)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(19)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(20)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(21)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(22)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(23)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(24)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(25)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(26)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(27)),\n+\tPINCTRL_CONF_DESC(28, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),\n+\tPINCTRL_CONF_DESC(29, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7523_pinctrl_pulldown_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_GPIO_L_PD, BIT(0)),\n+\tPINCTRL_CONF_DESC(1, REG_GPIO_L_PD, BIT(1)),\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(2)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(3)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(4)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(5)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(6)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(7)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(8)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(9)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(10)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(11)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(12)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(13)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(14)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(15)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(16)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(17)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(18)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(19)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(20)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(21)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(22)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(23)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(24)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(25)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(26)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(27)),\n+\tPINCTRL_CONF_DESC(28, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),\n+\tPINCTRL_CONF_DESC(29, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e2_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_GPIO_L_E2, BIT(0)),\n+\tPINCTRL_CONF_DESC(1, REG_GPIO_L_E2, BIT(1)),\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(2)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(3)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(4)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(5)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(6)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(7)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(8)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(9)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(10)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(11)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(12)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(13)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(14)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(15)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(16)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(17)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(18)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(19)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(20)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(21)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(22)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(23)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(24)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(25)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(26)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(27)),\n+\tPINCTRL_CONF_DESC(28, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),\n+\tPINCTRL_CONF_DESC(29, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e4_conf[] = {\n+\tPINCTRL_CONF_DESC(0, REG_GPIO_L_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(1, REG_GPIO_L_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(7)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),\n+\tPINCTRL_CONF_DESC(28, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),\n+\tPINCTRL_CONF_DESC(29, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf en7523_pinctrl_pcie_rst_od_conf[] = {\n+\tPINCTRL_CONF_DESC(28, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),\n+\tPINCTRL_CONF_DESC(29, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_match_data en7523_pinctrl_match_data = {\n+\t.gpio_offs = 0,\n+\t.gpio_pin_cnt = 58,\n+\t.pins = en7523_pinctrl_pins,\n+\t.num_pins = ARRAY_SIZE(en7523_pinctrl_pins),\n+\t.grps = en7523_pinctrl_groups,\n+\t.num_grps = ARRAY_SIZE(en7523_pinctrl_groups),\n+\t.funcs = en7523_pinctrl_funcs,\n+\t.num_funcs = ARRAY_SIZE(en7523_pinctrl_funcs),\n+\t.confs_info = {\n+\t\t[AIROHA_PINCTRL_CONFS_PULLUP] = {\n+\t\t\t.confs = en7523_pinctrl_pullup_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7523_pinctrl_pullup_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PULLDOWN] = {\n+\t\t\t.confs = en7523_pinctrl_pulldown_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7523_pinctrl_pulldown_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {\n+\t\t\t.confs = en7523_pinctrl_drive_e2_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7523_pinctrl_drive_e2_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {\n+\t\t\t.confs = en7523_pinctrl_drive_e4_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7523_pinctrl_drive_e4_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {\n+\t\t\t.confs = en7523_pinctrl_pcie_rst_od_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(en7523_pinctrl_pcie_rst_od_conf),\n+\t\t},\n+\t},\n+};\n+\n+static const struct udevice_id airoha_pinctrl_of_match[] = {\n+\t{ .compatible = \"airoha,en7523-pinctrl\",\n+\t .data = (uintptr_t)&en7523_pinctrl_match_data },\n+\t{ /* sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(airoha_pinctrl) = {\n+\t.name = \"airoha-en7523-pinctrl\",\n+\t.id = UCLASS_PINCTRL,\n+\t.of_match = of_match_ptr(airoha_pinctrl_of_match),\n+\t.probe = airoha_pinctrl_probe,\n+\t.bind = airoha_pinctrl_bind,\n+\t.priv_auto = sizeof(struct airoha_pinctrl),\n+\t.ops = &airoha_pinctrl_ops,\n+};\n", "prefixes": [ "v2", "4/6" ] }