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GET /api/1.1/patches/2229666/?format=api
{ "id": 2229666, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229666/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu>", "date": "2026-04-28T15:34:45", "name": "[v2,3/6] pinctrl: airoha: add pin controller and gpio driver for AN7583 SoC", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "51a3166eb3b02891112068d8210a9c2ba6448e6a", "submitter": { "id": 84987, "url": "http://patchwork.ozlabs.org/api/1.1/people/84987/?format=api", "name": "Mikhail Kshevetskiy", "email": "mikhail.kshevetskiy@iopsys.eu" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu/mbox/", "series": [ { "id": 501878, "url": "http://patchwork.ozlabs.org/api/1.1/series/501878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501878", "date": "2026-04-28T15:34:43", "name": "pinctrl: add support of Airoha SoCs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229666/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229666/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=iopsys.eu header.i=@iopsys.eu header.a=rsa-sha256\n header.s=selector1 header.b=RPm758uV;\n\tdkim-atps=neutral", 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b=RPm758uVekHwVu37PKuvCcEA0xTu3eikaukjZRn4A0pt10buCqUfZ5cLmKIlZ5S0vNaxBg4SsG+EpcY3bVgm/OwE00az24QY7MdcoV8dUYIn6NdOPcQtOB77Alfb3Un2/OK2EfEvF0MFlRL+hAcyyDGLD5JniH4BU3x6DS8DKvkxYe3Z2F2XoK0Kf51ABPdH23nbVoQVn0WsX675h8Oa16q+NU8POIbjH0zFjt47ahRJN7QdTYtGHALidFWhAFmnbKWYmefvmyGB782RBB1Ux4eGnK6Dfefa1SJcH2dcsFC3jhxcqiT+GOkkHRxj6tD+0JW54PH2TIgZpy47srO1Dw==", "From": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>", "To": "Tom Rini <trini@konsulko.com>, Christian Marangi <ansuelsmth@gmail.com>,\n Simon Glass <sjg@chromium.org>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>, Peng Fan <peng.fan@nxp.com>,\n Sean Anderson <sean.anderson@linux.dev>, Yao Zi <me@ziyao.cc>,\n Michal Simek <michal.simek@amd.com>, Anis Chali <chalianis1@gmail.com>,\n u-boot@lists.denx.de, Lorenzo Bianconi <lorenzo@kernel.org>,\n Markus Gothe <markus.gothe@genexis.eu>,\n Matheus Sampaio Queiroga <srherobrine20@gmail.com>,\n Benjamin Larsson <benjamin.larsson@genexis.eu>,\n David Lechner <dlechner@baylibre.com>", "Cc": "Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>", "Subject": "[PATCH v2 3/6] pinctrl: airoha: add pin controller and gpio driver\n for AN7583 SoC", "Date": "Tue, 28 Apr 2026 18:34:45 +0300", "Message-ID": "<20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260428153448.980150-1-mikhail.kshevetskiy@iopsys.eu>", "References": "<20260428153448.980150-1-mikhail.kshevetskiy@iopsys.eu>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "FR0P281CA0078.DEUP281.PROD.OUTLOOK.COM\n (2603:10a6:d10:1e::17) To DU2PR08MB10037.eurprd08.prod.outlook.com\n (2603:10a6:10:49a::20)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DU2PR08MB10037:EE_|PAXPR08MB6720:EE_", "X-MS-Office365-Filtering-Correlation-Id": "53f27c19-b425-49b2-547e-08dea53bb5d8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n 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"X-OriginatorOrg": "iopsys.eu", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 53f27c19-b425-49b2-547e-08dea53bb5d8", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR08MB10037.eurprd08.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Apr 2026 15:35:00.7386 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "8d891be1-7bce-4216-9a99-bee9de02ba58", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n XmvB/GEdrrQVktrs/5Up7BDYOECm5k9HIYMyZjCAvAGDrRxnvo/3Q+a2HpcfnBlDILxLcJjfps7XdNdx5Ms/XZFBgn6gRjYdTkxB2dPuqZw=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PAXPR08MB6720", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The driver based on official linux airoha pinctrl and gpio driver with\nMatheus Sampaio Queiroga <srherobrine20@gmail.com> changes.\nThe changes:\n * Separate code for each SoC and keep some of the functions in\n common between them,\n * Add pinctrl driver for EN7523 SoC.\n\nThe original Matheus Sampaio Queiroga driver can be taken from the repo:\n https://sirherobrine23.com.br/airoha_an7523/kernel/commits/branch/airoha_an7523_pinctrl\n\nThis patch adds U-Boot pin controller and gpio driver for Airoha AN7583 SoC.\n\nSigned-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>\n---\n drivers/pinctrl/airoha/Kconfig | 5 +\n drivers/pinctrl/airoha/Makefile | 1 +\n drivers/pinctrl/airoha/pinctrl-an7583.c | 966 ++++++++++++++++++++++++\n 3 files changed, 972 insertions(+)\n create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c", "diff": "diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig\nindex 986d23c2e3d..d9df89b20b7 100644\n--- a/drivers/pinctrl/airoha/Kconfig\n+++ b/drivers/pinctrl/airoha/Kconfig\n@@ -14,3 +14,8 @@ config PINCTRL_AIROHA_AN7581\n \ttristate \"AN7581 pin controller and gpio driver\"\n \tdepends on TARGET_AN7581\n \tselect PINCTRL_AIROHA\n+\n+config PINCTRL_AIROHA_AN7583\n+\ttristate \"AN7583 pin controller and gpio driver\"\n+\tdepends on TARGET_AN7583\n+\tselect PINCTRL_AIROHA\ndiff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile\nindex 909bd9a04d9..c8c99dd22f8 100644\n--- a/drivers/pinctrl/airoha/Makefile\n+++ b/drivers/pinctrl/airoha/Makefile\n@@ -3,3 +3,4 @@\n obj-$(CONFIG_PINCTRL_AIROHA)\t\t+= pinctrl-airoha.o\n \n obj-$(CONFIG_PINCTRL_AIROHA_AN7581)\t+= pinctrl-an7581.o\n+obj-$(CONFIG_PINCTRL_AIROHA_AN7583)\t+= pinctrl-an7583.o\ndiff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c\nnew file mode 100644\nindex 00000000000..5aa7e5d9172\n--- /dev/null\n+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c\n@@ -0,0 +1,966 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>\n+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>\n+ * Author: Markus Gothe <markus.gothe@genexis.eu>\n+ */\n+#include \"airoha-common.h\"\n+\n+static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };\n+static const int an7583_pon_tod_1pps_pins[] = { 32 };\n+static const int an7583_gsw_tod_1pps_pins[] = { 32 };\n+static const int an7583_sipo_pins[] = { 34, 35 };\n+static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };\n+static const int an7583_mdio_pins[] = { 43, 44 };\n+static const int an7583_uart2_pins[] = { 34, 35 };\n+static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };\n+static const int an7583_hsuart_pins[] = { 30, 31 };\n+static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };\n+static const int an7583_npu_uart_pins[] = { 7, 8 };\n+static const int an7583_uart4_pins[] = { 7, 8 };\n+static const int an7583_uart5_pins[] = { 23, 24 };\n+static const int an7583_i2c0_pins[] = { 41, 42 };\n+static const int an7583_i2c1_pins[] = { 43, 44 };\n+static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };\n+static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };\n+static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };\n+static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };\n+static const int an7583_spi_pins[] = { 28, 29, 30, 31 };\n+static const int an7583_spi_quad_pins[] = { 25, 26 };\n+static const int an7583_spi_cs1_pins[] = { 27 };\n+static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };\n+static const int an7583_pcm_spi_rst_pins[] = { 14 };\n+static const int an7583_pcm_spi_cs1_pins[] = { 24 };\n+static const int an7583_emmc_pins[] = {\n+\t7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47\n+};\n+static const int an7583_pnand_pins[] = { 7, 8,\t 9, 22, 23, 24, 25, 26, 27,\n+\t\t\t\t\t 28, 29, 30, 31, 45, 46, 47, 48 };\n+static const int an7583_gpio0_pins[] = { 2 };\n+static const int an7583_gpio1_pins[] = { 3 };\n+static const int an7583_gpio2_pins[] = { 4 };\n+static const int an7583_gpio3_pins[] = { 5 };\n+static const int an7583_gpio4_pins[] = { 6 };\n+static const int an7583_gpio5_pins[] = { 7 };\n+static const int an7583_gpio6_pins[] = { 8 };\n+static const int an7583_gpio7_pins[] = { 9 };\n+static const int an7583_gpio8_pins[] = { 10 };\n+static const int an7583_gpio9_pins[] = { 11 };\n+static const int an7583_gpio10_pins[] = { 12 };\n+static const int an7583_gpio11_pins[] = { 13 };\n+static const int an7583_gpio12_pins[] = { 14 };\n+static const int an7583_gpio13_pins[] = { 15 };\n+static const int an7583_gpio14_pins[] = { 16 };\n+static const int an7583_gpio15_pins[] = { 17 };\n+static const int an7583_gpio16_pins[] = { 18 };\n+static const int an7583_gpio17_pins[] = { 19 };\n+static const int an7583_gpio18_pins[] = { 20 };\n+static const int an7583_gpio19_pins[] = { 21 };\n+static const int an7583_gpio20_pins[] = { 22 };\n+static const int an7583_gpio21_pins[] = { 24 };\n+static const int an7583_gpio23_pins[] = { 25 };\n+static const int an7583_gpio24_pins[] = { 26 };\n+static const int an7583_gpio25_pins[] = { 27 };\n+static const int an7583_gpio26_pins[] = { 28 };\n+static const int an7583_gpio27_pins[] = { 29 };\n+static const int an7583_gpio28_pins[] = { 30 };\n+static const int an7583_gpio29_pins[] = { 31 };\n+static const int an7583_gpio30_pins[] = { 32 };\n+static const int an7583_gpio31_pins[] = { 33 };\n+static const int an7583_gpio33_pins[] = { 35 };\n+static const int an7583_gpio34_pins[] = { 36 };\n+static const int an7583_gpio35_pins[] = { 37 };\n+static const int an7583_gpio36_pins[] = { 38 };\n+static const int an7583_gpio37_pins[] = { 39 };\n+static const int an7583_gpio38_pins[] = { 40 };\n+static const int an7583_gpio39_pins[] = { 41 };\n+static const int an7583_gpio40_pins[] = { 42 };\n+static const int an7583_gpio41_pins[] = { 43 };\n+static const int an7583_gpio42_pins[] = { 44 };\n+static const int an7583_gpio43_pins[] = { 45 };\n+static const int an7583_gpio44_pins[] = { 46 };\n+static const int an7583_gpio45_pins[] = { 47 };\n+static const int an7583_gpio46_pins[] = { 48 };\n+static const int an7583_gpio47_pins[] = { 49 };\n+static const int an7583_gpio48_pins[] = { 50 };\n+static const int an7583_pcie_reset0_pins[] = { 51 };\n+static const int an7583_pcie_reset1_pins[] = { 52 };\n+\n+static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {\n+\tPINCTRL_PIN(2, \"gpio0\"),\n+\tPINCTRL_PIN(3, \"gpio1\"),\n+\tPINCTRL_PIN(4, \"gpio2\"),\n+\tPINCTRL_PIN(5, \"gpio3\"),\n+\tPINCTRL_PIN(6, \"gpio4\"),\n+\tPINCTRL_PIN(7, \"gpio5\"),\n+\tPINCTRL_PIN(8, \"gpio6\"),\n+\tPINCTRL_PIN(9, \"gpio7\"),\n+\tPINCTRL_PIN(10, \"gpio8\"),\n+\tPINCTRL_PIN(11, \"gpio9\"),\n+\tPINCTRL_PIN(12, \"gpio10\"),\n+\tPINCTRL_PIN(13, \"gpio11\"),\n+\tPINCTRL_PIN(14, \"gpio12\"),\n+\tPINCTRL_PIN(15, \"gpio13\"),\n+\tPINCTRL_PIN(16, \"gpio14\"),\n+\tPINCTRL_PIN(17, \"gpio15\"),\n+\tPINCTRL_PIN(18, \"gpio16\"),\n+\tPINCTRL_PIN(19, \"gpio17\"),\n+\tPINCTRL_PIN(20, \"gpio18\"),\n+\tPINCTRL_PIN(21, \"gpio19\"),\n+\tPINCTRL_PIN(22, \"gpio20\"),\n+\tPINCTRL_PIN(23, \"gpio21\"),\n+\tPINCTRL_PIN(24, \"gpio22\"),\n+\tPINCTRL_PIN(25, \"gpio23\"),\n+\tPINCTRL_PIN(26, \"gpio24\"),\n+\tPINCTRL_PIN(27, \"gpio25\"),\n+\tPINCTRL_PIN(28, \"gpio26\"),\n+\tPINCTRL_PIN(29, \"gpio27\"),\n+\tPINCTRL_PIN(30, \"gpio28\"),\n+\tPINCTRL_PIN(31, \"gpio29\"),\n+\tPINCTRL_PIN(32, \"gpio30\"),\n+\tPINCTRL_PIN(33, \"gpio31\"),\n+\tPINCTRL_PIN(34, \"gpio32\"),\n+\tPINCTRL_PIN(35, \"gpio33\"),\n+\tPINCTRL_PIN(36, \"gpio34\"),\n+\tPINCTRL_PIN(37, \"gpio35\"),\n+\tPINCTRL_PIN(38, \"gpio36\"),\n+\tPINCTRL_PIN(39, \"gpio37\"),\n+\tPINCTRL_PIN(40, \"gpio38\"),\n+\tPINCTRL_PIN(41, \"i2c0_scl\"),\n+\tPINCTRL_PIN(42, \"i2c0_sda\"),\n+\tPINCTRL_PIN(43, \"i2c1_scl\"),\n+\tPINCTRL_PIN(44, \"i2c1_sda\"),\n+\tPINCTRL_PIN(45, \"spi_clk\"),\n+\tPINCTRL_PIN(46, \"spi_cs\"),\n+\tPINCTRL_PIN(47, \"spi_mosi\"),\n+\tPINCTRL_PIN(48, \"spi_miso\"),\n+\tPINCTRL_PIN(49, \"uart_txd\"),\n+\tPINCTRL_PIN(50, \"uart_rxd\"),\n+\tPINCTRL_PIN(51, \"pcie_reset0\"),\n+\tPINCTRL_PIN(52, \"pcie_reset1\"),\n+\tPINCTRL_PIN(53, \"mdc_0\"),\n+\tPINCTRL_PIN(54, \"mdio_0\"),\n+};\n+\n+static const char *const pon_groups[] = { \"pon\" };\n+static const char *const tod_1pps_groups[] = { \"pon_tod_1pps\", \"gsw_tod_1pps\" };\n+static const char *const sipo_groups[] = { \"sipo\", \"sipo_rclk\" };\n+\n+static const char *const uart_groups[] = { \"uart2\", \"uart2_cts_rts\",\n+\t\t\t\t\t \"hsuart\", \"hsuart_cts_rts\",\n+\t\t\t\t\t \"uart4\", \"uart5\" };\n+static const char *const i2c_groups[] = { \"i2c1\" };\n+static const char *const jtag_groups[] = { \"jtag_udi\", \"jtag_dfd\" };\n+static const char *const pcm_groups[] = { \"pcm1\", \"pcm2\" };\n+static const char *const spi_groups[] = { \"spi_quad\", \"spi_cs1\" };\n+\n+static const char *const emmc_groups[] = { \"emmc\" };\n+static const char *const pnand_groups[] = { \"pnand\" };\n+static const char *const pwm_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\t\"gpio4\", \"gpio5\", \"gpio6\",\n+\t\"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+\t\"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\",\n+\t\"gpio21\", \"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\",\n+\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio36\", \"gpio37\", \"gpio38\",\n+\t\"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\"gpio46\", \"gpio47\"\n+};\n+\n+static const char *const an7583_mdio_groups[] = { \"mdio\" };\n+static const char *const an7583_pcm_spi_groups[] = {\n+\t\"pcm_spi\", \"pcm_spi_int\", \"pcm_spi_rst\", \"pcm_spi_cs1\",\n+\t\"pcm_spi_cs2\", \"pcm_spi_cs3\", \"pcm_spi_cs4\"\n+};\n+static const char *const an7583_pcie_reset_groups[] = { \"pcie_reset0\",\n+\t\t\t\t\t\t\t\"pcie_reset1\" };\n+static const char *const an7583_phy1_led0_groups[] = { \"gpio1\", \"gpio2\",\n+\t\t\t\t\t\t \"gpio3\", \"gpio4\" };\n+static const char *const an7583_phy2_led0_groups[] = { \"gpio1\", \"gpio2\",\n+\t\t\t\t\t\t \"gpio3\", \"gpio4\" };\n+static const char *const an7583_phy3_led0_groups[] = { \"gpio1\", \"gpio2\",\n+\t\t\t\t\t\t \"gpio3\", \"gpio4\" };\n+static const char *const an7583_phy4_led0_groups[] = { \"gpio1\", \"gpio2\",\n+\t\t\t\t\t\t \"gpio3\", \"gpio4\" };\n+static const char *const an7583_phy1_led1_groups[] = { \"gpio8\", \"gpio9\",\n+\t\t\t\t\t\t \"gpio10\", \"gpio11\" };\n+static const char *const an7583_phy2_led1_groups[] = { \"gpio8\", \"gpio9\",\n+\t\t\t\t\t\t \"gpio10\", \"gpio11\" };\n+static const char *const an7583_phy3_led1_groups[] = { \"gpio8\", \"gpio9\",\n+\t\t\t\t\t\t \"gpio10\", \"gpio11\" };\n+static const char *const an7583_phy4_led1_groups[] = { \"gpio8\", \"gpio9\",\n+\t\t\t\t\t\t \"gpio10\", \"gpio11\" };\n+\n+static const struct airoha_pinctrl_func_group pon_func_group[] = {\n+\t{\n+\t\t.name = \"pon\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PON_MODE_MASK, GPIO_PON_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {\n+\t{\n+\t\t.name = \"pon_tod_1pps\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"gsw_tod_1pps\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group sipo_func_group[] = {\n+\t{\n+\t\t.name = \"sipo\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,\n+\t\t\t GPIO_SIPO_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"sipo_rclk\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,\n+\t\t\t GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group uart_func_group[] = {\n+\t{\n+\t\t.name = \"uart2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart2_cts_rts\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_UART2_MODE_MASK |\n+\t\t\t\t GPIO_UART2_CTS_RTS_MODE_MASK,\n+\t\t\t GPIO_UART2_MODE_MASK |\n+\t\t\t\t GPIO_UART2_CTS_RTS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"hsuart\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_HSUART_MODE_MASK |\n+\t\t\t\t GPIO_HSUART_CTS_RTS_MODE_MASK,\n+\t\t\t GPIO_HSUART_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"hsuart_cts_rts\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_HSUART_MODE_MASK |\n+\t\t\t\t GPIO_HSUART_CTS_RTS_MODE_MASK,\n+\t\t\t GPIO_HSUART_MODE_MASK |\n+\t\t\t\t GPIO_HSUART_CTS_RTS_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_UART4_MODE_MASK, GPIO_UART4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"uart5\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_UART5_MODE_MASK, GPIO_UART5_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group i2c_func_group[] = {\n+\t{\n+\t\t.name = \"i2c1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, AN7581_REG_GPIO_2ND_I2C_MODE,\n+\t\t\t GPIO_2ND_I2C_MODE_MASK, GPIO_2ND_I2C_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group jtag_func_group[] = {\n+\t{\n+\t\t.name = \"jtag_udi\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN,\n+\t\t\t JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"jtag_dfd\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN,\n+\t\t\t JTAG_DFD_EN_MASK, JTAG_DFD_EN_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pcm_func_group[] = {\n+\t{\n+\t\t.name = \"pcm1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group spi_func_group[] = {\n+\t{\n+\t\t.name = \"spi_quad\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_SPI_QUAD_MODE_MASK,\n+\t\t\t GPIO_SPI_QUAD_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs3\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"spi_cs4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group emmc_func_group[] = {\n+\t{\n+\t\t.name = \"emmc\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_EMMC_MODE_MASK, GPIO_EMMC_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pnand_func_group[] = {\n+\t{\n+\t\t.name = \"pnand\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PARALLEL_NAND_MODE_MASK,\n+\t\t\t GPIO_PARALLEL_NAND_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group pwm_func_group[] = {\n+\tAIROHA_PINCTRL_PWM(\"gpio0\", GPIO0_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio1\", GPIO1_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio2\", GPIO2_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio3\", GPIO3_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio4\", GPIO4_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio5\", GPIO5_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio6\", GPIO6_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio7\", GPIO7_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio8\", GPIO8_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio9\", GPIO9_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio10\", GPIO10_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio11\", GPIO11_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio12\", GPIO12_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio13\", GPIO13_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio14\", GPIO14_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM(\"gpio15\", GPIO15_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio16\", GPIO16_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio17\", GPIO17_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio18\", GPIO18_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio19\", GPIO19_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio20\", GPIO20_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio21\", GPIO21_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio22\", GPIO22_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio23\", GPIO23_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio24\", GPIO24_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio25\", GPIO25_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio26\", GPIO26_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio27\", GPIO27_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio28\", GPIO28_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio29\", GPIO29_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio30\", GPIO30_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio31\", GPIO31_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio36\", GPIO36_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio37\", GPIO37_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio38\", GPIO38_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio39\", GPIO39_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio40\", GPIO40_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio41\", GPIO41_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio42\", GPIO42_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio43\", GPIO43_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio44\", GPIO44_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio45\", GPIO45_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio46\", GPIO46_FLASH_MODE_CFG),\n+\tAIROHA_PINCTRL_PWM_EXT(\"gpio47\", GPIO47_FLASH_MODE_CFG),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {\n+\t{\n+\t\t.name = \"mdio\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_SGMII_MDIO_MODE_MASK,\n+\t\t\t GPIO_SGMII_MDIO_MODE_MASK },\n+\t\t.regmap[1] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_MDC_IO_MASTER_MODE_MODE,\n+\t\t\t GPIO_MDC_IO_MASTER_MODE_MODE },\n+\t\t.regmap_size = 2,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {\n+\t{\n+\t\t.name = \"pcm_spi\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_MODE_MASK, GPIO_PCM_SPI_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_int\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_rst\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_RESET_MODE_MASK,\n+\t\t\t GPIO_PCM_RESET_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS1_MODE_MASK,\n+\t\t\t GPIO_PCM_SPI_CS1_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs2\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,\n+\t\t\t AN7583_GPIO_PCM_SPI_CS2_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs3\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS3_MODE_MASK,\n+\t\t\t GPIO_PCM_SPI_CS3_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcm_spi_cs4\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE,\n+\t\t\t GPIO_PCM_SPI_CS4_MODE_MASK,\n+\t\t\t GPIO_PCM_SPI_CS4_MODE_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {\n+\t{\n+\t\t.name = \"pcie_reset0\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+\t{\n+\t\t.name = \"pcie_reset1\",\n+\t\t.regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE,\n+\t\t\t GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK },\n+\t\t.regmap_size = 1,\n+\t},\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio1\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio2\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio3\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio4\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio1\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio2\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio3\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio4\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio1\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio2\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio3\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio4\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio1\", GPIO_LAN0_LED0_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio2\", GPIO_LAN1_LED0_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio3\", GPIO_LAN2_LED0_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),\n+\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio4\", GPIO_LAN3_LED0_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio1\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n+\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n+\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n+\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n+\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n+\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n+};\n+\n+static const struct pingroup an7583_pinctrl_groups[] = {\n+\tPINCTRL_PIN_GROUP(\"pon\", an7583_pon),\n+\tPINCTRL_PIN_GROUP(\"pon_tod_1pps\", an7583_pon_tod_1pps),\n+\tPINCTRL_PIN_GROUP(\"gsw_tod_1pps\", an7583_gsw_tod_1pps),\n+\tPINCTRL_PIN_GROUP(\"sipo\", an7583_sipo),\n+\tPINCTRL_PIN_GROUP(\"sipo_rclk\", an7583_sipo_rclk),\n+\tPINCTRL_PIN_GROUP(\"mdio\", an7583_mdio),\n+\tPINCTRL_PIN_GROUP(\"uart2\", an7583_uart2),\n+\tPINCTRL_PIN_GROUP(\"uart2_cts_rts\", an7583_uart2_cts_rts),\n+\tPINCTRL_PIN_GROUP(\"hsuart\", an7583_hsuart),\n+\tPINCTRL_PIN_GROUP(\"hsuart_cts_rts\", an7583_hsuart_cts_rts),\n+\tPINCTRL_PIN_GROUP(\"npu_uart\", an7583_npu_uart),\n+\tPINCTRL_PIN_GROUP(\"uart4\", an7583_uart4),\n+\tPINCTRL_PIN_GROUP(\"uart5\", an7583_uart5),\n+\tPINCTRL_PIN_GROUP(\"i2c0\", an7583_i2c0),\n+\tPINCTRL_PIN_GROUP(\"i2c1\", an7583_i2c1),\n+\tPINCTRL_PIN_GROUP(\"jtag_udi\", an7583_jtag_udi),\n+\tPINCTRL_PIN_GROUP(\"jtag_dfd\", an7583_jtag_dfd),\n+\tPINCTRL_PIN_GROUP(\"pcm1\", an7583_pcm1),\n+\tPINCTRL_PIN_GROUP(\"pcm2\", an7583_pcm2),\n+\tPINCTRL_PIN_GROUP(\"spi\", an7583_spi),\n+\tPINCTRL_PIN_GROUP(\"spi_quad\", an7583_spi_quad),\n+\tPINCTRL_PIN_GROUP(\"spi_cs1\", an7583_spi_cs1),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi\", an7583_pcm_spi),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_rst\", an7583_pcm_spi_rst),\n+\tPINCTRL_PIN_GROUP(\"pcm_spi_cs1\", an7583_pcm_spi_cs1),\n+\tPINCTRL_PIN_GROUP(\"emmc\", an7583_emmc),\n+\tPINCTRL_PIN_GROUP(\"pnand\", an7583_pnand),\n+\tPINCTRL_PIN_GROUP(\"gpio0\", an7583_gpio0),\n+\tPINCTRL_PIN_GROUP(\"gpio1\", an7583_gpio1),\n+\tPINCTRL_PIN_GROUP(\"gpio2\", an7583_gpio2),\n+\tPINCTRL_PIN_GROUP(\"gpio3\", an7583_gpio3),\n+\tPINCTRL_PIN_GROUP(\"gpio4\", an7583_gpio4),\n+\tPINCTRL_PIN_GROUP(\"gpio5\", an7583_gpio5),\n+\tPINCTRL_PIN_GROUP(\"gpio6\", an7583_gpio6),\n+\tPINCTRL_PIN_GROUP(\"gpio7\", an7583_gpio7),\n+\tPINCTRL_PIN_GROUP(\"gpio8\", an7583_gpio8),\n+\tPINCTRL_PIN_GROUP(\"gpio9\", an7583_gpio9),\n+\tPINCTRL_PIN_GROUP(\"gpio10\", an7583_gpio10),\n+\tPINCTRL_PIN_GROUP(\"gpio11\", an7583_gpio11),\n+\tPINCTRL_PIN_GROUP(\"gpio12\", an7583_gpio12),\n+\tPINCTRL_PIN_GROUP(\"gpio13\", an7583_gpio13),\n+\tPINCTRL_PIN_GROUP(\"gpio14\", an7583_gpio14),\n+\tPINCTRL_PIN_GROUP(\"gpio15\", an7583_gpio15),\n+\tPINCTRL_PIN_GROUP(\"gpio16\", an7583_gpio16),\n+\tPINCTRL_PIN_GROUP(\"gpio17\", an7583_gpio17),\n+\tPINCTRL_PIN_GROUP(\"gpio18\", an7583_gpio18),\n+\tPINCTRL_PIN_GROUP(\"gpio19\", an7583_gpio19),\n+\tPINCTRL_PIN_GROUP(\"gpio20\", an7583_gpio20),\n+\tPINCTRL_PIN_GROUP(\"gpio21\", an7583_gpio21),\n+\tPINCTRL_PIN_GROUP(\"gpio23\", an7583_gpio23),\n+\tPINCTRL_PIN_GROUP(\"gpio24\", an7583_gpio24),\n+\tPINCTRL_PIN_GROUP(\"gpio25\", an7583_gpio25),\n+\tPINCTRL_PIN_GROUP(\"gpio26\", an7583_gpio26),\n+\tPINCTRL_PIN_GROUP(\"gpio27\", an7583_gpio27),\n+\tPINCTRL_PIN_GROUP(\"gpio28\", an7583_gpio28),\n+\tPINCTRL_PIN_GROUP(\"gpio29\", an7583_gpio29),\n+\tPINCTRL_PIN_GROUP(\"gpio30\", an7583_gpio30),\n+\tPINCTRL_PIN_GROUP(\"gpio31\", an7583_gpio31),\n+\tPINCTRL_PIN_GROUP(\"gpio33\", an7583_gpio33),\n+\tPINCTRL_PIN_GROUP(\"gpio34\", an7583_gpio34),\n+\tPINCTRL_PIN_GROUP(\"gpio35\", an7583_gpio35),\n+\tPINCTRL_PIN_GROUP(\"gpio36\", an7583_gpio36),\n+\tPINCTRL_PIN_GROUP(\"gpio37\", an7583_gpio37),\n+\tPINCTRL_PIN_GROUP(\"gpio38\", an7583_gpio38),\n+\tPINCTRL_PIN_GROUP(\"gpio39\", an7583_gpio39),\n+\tPINCTRL_PIN_GROUP(\"gpio40\", an7583_gpio40),\n+\tPINCTRL_PIN_GROUP(\"gpio41\", an7583_gpio41),\n+\tPINCTRL_PIN_GROUP(\"gpio42\", an7583_gpio42),\n+\tPINCTRL_PIN_GROUP(\"gpio43\", an7583_gpio43),\n+\tPINCTRL_PIN_GROUP(\"gpio44\", an7583_gpio44),\n+\tPINCTRL_PIN_GROUP(\"gpio45\", an7583_gpio45),\n+\tPINCTRL_PIN_GROUP(\"gpio46\", an7583_gpio46),\n+\tPINCTRL_PIN_GROUP(\"gpio47\", an7583_gpio47),\n+\tPINCTRL_PIN_GROUP(\"gpio48\", an7583_gpio48),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset0\", an7583_pcie_reset0),\n+\tPINCTRL_PIN_GROUP(\"pcie_reset1\", an7583_pcie_reset1),\n+};\n+\n+static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {\n+\tPINCTRL_FUNC_DESC(\"pon\", pon),\n+\tPINCTRL_FUNC_DESC(\"tod_1pps\", tod_1pps),\n+\tPINCTRL_FUNC_DESC(\"sipo\", sipo),\n+\tPINCTRL_FUNC_DESC(\"mdio\", an7583_mdio),\n+\tPINCTRL_FUNC_DESC(\"uart\", uart),\n+\tPINCTRL_FUNC_DESC(\"i2c\", i2c),\n+\tPINCTRL_FUNC_DESC(\"jtag\", jtag),\n+\tPINCTRL_FUNC_DESC(\"pcm\", pcm),\n+\tPINCTRL_FUNC_DESC(\"spi\", spi),\n+\tPINCTRL_FUNC_DESC(\"pcm_spi\", an7583_pcm_spi),\n+\tPINCTRL_FUNC_DESC(\"emmc\", emmc),\n+\tPINCTRL_FUNC_DESC(\"pnand\", pnand),\n+\tPINCTRL_FUNC_DESC(\"pcie_reset\", an7583_pcie_reset),\n+\tPINCTRL_FUNC_DESC(\"pwm\", pwm),\n+\tPINCTRL_FUNC_DESC(\"phy1_led0\", an7583_phy1_led0),\n+\tPINCTRL_FUNC_DESC(\"phy2_led0\", an7583_phy2_led0),\n+\tPINCTRL_FUNC_DESC(\"phy3_led0\", an7583_phy3_led0),\n+\tPINCTRL_FUNC_DESC(\"phy4_led0\", an7583_phy4_led0),\n+\tPINCTRL_FUNC_DESC(\"phy1_led1\", an7583_phy1_led1),\n+\tPINCTRL_FUNC_DESC(\"phy2_led1\", an7583_phy2_led1),\n+\tPINCTRL_FUNC_DESC(\"phy3_led1\", an7583_phy3_led1),\n+\tPINCTRL_FUNC_DESC(\"phy4_led1\", an7583_phy4_led1),\n+};\n+\n+static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),\n+\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),\n+\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),\n+\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),\n+\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),\n+\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),\n+\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),\n+\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),\n+\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),\n+\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),\n+\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),\n+\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),\n+\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),\n+\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),\n+\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),\n+\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),\n+\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),\n+\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),\n+\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),\n+\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),\n+\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),\n+\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),\n+\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),\n+\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),\n+\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),\n+\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),\n+\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),\n+\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),\n+\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),\n+\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),\n+\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),\n+\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),\n+\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),\n+\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),\n+\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),\n+\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),\n+\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),\n+\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),\n+\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),\n+\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),\n+\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),\n+\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),\n+\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {\n+\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),\n+\tPINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),\n+\tPINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),\n+\tPINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),\n+\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),\n+\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),\n+\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),\n+\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),\n+\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),\n+\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),\n+\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),\n+\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),\n+\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),\n+\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),\n+\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),\n+\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),\n+\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),\n+\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),\n+\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),\n+\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),\n+\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),\n+\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),\n+\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),\n+\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),\n+\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),\n+\tPINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),\n+\tPINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),\n+\tPINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),\n+\tPINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),\n+\tPINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),\n+\tPINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),\n+\tPINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),\n+\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),\n+\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),\n+\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),\n+\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),\n+\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),\n+\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),\n+\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),\n+\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),\n+\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),\n+\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),\n+\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),\n+\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),\n+\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),\n+\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),\n+};\n+\n+static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {\n+\tPINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),\n+\tPINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),\n+};\n+\n+static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {\n+\t.gpio_offs = 2,\n+\t.gpio_pin_cnt = 53,\n+\t.pins = an7583_pinctrl_pins,\n+\t.num_pins = ARRAY_SIZE(an7583_pinctrl_pins),\n+\t.grps = an7583_pinctrl_groups,\n+\t.num_grps = ARRAY_SIZE(an7583_pinctrl_groups),\n+\t.funcs = an7583_pinctrl_funcs,\n+\t.num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),\n+\t.confs_info = {\n+\t\t[AIROHA_PINCTRL_CONFS_PULLUP] = {\n+\t\t\t.confs = an7583_pinctrl_pullup_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PULLDOWN] = {\n+\t\t\t.confs = an7583_pinctrl_pulldown_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {\n+\t\t\t.confs = an7583_pinctrl_drive_e2_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {\n+\t\t\t.confs = an7583_pinctrl_drive_e4_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),\n+\t\t},\n+\t\t[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {\n+\t\t\t.confs = an7583_pinctrl_pcie_rst_od_conf,\n+\t\t\t.num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),\n+\t\t},\n+\t},\n+};\n+\n+static const struct udevice_id airoha_pinctrl_of_match[] = {\n+\t{ .compatible = \"airoha,an7583-pinctrl\",\n+\t .data = (uintptr_t)&an7583_pinctrl_match_data },\n+\t{ /* sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(airoha_pinctrl) = {\n+\t.name = \"airoha-an7583-pinctrl\",\n+\t.id = UCLASS_PINCTRL,\n+\t.of_match = of_match_ptr(airoha_pinctrl_of_match),\n+\t.probe = airoha_pinctrl_probe,\n+\t.bind = airoha_pinctrl_bind,\n+\t.priv_auto = sizeof(struct airoha_pinctrl),\n+\t.ops = &airoha_pinctrl_ops,\n+};\n", "prefixes": [ "v2", "3/6" ] }