[{"id":3683710,"web_url":"http://patchwork.ozlabs.org/comment/3683710/","msgid":"<72f227d7-20ba-451e-a847-a58e309d61f2@baylibre.com>","list_archive_url":null,"date":"2026-04-28T20:48:57","subject":"Re: [PATCH v2 3/6] pinctrl: airoha: add pin controller and gpio\n driver for AN7583 SoC","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/people/87228/","name":"David Lechner","email":"dlechner@baylibre.com"},"content":"On 4/28/26 10:34 AM, Mikhail Kshevetskiy wrote:\n> The driver based on official linux airoha pinctrl and gpio driver with\n> Matheus Sampaio Queiroga changes.\n> The changes:\n> * Separate code for each SoC and keep some of the functions in\n> common between them,\n> * Add pinctrl driver for EN7523 SoC.\n> \n> The original Matheus Sampaio Queiroga driver can be taken from the repo:\n> https://sirherobrine23.com.br/airoha_an7523/kernel/commits/branch/airoha_an7523_pinctrl\n> \n> This patch adds U-Boot pin controller and gpio driver for Airoha AN7583 SoC.\n> \n> Signed-off-by: Mikhail Kshevetskiy \n> ---\n\nSame comments about subject, commit message, general code style from other\npatches applies here as well.\n\n> +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio1\", GPIO_LAN0_LED0_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),\n> +\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio2\", GPIO_LAN1_LED0_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),\n> +\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio3\", GPIO_LAN2_LED0_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),\n> +\tAIROHA_PINCTRL_PHY_LED0(AN7581, \"gpio4\", GPIO_LAN3_LED0_MODE_MASK,\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),\n> +};\n> +\n> +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio1\", GPIO_LAN3_LED1_MODE_MASK,\n\nIs this supposed to be gpio11? It doesn't match the pattern of the others.\n\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),\n> +};\n> +\n> +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),\n> +};\n> +\n> +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n> +};\n> +\n> +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio8\", GPIO_LAN0_LED1_MODE_MASK,\n> +\t\t\t\tLAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio9\", GPIO_LAN1_LED1_MODE_MASK,\n> +\t\t\t\tLAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio10\", GPIO_LAN2_LED1_MODE_MASK,\n> +\t\t\t\tLAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),\n> +\tAIROHA_PINCTRL_PHY_LED1(AN7581, \"gpio11\", GPIO_LAN3_LED1_MODE_MASK,\n> +\t\t\t\tLAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),\n\nAre these supposed to be LANX_PHY_LED_MAP(3) instead of 2?\n\n> +};\n> +\n\n...\n\n> +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {\n> +\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),\n> +\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),\n> +\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),\n> +\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),\n> +\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),\n> +\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),\n> +\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),\n> +\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),\n> +\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),\n> +\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),\n> +\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),\n> +\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),\n> +\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),\n> +\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),\n> +\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),\n> +\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),\n> +\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),\n> +\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),\n> +\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),\n> +\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),\n> +\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),\n> +\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),\n> +\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),\n> +\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),\n> +\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),\n> +};\n> +\n> +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {\n> +\tPINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),\n> +\tPINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),\n> +\tPINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),\n> +\tPINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),\n> +\tPINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),\n> +\tPINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),\n> +\tPINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),\n> +\tPINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),\n> +\tPINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),\n> +\tPINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),\n> +\tPINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),\n> +\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),\n> +\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),\n> +\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),\n> +\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),\n> +\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),\n> +\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),\n> +\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),\n> +\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),\n> +\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),\n> +\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),\n> +\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),\n> +\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),\n> +\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),\n> +\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),\n> +};\n> +\n> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {\n> +\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),\n> +\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),\n> +\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),\n> +\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),\n> +\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),\n> +\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),\n> +\tPINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),\n> +\tPINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),\n> +\tPINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),\n> +\tPINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),\n> +\tPINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),\n> +\tPINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),\n> +\tPINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),\n> +\tPINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),\n> +\tPINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),\n> +\tPINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),\n> +\tPINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),\n> +\tPINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),\n> +\tPINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),\n> +\tPINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),\n> +\tPINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),\n> +\tPINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),\n> +\tPINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),\n> +\tPINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),\n> +\tPINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),\n> +\tPINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),\n> +\tPINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),\n> +\tPINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),\n> +\tPINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),\n> +\tPINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),\n> +\tPINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),\n> +\tPINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),\n> +\tPINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),\n> +\tPINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),\n> +\tPINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),\n> +\tPINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),\n> +\tPINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),\n> +\tPINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),\n> +\tPINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),\n> +\tPINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),\n> +};\n> +\n> +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {\n> +\tPINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),\n> +\tPINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),\n> +\tPINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),\n> +\tPINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),\n> +\tPINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),\n> +\tPINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),\n> +\tPINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),\n> +\tPINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),\n> +\tPINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),\n> +\tPINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),\n> +\tPINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),\n> +\tPINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),\n> +\tPINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),\n> +\tPINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),\n> +\tPINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),\n> +\tPINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),\n> +\tPINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),\n> +\tPINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),\n> +\tPINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),\n> +\tPINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),\n\nIs this supposed to be BIT(19)?\n\n> +\tPINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),\n> +\tPINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),\n> +\tPINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),\n> +\tPINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),\n\n..\n\n> +U_BOOT_DRIVER(airoha_pinctrl) = {\n\nairoha_an7583_pinctrl\n\n> +\t.name = \"airoha-an7583-pinctrl\",\n> +\t.id = UCLASS_PINCTRL,\n> +\t.of_match = of_match_ptr(airoha_pinctrl_of_match),\n> +\t.probe = airoha_pinctrl_probe,\n> +\t.bind = airoha_pinctrl_bind,\n> +\t.priv_auto = sizeof(struct airoha_pinctrl),\n> +\t.ops = &airoha_pinctrl_ops,\n> +};","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20251104.gappssmtp.com\n header.i=@baylibre-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=LYdQmnLp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=baylibre.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) 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Sampaio Queiroga ,\n Benjamin Larsson ","References":"<20260428153448.980150-1-mikhail.kshevetskiy@iopsys.eu>\n <20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu>","Content-Language":"en-US","From":"David Lechner ","In-Reply-To":"<20260428153448.980150-4-mikhail.kshevetskiy@iopsys.eu>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}}]