Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2229598/?format=api
{ "id": 2229598, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229598/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428135053.251200-4-dblanzeanu@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428135053.251200-4-dblanzeanu@linux.microsoft.com>", "date": "2026-04-28T13:50:50", "name": "[3/6] include/hw/hyperv: add hv_vp_register_page struct definition", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d8ac71041d8af387432458fb1a3b9986a2348938", "submitter": { "id": 93106, "url": "http://patchwork.ozlabs.org/api/1.1/people/93106/?format=api", "name": "Doru Blânzeanu", "email": "dblanzeanu@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428135053.251200-4-dblanzeanu@linux.microsoft.com/mbox/", "series": [ { "id": 501862, "url": "http://patchwork.ozlabs.org/api/1.1/series/501862/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501862", "date": "2026-04-28T13:50:49", "name": "target/i386/mshv: use hv_vp_register_page for fast register access", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501862/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229598/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229598/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=LYhAsljs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4hv84MlHz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 00:01:56 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHizs-00040Y-IB; Tue, 28 Apr 2026 10:01:09 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dblanzeanu@linux.microsoft.com>)\n id 1wHiqD-0002Ti-Bq\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:09 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <dblanzeanu@linux.microsoft.com>) id 1wHiqB-0005kH-Qm\n for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:09 -0400", "from laptop.localdomain (unknown [86.121.140.248])\n by linux.microsoft.com (Postfix) with ESMTPSA id AEE8420B716C;\n Tue, 28 Apr 2026 06:51:05 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com AEE8420B716C", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1777384267;\n bh=WJ38DvPHOqPdr07vUC966sHLG/3L8q3zyQeBdhMkfd8=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=LYhAsljsNH8Fze7X7qLlONLrF6eA/2SZ4P1w+2pCowMkN91G60EYjKqvlTAXs3uDI\n J6bsxFO06fJsQkIpuA1xB6E5sgDXJEsbyNdTSSVneyc5CbSNDbOWIhQGc/lwUt7gXJ\n RDHDO1sUe9LR4faPcJc9BSfN2uFs5CJRKND3lGTs=", "From": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>", "Subject": "[PATCH 3/6] include/hw/hyperv: add hv_vp_register_page struct\n definition", "Date": "Tue, 28 Apr 2026 16:50:50 +0300", "Message-ID": "<20260428135053.251200-4-dblanzeanu@linux.microsoft.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260428135053.251200-1-dblanzeanu@linux.microsoft.com>", "References": "<20260428135053.251200-1-dblanzeanu@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-26", "X-Spam_score": "-2.7", "X-Spam_bar": "--", "X-Spam_report": "(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Tue, 28 Apr 2026 10:00:24 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Define the `hv_vp_register_page` structure that the linux kernel uses\nto allow access to vcpu registers.\n\nThis structure is going to be used in later patches to access vcpu\nregisters.\n\nSigned-off-by: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>\n---\n include/hw/hyperv/hvgdk_mini.h | 103 +++++++++++++++++++++++++++++++++\n 1 file changed, 103 insertions(+)", "diff": "diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex c3a8f33280..07e322865a 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -474,6 +474,109 @@ struct hv_input_assert_virtual_interrupt {\n uint16_t rsvd_z1;\n } QEMU_PACKED;\n \n+/* Flags for dirty mask of hv_vp_register_page */\n+enum hv_x64_register_class_type {\n+ HV_X64_REGISTER_CLASS_GENERAL = 0,\n+ HV_X64_REGISTER_CLASS_IP = 1,\n+ HV_X64_REGISTER_CLASS_XMM = 2,\n+ HV_X64_REGISTER_CLASS_SEGMENT = 3,\n+ HV_X64_REGISTER_CLASS_FLAGS = 4,\n+};\n+\n+#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7\n+\n+union hv_vp_register_page_interrupt_vectors {\n+ uint64_t as_uint64;\n+ struct {\n+ uint8_t vector_count;\n+ uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];\n+ };\n+};\n+\n+struct hv_vp_register_page {\n+ uint16_t version;\n+ uint8_t isvalid;\n+ uint8_t rsvdz;\n+ uint32_t dirty;\n+\n+ union {\n+ struct {\n+ /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */\n+ union {\n+ struct {\n+ uint64_t rax;\n+ uint64_t rcx;\n+ uint64_t rdx;\n+ uint64_t rbx;\n+ uint64_t rsp;\n+ uint64_t rbp;\n+ uint64_t rsi;\n+ uint64_t rdi;\n+ uint64_t r8;\n+ uint64_t r9;\n+ uint64_t r10;\n+ uint64_t r11;\n+ uint64_t r12;\n+ uint64_t r13;\n+ uint64_t r14;\n+ uint64_t r15;\n+ } QEMU_PACKED;\n+\n+ uint64_t gp_registers[16];\n+ };\n+ /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */\n+ uint64_t rip;\n+ /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */\n+ uint64_t rflags;\n+ } QEMU_PACKED;\n+\n+ uint64_t registers[18];\n+ };\n+ uint8_t reserved[8];\n+ /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */\n+ union {\n+ struct {\n+ struct hv_u128 xmm0;\n+ struct hv_u128 xmm1;\n+ struct hv_u128 xmm2;\n+ struct hv_u128 xmm3;\n+ struct hv_u128 xmm4;\n+ struct hv_u128 xmm5;\n+ } QEMU_PACKED;\n+\n+ struct hv_u128 xmm_registers[6];\n+ };\n+ /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */\n+ union {\n+ struct {\n+ struct hv_x64_segment_register es;\n+ struct hv_x64_segment_register cs;\n+ struct hv_x64_segment_register ss;\n+ struct hv_x64_segment_register ds;\n+ struct hv_x64_segment_register fs;\n+ struct hv_x64_segment_register gs;\n+ } QEMU_PACKED;\n+\n+ struct hv_x64_segment_register segment_registers[6];\n+ };\n+ /* Misc. control registers (cannot be set via this interface) */\n+ uint64_t cr0;\n+ uint64_t cr3;\n+ uint64_t cr4;\n+ uint64_t cr8;\n+ uint64_t efer;\n+ uint64_t dr7;\n+ union hv_x64_pending_interruption_register pending_interruption;\n+ union hv_x64_interrupt_state_register interrupt_state;\n+ uint64_t instruction_emulation_hints;\n+ uint64_t xfem;\n+\n+ uint8_t reserved1[0x100];\n+\n+ /* Interrupts injected as part of HvCallDispatchVp. */\n+ union hv_vp_register_page_interrupt_vectors interrupt_vectors;\n+} QEMU_PACKED;\n+\n /* /dev/mshv */\n #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_partition)\n #define MSHV_CREATE_VP _IOW(MSHV_IOCTL, 0x01, struct mshv_create_vp)\n", "prefixes": [ "3/6" ] }