[{"id":3683608,"web_url":"http://patchwork.ozlabs.org/comment/3683608/","msgid":"<9F805A9B-13C5-44AB-B3F8-862952C97599@unpredictable.fr>","list_archive_url":null,"date":"2026-04-28T17:44:25","subject":"Re: [PATCH 3/6] include/hw/hyperv: add hv_vp_register_page struct\n definition","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"content":"> On 28. Apr 2026, at 15:50, Doru Blânzeanu wrote:\n> \n> Define the `hv_vp_register_page` structure that the linux kernel uses\n> to allow access to vcpu registers.\n> \n> This structure is going to be used in later patches to access vcpu\n> registers.\n> \n> Signed-off-by: Doru Blânzeanu \nReviewed-by: Mohamed Mediouni \n\n> ---\n> include/hw/hyperv/hvgdk_mini.h | 103 +++++++++++++++++++++++++++++++++\n> 1 file changed, 103 insertions(+)\n> \n> diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\n> index c3a8f33280..07e322865a 100644\n> --- a/include/hw/hyperv/hvgdk_mini.h\n> +++ b/include/hw/hyperv/hvgdk_mini.h\n> @@ -474,6 +474,109 @@ struct hv_input_assert_virtual_interrupt {\n> uint16_t rsvd_z1;\n> } QEMU_PACKED;\n> \n> +/* Flags for dirty mask of hv_vp_register_page */\n> +enum hv_x64_register_class_type {\n> + HV_X64_REGISTER_CLASS_GENERAL = 0,\n> + HV_X64_REGISTER_CLASS_IP = 1,\n> + HV_X64_REGISTER_CLASS_XMM = 2,\n> + HV_X64_REGISTER_CLASS_SEGMENT = 3,\n> + HV_X64_REGISTER_CLASS_FLAGS = 4,\n> +};\n> +\n> +#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7\n> +\n> +union hv_vp_register_page_interrupt_vectors {\n> + uint64_t as_uint64;\n> + struct {\n> + uint8_t vector_count;\n> + uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];\n> + };\n> +};\n> +\n> +struct hv_vp_register_page {\n> + uint16_t version;\n> + uint8_t isvalid;\n> + uint8_t rsvdz;\n> + uint32_t dirty;\n> +\n> + union {\n> + struct {\n> + /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */\n> + union {\n> + struct {\n> + uint64_t rax;\n> + uint64_t rcx;\n> + uint64_t rdx;\n> + uint64_t rbx;\n> + uint64_t rsp;\n> + uint64_t rbp;\n> + uint64_t rsi;\n> + uint64_t rdi;\n> + uint64_t r8;\n> + uint64_t r9;\n> + uint64_t r10;\n> + uint64_t r11;\n> + uint64_t r12;\n> + uint64_t r13;\n> + uint64_t r14;\n> + uint64_t r15;\n> + } QEMU_PACKED;\n> +\n> + uint64_t gp_registers[16];\n> + };\n> + /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */\n> + uint64_t rip;\n> + /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */\n> + uint64_t rflags;\n> + } QEMU_PACKED;\n> +\n> + uint64_t registers[18];\n> + };\n> + uint8_t reserved[8];\n> + /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */\n> + union {\n> + struct {\n> + struct hv_u128 xmm0;\n> + struct hv_u128 xmm1;\n> + struct hv_u128 xmm2;\n> + struct hv_u128 xmm3;\n> + struct hv_u128 xmm4;\n> + struct hv_u128 xmm5;\n> + } QEMU_PACKED;\n> +\n> + struct hv_u128 xmm_registers[6];\n> + };\n> + /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */\n> + union {\n> + struct {\n> + struct hv_x64_segment_register es;\n> + struct hv_x64_segment_register cs;\n> + struct hv_x64_segment_register ss;\n> + struct hv_x64_segment_register ds;\n> + struct hv_x64_segment_register fs;\n> + struct hv_x64_segment_register gs;\n> + } QEMU_PACKED;\n> +\n> + struct hv_x64_segment_register segment_registers[6];\n> + };\n> + /* Misc. control registers (cannot be set via this interface) */\n> + uint64_t cr0;\n> + uint64_t cr3;\n> + uint64_t cr4;\n> + uint64_t cr8;\n> + uint64_t efer;\n> + uint64_t dr7;\n> + union hv_x64_pending_interruption_register pending_interruption;\n> + union hv_x64_interrupt_state_register interrupt_state;\n> + uint64_t instruction_emulation_hints;\n> + uint64_t xfem;\n> +\n> + uint8_t reserved1[0x100];\n> +\n> + /* Interrupts injected as part of HvCallDispatchVp. */\n> + union hv_vp_register_page_interrupt_vectors interrupt_vectors;\n> +} QEMU_PACKED;\n> +\n> /* /dev/mshv */\n> #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_partition)\n> #define MSHV_CREATE_VP _IOW(MSHV_IOCTL, 0x01, struct mshv_create_vp)\n> -- \n> 2.53.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=QzvEe3BV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.pv.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3683980,"web_url":"http://patchwork.ozlabs.org/comment/3683980/","msgid":"","list_archive_url":null,"date":"2026-04-29T10:28:41","subject":"Re: [PATCH 3/6] include/hw/hyperv: add hv_vp_register_page struct\n definition","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"content":"On Tue, Apr 28, 2026 at 04:50:50PM +0300, Doru Blânzeanu wrote:\n> Define the `hv_vp_register_page` structure that the linux kernel uses\n> to allow access to vcpu registers.\n> \n> This structure is going to be used in later patches to access vcpu\n> registers.\n> \n> Signed-off-by: Doru Blânzeanu \n> ---\n> include/hw/hyperv/hvgdk_mini.h | 103 +++++++++++++++++++++++++++++++++\n> 1 file changed, 103 insertions(+)\n> \n> diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\n\nIn the kernel and the mshv crates the definitions are in hvhdk.h. We\nprobably want to put it into the same header in QEMU to avoid confusion.\n\n> index c3a8f33280..07e322865a 100644\n> --- a/include/hw/hyperv/hvgdk_mini.h\n> +++ b/include/hw/hyperv/hvgdk_mini.h\n> @@ -474,6 +474,109 @@ struct hv_input_assert_virtual_interrupt {\n> uint16_t rsvd_z1;\n> } QEMU_PACKED;\n> \n> +/* Flags for dirty mask of hv_vp_register_page */\n> +enum hv_x64_register_class_type {\n> + HV_X64_REGISTER_CLASS_GENERAL = 0,\n> + HV_X64_REGISTER_CLASS_IP = 1,\n> + HV_X64_REGISTER_CLASS_XMM = 2,\n> + HV_X64_REGISTER_CLASS_SEGMENT = 3,\n> + HV_X64_REGISTER_CLASS_FLAGS = 4,\n> +};\n> +\n> +#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7\n> +\n> +union hv_vp_register_page_interrupt_vectors {\n> + uint64_t as_uint64;\n> + struct {\n> + uint8_t vector_count;\n> + uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];\n> + };\n> +};\n> +\n> +struct hv_vp_register_page {\n> + uint16_t version;\n> + uint8_t isvalid;\n> + uint8_t rsvdz;\n> + uint32_t dirty;\n> +\n> + union {\n> + struct {\n> + /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */\n> + union {\n> + struct {\n> + uint64_t rax;\n> + uint64_t rcx;\n> + uint64_t rdx;\n> + uint64_t rbx;\n> + uint64_t rsp;\n> + uint64_t rbp;\n> + uint64_t rsi;\n> + uint64_t rdi;\n> + uint64_t r8;\n> + uint64_t r9;\n> + uint64_t r10;\n> + uint64_t r11;\n> + uint64_t r12;\n> + uint64_t r13;\n> + uint64_t r14;\n> + uint64_t r15;\n> + } QEMU_PACKED;\n> +\n> + uint64_t gp_registers[16];\n> + };\n> + /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */\n> + uint64_t rip;\n> + /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */\n> + uint64_t rflags;\n> + } QEMU_PACKED;\n> +\n> + uint64_t registers[18];\n> + };\n> + uint8_t reserved[8];\n> + /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */\n> + union {\n> + struct {\n> + struct hv_u128 xmm0;\n> + struct hv_u128 xmm1;\n> + struct hv_u128 xmm2;\n> + struct hv_u128 xmm3;\n> + struct hv_u128 xmm4;\n> + struct hv_u128 xmm5;\n> + } QEMU_PACKED;\n> +\n> + struct hv_u128 xmm_registers[6];\n> + };\n> + /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */\n> + union {\n> + struct {\n> + struct hv_x64_segment_register es;\n> + struct hv_x64_segment_register cs;\n> + struct hv_x64_segment_register ss;\n> + struct hv_x64_segment_register ds;\n> + struct hv_x64_segment_register fs;\n> + struct hv_x64_segment_register gs;\n> + } QEMU_PACKED;\n> +\n> + struct hv_x64_segment_register segment_registers[6];\n> + };\n> + /* Misc. control registers (cannot be set via this interface) */\n> + uint64_t cr0;\n> + uint64_t cr3;\n> + uint64_t cr4;\n> + uint64_t cr8;\n> + uint64_t efer;\n> + uint64_t dr7;\n> + union hv_x64_pending_interruption_register pending_interruption;\n> + union hv_x64_interrupt_state_register interrupt_state;\n> + uint64_t instruction_emulation_hints;\n> + uint64_t xfem;\n> +\n> + uint8_t reserved1[0x100];\n> +\n> + /* Interrupts injected as part of HvCallDispatchVp. */\n> + union hv_vp_register_page_interrupt_vectors interrupt_vectors;\n> +} QEMU_PACKED;\n> +\n> /* /dev/mshv */\n> #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_partition)\n> #define MSHV_CREATE_VP _IOW(MSHV_IOCTL, 0x01, struct mshv_create_vp)\n> -- \n> 2.53.0","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=eXWkpYsj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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