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GET /api/1.1/patches/2229436/?format=api
{ "id": 2229436, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428-t_power_on_fux-v5-1-f1ef926a91ff@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428-t_power_on_fux-v5-1-f1ef926a91ff@oss.qualcomm.com>", "date": "2026-04-28T08:37:15", "name": "[v5,1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bee7dd99313a638a39f412f176d3c341f5b99091", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.1/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428-t_power_on_fux-v5-1-f1ef926a91ff@oss.qualcomm.com/mbox/", "series": [ { "id": 501799, "url": "http://patchwork.ozlabs.org/api/1.1/series/501799/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501799", "date": "2026-04-28T08:37:15", "name": "PCI: qcom: Program T_POWER_ON value for L1.2 exit timing", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/501799/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229436/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229436/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53313-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=CKdGFCWn;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=L7s174C/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260428-t_power_on_fux-v5-1-f1ef926a91ff@oss.qualcomm.com>", "References": "<20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com>", "In-Reply-To": "<20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>", "Cc": "linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,\n quic_vbadigan@quicinc.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,\n Shawn Lin <shawn.lin@rock-chips.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777365442; l=3731;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=XiLKTsze8J8AZJi/BMBbOlFuV680Mddl8yNvZzrLHJE=;\n b=g47OKo/9QXn3oxthv11scYA0upYKny9R5Bl2k1j632CT3/up21E5N8hSJv3ggEu56+2lyzWt4\n n21McJlZhbxBJrQSTW4DbelAKFikr5Q/T5elz49WhQrRghTr/GJjNow", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Authority-Analysis": "v=2.4 cv=KuJ9H2WN c=1 sm=1 tr=0 ts=69f071cc cx=c_pps\n a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22\n a=s8YR1HE3AAAA:8 a=EUspDBNiAAAA:8 a=j3416i00YO8nPnzCGbIA:9 a=QEXdDO2ut3YA:10\n a=324X-CrmTo6CU4MGRt3R:22 a=jGH_LyMDp9YhSvY-UuyI:22", "X-Proofpoint-GUID": "2vXPKKD208yTuxJSSM4LeV7ndqbgYgct", "X-Proofpoint-ORIG-GUID": "2vXPKKD208yTuxJSSM4LeV7ndqbgYgct", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI4MDA3OSBTYWx0ZWRfX5Gig5PIoIIt7\n vy7IhA5xDO8c0Dglugm7d8TM8mbiHyg2BkoAuvDfqUk/dpCqfbGT7gMbhyxTsytV62/p30Y2rHx\n gkuuDCf72h2BJWoFcKU7IQtjjJPDipfSWp68ZUuHAzx8mmXP2WfZZ6+4FL/zRZkCBWHEb7lc8Nu\n 4qcgqbByxDhWL8qX9aE9ev8Lht0DVEwET+6vYwwIzs778SDzze/oy3NG69rMQLdScBGNuxumpU4\n hEU5wFSyWVK72a3xqkxj22iF/quNWKJ/tP85/lYFfCsbrkMJUM+jFmuLWo7/D77qujR3zcOV3fh\n ruSYBMRhGQX2R3tNZSfgFdjZ/h4sDzNe/qM1twdzFZuWuW3bk8R+bbzaA1owbwtcy15tMjSZX1J\n QQYLQNkEJTNz1AcYUtYEXjL66nC9P08Nh0RIdwL5nI0JL88jPb3UFP9WFmTOssyGHSTLTHeMCnb\n 867Y6bE+9zRUW8gGduA==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_02,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 suspectscore=0 spamscore=0 clxscore=1015\n lowpriorityscore=0 phishscore=0 bulkscore=0 malwarescore=0 impostorscore=0\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604280079" }, "content": "Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON\nparameter into the T_POWER_ON Scale and T_POWER_ON Value fields.\n\nThis helper can be used by the controller drivers to change the\ndefault/wrong value of T_POWER_ON in L1ss capability register to\navoid incorrect calculation of LTR_L1.2_THRESHOLD value.\n\nThe helper converts a T_POWER_ON time specified in microseconds into\nthe appropriate scale/value encoding defined by the PCIe spec r7.0,\nsec 7.8.3.2. Values that exceed the maximum encodable range are clamped\nto the largest representable encoding.\n\nTested-by: Shawn Lin <shawn.lin@rock-chips.com>\nReviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/pci.h | 6 ++++++\n drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 46 insertions(+)", "diff": "diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 4a14f88e543a..c379befe1ebe 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -1110,6 +1110,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);\n void pcie_aspm_powersave_config_link(struct pci_dev *pdev);\n void pci_configure_ltr(struct pci_dev *pdev);\n void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);\n+void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);\n #else\n static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }\n static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }\n@@ -1118,6 +1119,11 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)\n static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }\n static inline void pci_configure_ltr(struct pci_dev *pdev) { }\n static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }\n+static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)\n+{\n+\t*scale = 0;\n+\t*value = 0;\n+}\n #endif\n \n #ifdef CONFIG_PCIE_ECRC\ndiff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c\nindex 925373b98dff..457d469b8d49 100644\n--- a/drivers/pci/pcie/aspm.c\n+++ b/drivers/pci/pcie/aspm.c\n@@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)\n \treturn 0;\n }\n \n+/**\n+ * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields\n+ * @t_power_on_us: T_POWER_ON time in microseconds\n+ * @scale: Encoded T_POWER_ON Scale (0..2)\n+ * @value: Encoded T_POWER_ON Value\n+ *\n+ * T_POWER_ON is encoded as:\n+ * T_POWER_ON(us) = scale_unit(us) * value\n+ *\n+ * where scale_unit is selected by @scale:\n+ * 0: 2us\n+ * 1: 10us\n+ * 2: 100us\n+ *\n+ * If @t_power_on_us exceeds the maximum representable value, the result\n+ * is clamped to the largest encodable T_POWER_ON.\n+ *\n+ * See PCIe r7.0, sec 7.8.3.2.\n+ */\n+void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)\n+{\n+\tu8 maxv = FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE);\n+\n+\t/* T_POWER_ON_Value (\"value\") is a 5-bit field with max value of 31. */\n+\tif (t_power_on_us <= 2 * maxv) {\n+\t\t*scale = 0; /* Value times 2us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 2);\n+\t} else if (t_power_on_us <= 10 * maxv) {\n+\t\t*scale = 1; /* Value times 10us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 10);\n+\t} else if (t_power_on_us <= 100 * maxv) {\n+\t\t*scale = 2; /* value times 100us */\n+\t\t*value = DIV_ROUND_UP(t_power_on_us, 100);\n+\t} else {\n+\t\t*scale = 2;\n+\t\t*value = maxv;\n+\t}\n+}\n+EXPORT_SYMBOL(pcie_encode_t_power_on);\n+\n /*\n * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1\n * register. Ports enter L1.2 when the most recent LTR value is greater\n", "prefixes": [ "v5", "1/3" ] }