[{"id":3683332,"web_url":"http://patchwork.ozlabs.org/comment/3683332/","msgid":"","list_archive_url":null,"date":"2026-04-28T09:27:49","subject":"Re: [PATCH v5 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON\n fields","submitter":{"id":83553,"url":"http://patchwork.ozlabs.org/api/people/83553/","name":"Ilpo Järvinen","email":"ilpo.jarvinen@linux.intel.com"},"content":"On Tue, 28 Apr 2026, Krishna Chaitanya Chundru wrote:\n\n> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON\n> parameter into the T_POWER_ON Scale and T_POWER_ON Value fields.\n> \n> This helper can be used by the controller drivers to change the\n> default/wrong value of T_POWER_ON in L1ss capability register to\n> avoid incorrect calculation of LTR_L1.2_THRESHOLD value.\n> \n> The helper converts a T_POWER_ON time specified in microseconds into\n> the appropriate scale/value encoding defined by the PCIe spec r7.0,\n> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped\n> to the largest representable encoding.\n> \n> Tested-by: Shawn Lin \n> Reviewed-by: Shawn Lin \n> Signed-off-by: Krishna Chaitanya Chundru \n> ---\n> drivers/pci/pci.h | 6 ++++++\n> drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++\n> 2 files changed, 46 insertions(+)\n> \n> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\n> index 4a14f88e543a..c379befe1ebe 100644\n> --- a/drivers/pci/pci.h\n> +++ b/drivers/pci/pci.h\n> @@ -1110,6 +1110,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);\n> void pcie_aspm_powersave_config_link(struct pci_dev *pdev);\n> void pci_configure_ltr(struct pci_dev *pdev);\n> void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);\n> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);\n> #else\n> static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }\n> static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }\n> @@ -1118,6 +1119,11 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)\n> static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }\n> static inline void pci_configure_ltr(struct pci_dev *pdev) { }\n> static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }\n> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)\n> +{\n> +\t*scale = 0;\n> +\t*value = 0;\n> +}\n> #endif\n> \n> #ifdef CONFIG_PCIE_ECRC\n> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c\n> index 925373b98dff..457d469b8d49 100644\n> --- a/drivers/pci/pcie/aspm.c\n> +++ b/drivers/pci/pcie/aspm.c\n> @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)\n> \treturn 0;\n> }\n> \n> +/**\n> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields\n> + * @t_power_on_us: T_POWER_ON time in microseconds\n> + * @scale: Encoded T_POWER_ON Scale (0..2)\n> + * @value: Encoded T_POWER_ON Value\n> + *\n> + * T_POWER_ON is encoded as:\n> + * T_POWER_ON(us) = scale_unit(us) * value\n> + *\n> + * where scale_unit is selected by @scale:\n> + * 0: 2us\n> + * 1: 10us\n> + * 2: 100us\n> + *\n> + * If @t_power_on_us exceeds the maximum representable value, the result\n> + * is clamped to the largest encodable T_POWER_ON.\n> + *\n> + * See PCIe r7.0, sec 7.8.3.2.\n> + */\n> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)\n\nHi,\n\nI don't know how the type for t_power_on_us was picked but if it was \narbitrary decision, I suggest you just go with 32-bit input.\n\nThat would also remove the u32 -> u16 truncate done in the other patches \nof your series which would potentially corrupt the number (I assume \nnumbers that big would be invalid but they could alias to small u16 \nnumbers).\n\nReviewed-by: Ilpo Järvinen \n\n> +{\n> +\tu8 maxv = FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE);\n> +\n> +\t/* T_POWER_ON_Value (\"value\") is a 5-bit field with max value of 31. */\n> +\tif (t_power_on_us <= 2 * maxv) {\n> +\t\t*scale = 0; /* Value times 2us */\n> +\t\t*value = DIV_ROUND_UP(t_power_on_us, 2);\n> +\t} else if (t_power_on_us <= 10 * maxv) {\n> +\t\t*scale = 1; /* Value times 10us */\n> +\t\t*value = DIV_ROUND_UP(t_power_on_us, 10);\n> +\t} else if (t_power_on_us <= 100 * maxv) {\n> +\t\t*scale = 2; /* value times 100us */\n> +\t\t*value = DIV_ROUND_UP(t_power_on_us, 100);\n> +\t} else {\n> +\t\t*scale = 2;\n> +\t\t*value = maxv;\n> +\t}\n> +}\n> +EXPORT_SYMBOL(pcie_encode_t_power_on);\n> +\n> /*\n> * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1\n> * register. Ports enter L1.2 when the most recent LTR value is greater\n> \n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=dH+hDT/3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53319-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"dH+hDT/3\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.21","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4bYv3dTnz1yHX\n\tfor ; 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