Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2229371/?format=api
{ "id": 2229371, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229371/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428075030.1626440-2-hongxing.zhu@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428075030.1626440-2-hongxing.zhu@nxp.com>", "date": "2026-04-28T07:50:28", "name": "[v2,1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1534c766b4e9257b93511f0039378f1191500a88", "submitter": { "id": 68324, "url": "http://patchwork.ozlabs.org/api/1.1/people/68324/?format=api", "name": "Richard Zhu", "email": "hongxing.zhu@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428075030.1626440-2-hongxing.zhu@nxp.com/mbox/", "series": [ { "id": 501780, "url": "http://patchwork.ozlabs.org/api/1.1/series/501780/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501780", "date": "2026-04-28T07:50:29", "name": "Add root port reset to support link recovery", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501780/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229371/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229371/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53308-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=faACGMNZpizyjWFztosPz21RGF5jipmknDkqw00NaiU=;\n b=T53qDN0ZQCQjK6CzIkR8tAMShzA2FUWcWkr7mqTHugve8oZV0RpfzJXzx6N0JNsJ/eLM5wiIJ3x9UEb5kMu8Cqd9Qc7E1yz+qeo3DkpxbuEz5jQAuR1wR3scOOwNBP4d4RNFYiVD5DR9BdRQIi7+H/PEuasATytrUfAHkodMppfepA5w5T66TY49THJQ6AiW2J2TZ+kTJnthuptKsoHIrfyMCjg3D9bOOWTtr6aHRwZrDrHNF2DaLNjArpiANlu++CPKhVkAMe/xpA8MuWNnHPu3LM8i6x5OccKHGfzCQ19qkFYkMK4kPfXdd3etpuhaQPiXL2QAvAQ+bjyOwjS7MQ==", "From": "Richard Zhu <hongxing.zhu@nxp.com>", "To": "robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tbhelgaas@google.com,\n\tfrank.li@nxp.com,\n\tl.stach@pengutronix.de,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com", "Cc": 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"X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 947c1c08-093b-498e-ab3a-08dea4faab76", "X-MS-Exchange-CrossTenant-AuthSource": "AM0PR04MB5220.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Apr 2026 07:49:26.0469\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n /Fi8mM1knlBpdTQk9ik2qkshr2Ozxlzd+/YU378o0/xxEh7btssBh9zayL2CG2HulqZrmL1Q6BlUHb/uN8YaAA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AMBPR04MB11720" }, "content": "Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe\nbinding to support PCIe event-based interrupts for general controller\nevents, Advanced Error Reporting, and Power Management Events\nrespectively.\n\nThese interrupts are optional for most variants but required for\nfsl,imx95-pcie, which must specify all 5 interrupts (msi, dma, intr,\naer, pme).\n\nSigned-off-by: Richard Zhu <hongxing.zhu@nxp.com>\n---\n .../bindings/pci/fsl,imx6q-pcie.yaml | 21 +++++++++++++++++++\n 1 file changed, 21 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\nindex 9d1349855b422..0913c3312ed26 100644\n--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n@@ -58,12 +58,18 @@ properties:\n items:\n - description: builtin MSI controller.\n - description: builtin DMA controller.\n+ - description: PCIe event interrupt.\n+ - description: builtin AER SPI standalone interrupter line.\n+ - description: builtin PME SPI standalone interrupter line.\n \n interrupt-names:\n minItems: 1\n items:\n - const: msi\n - const: dma\n+ - const: intr\n+ - const: aer\n+ - const: pme\n \n reset-gpio:\n description: Should specify the GPIO for controlling the PCI bus device\n@@ -231,6 +237,21 @@ allOf:\n - const: ref\n - const: extref # Optional\n \n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - fsl,imx95-pcie\n+ then:\n+ properties:\n+ interrupts:\n+ minItems: 5\n+ maxItems: 5\n+ interrupt-names:\n+ minItems: 5\n+ maxItems: 5\n+\n unevaluatedProperties: false\n \n examples:\n", "prefixes": [ "v2", "1/3" ] }