[{"id":3683218,"web_url":"http://patchwork.ozlabs.org/comment/3683218/","msgid":"","list_archive_url":null,"date":"2026-04-28T07:56:02","subject":"RE: [PATCH v2 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and\n pme interrupts","submitter":{"id":68324,"url":"http://patchwork.ozlabs.org/api/people/68324/","name":"Richard Zhu","email":"hongxing.zhu@nxp.com"},"content":"Hi Frank:\nI didn't include your \"Reviewed-by: Frank Li Frank.Li@nxp.com\" tag in the v2\npatch-set because there were some changes made in v2. If you don't mind, I\nwould add your reviewed-by tag in the next version (v3) if you don't have\nsuggestions on the changes.\n\nBest Regards\nRichard Zhu\n\n> -----Original Message-----\n> From: Hongxing Zhu \n> Sent: Tuesday, April 28, 2026 3:50 PM\n> To: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;\n> bhelgaas@google.com; Frank Li ; l.stach@pengutronix.de;\n> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;\n> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com\n> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\n> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org;\n> Hongxing Zhu \n> Subject: [PATCH v2 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme\n> interrupts\n> \n> Add 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q PCIe binding to support\n> PCIe event-based interrupts for general controller events, Advanced Error\n> Reporting, and Power Management Events respectively.\n> \n> These interrupts are optional for most variants but required for fsl,imx95-pcie,\n> which must specify all 5 interrupts (msi, dma, intr, aer, pme).\n> \n> Signed-off-by: Richard Zhu \n> ---\n> .../bindings/pci/fsl,imx6q-pcie.yaml | 21 +++++++++++++++++++\n> 1 file changed, 21 insertions(+)\n> \n> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n> index 9d1349855b422..0913c3312ed26 100644\n> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n> @@ -58,12 +58,18 @@ properties:\n> items:\n> - description: builtin MSI controller.\n> - description: builtin DMA controller.\n> + - description: PCIe event interrupt.\n> + - description: builtin AER SPI standalone interrupter line.\n> + - description: builtin PME SPI standalone interrupter line.\n> \n> interrupt-names:\n> minItems: 1\n> items:\n> - const: msi\n> - const: dma\n> + - const: intr\n> + - const: aer\n> + - const: pme\n> \n> reset-gpio:\n> description: Should specify the GPIO for controlling the PCI bus device @@ -\n> 231,6 +237,21 @@ allOf:\n> - const: ref\n> - const: extref # Optional\n> \n> + - if:\n> + properties:\n> + compatible:\n> + contains:\n> + enum:\n> + - fsl,imx95-pcie\n> + then:\n> + properties:\n> + interrupts:\n> + minItems: 5\n> + maxItems: 5\n> + interrupt-names:\n> + minItems: 5\n> + maxItems: 5\n> +\n> unevaluatedProperties: false\n> \n> examples:\n> --\n> 2.37.1","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=RGtVqFe7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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