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GET /api/1.1/patches/2229288/?format=api
{ "id": 2229288, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229288/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-2-alif.zakuan.yuslaimi@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428033230.7777-2-alif.zakuan.yuslaimi@altera.com>", "date": "2026-04-28T03:32:28", "name": "[v2,1/3] arm: socfpga: Consolidate dram_bank_mmu_setup()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b2762e4263882ace5c330e9cdf748626b8a6a052", "submitter": { "id": 90458, "url": "http://patchwork.ozlabs.org/api/1.1/people/90458/?format=api", "name": "YUSLAIMI, ALIF ZAKUAN", "email": "alif.zakuan.yuslaimi@altera.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428033230.7777-2-alif.zakuan.yuslaimi@altera.com/mbox/", "series": [ { "id": 501756, "url": "http://patchwork.ozlabs.org/api/1.1/series/501756/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501756", "date": "2026-04-28T03:32:27", "name": "SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501756/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229288/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229288/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 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"X-OriginatorOrg": "altera.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e37b384d-f587-48c5-47c8-08dea4d6cb00", "X-MS-Exchange-CrossTenant-AuthSource": "PH7PR03MB7063.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Apr 2026 03:32:37.0950 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fbd72e03-d4a5-4110-adce-614d51f2077a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n /C46oJvO4ZEmyI04xgixSoc9eZGa6YC/JEMa9uv89Z+lXCHEeflNTrR0ZQTo4qVl9kWfuax9f97DhJkOrZQS9Vo5vLVRK3AQAwfxO0R4O+o=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR03MB5996", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n\nRelocate the dram_bank_mmu_setup() implementation from misc_arria10.c to\nthe common socfpga misc.c and update the function to correctly handle both\npre-relocation and post-relocation cases for DRAM cache enabling for\nconsistent MMU/dcache setup across Arria10 and CycloneV platforms.\n\nThese changes help to improve maintainability and consistency of DRAM\ninitialization as well as MMU configuration for Arria10 and CycloneV\nplatforms.\n\nNew Kconfig is introduced to enable this implementation only on the default\nArria10 and CycloneV boards as this will increase the SPL size which\nwill exceed some Gen5 devices' SPL size limit.\n\nFixes: e26ecebc684b (\"socfpga: arria10: Allow dcache_enable before relocation\")\n\nSigned-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n---\n arch/arm/mach-socfpga/Kconfig | 1 +\n arch/arm/mach-socfpga/misc.c | 31 ++++++++++++++++++++++++++++\n arch/arm/mach-socfpga/misc_arria10.c | 26 -----------------------\n 3 files changed, 32 insertions(+), 26 deletions(-)", "diff": "diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex fb98b647442..e2fdd6bb30f 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -115,6 +115,7 @@ config ARCH_SOCFPGA_CYCLONE5\n config ARCH_SOCFPGA_GEN5\n \tbool\n \tselect SPL_ALTERA_SDRAM\n+\tselect SPL_CACHE if SPL\n \timply FPGA_SOCFPGA\n \timply SPL_SIZE_LIMIT_SUBTRACT_GD\n \timply SPL_SIZE_LIMIT_SUBTRACT_MALLOC\ndiff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c\nindex 1eef7893e54..80b054dcae9 100644\n--- a/arch/arm/mach-socfpga/misc.c\n+++ b/arch/arm/mach-socfpga/misc.c\n@@ -318,3 +318,34 @@ phys_addr_t socfpga_get_clkmgr_addr(void)\n {\n \treturn socfpga_clkmgr_base;\n }\n+\n+#if IS_ENABLED(CONFIG_SYS_ARM_CACHE_CP15)\n+void dram_bank_mmu_setup(int bank)\n+{\n+\tstruct bd_info *bd = gd->bd;\n+\tu32 start, size;\n+\tint i;\n+\n+\t/* If we're still in OCRAM, don't set the XN bit on it */\n+\tif (!(gd->flags & GD_FLG_RELOC)) {\n+\t\tset_section_dcache(CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,\n+\t\t\t\t DCACHE_WRITETHROUGH);\n+\n+\t\t/*\n+\t\t * The default implementation of this function allows the DRAM dcache\n+\t\t * to be enabled only after relocation. However, to speed up ECC\n+\t\t * initialization, we want to be able to enable DRAM dcache before\n+\t\t * relocation.\n+\t\t */\n+\t\tstart = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n+\t\tsize = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n+\t\tfor (i = start; i < start + size; i++)\n+\t\t\tset_section_dcache(i, DCACHE_WRITETHROUGH);\n+\t} else {\n+\t\tstart = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n+\t\tsize = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n+\t\tfor (i = start; i < start + size; i++)\n+\t\t\tset_section_dcache(i, DCACHE_DEFAULT_OPTION);\n+\t}\n+}\n+#endif\ndiff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c\nindex 7e0f3875b7c..635fc3568fb 100644\n--- a/arch/arm/mach-socfpga/misc_arria10.c\n+++ b/arch/arm/mach-socfpga/misc_arria10.c\n@@ -243,29 +243,3 @@ int qspi_flash_software_reset(void)\n \treturn 0;\n }\n #endif\n-\n-void dram_bank_mmu_setup(int bank)\n-{\n-\tstruct bd_info *bd = gd->bd;\n-\tu32 start, size;\n-\tint i;\n-\n-\t/* If we're still in OCRAM, don't set the XN bit on it */\n-\tif (!(gd->flags & GD_FLG_RELOC)) {\n-\t\tset_section_dcache(\n-\t\t\tCFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,\n-\t\t\tDCACHE_WRITETHROUGH);\n-\t}\n-\n-\t/*\n-\t * The default implementation of this function allows the DRAM dcache\n-\t * to be enabled only after relocation. However, to speed up ECC\n-\t * initialization, we want to be able to enable DRAM dcache before\n-\t * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram\n-\t * is set first).\n-\t */\n-\tstart = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n-\tsize = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n-\tfor (i = start; i < start + size; i++)\n-\t\tset_section_dcache(i, DCACHE_DEFAULT_OPTION);\n-}\n", "prefixes": [ "v2", "1/3" ] }