Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2228911/?format=api
{ "id": 2228911, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427134231.531222-5-pshete@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260427134231.531222-5-pshete@nvidia.com>", "date": "2026-04-27T13:42:29", "name": "[v3,4/6] dt-bindings: pinctrl: Document Tegra264 pin controllers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0ccab4b701304ec7d63679461280127a6457624d", "submitter": { "id": 82424, "url": "http://patchwork.ozlabs.org/api/1.1/people/82424/?format=api", "name": "Prathamesh Shete", "email": "pshete@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427134231.531222-5-pshete@nvidia.com/mbox/", "series": [ { "id": 501650, "url": "http://patchwork.ozlabs.org/api/1.1/series/501650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501650", "date": "2026-04-27T13:42:25", "name": "Add Tegra238 and Tegra264 pinctrl support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228911/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228911/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14008-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Hseq+ZAh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14008-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"Hseq+ZAh\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.209.4", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g44ZV2MjRz1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 23:45:22 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 9FACD30387AD\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 13:43:43 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 6DE833CD8A1;\n\tMon, 27 Apr 2026 13:43:43 +0000 (UTC)", "from PH8PR06CU001.outbound.protection.outlook.com\n (mail-westus3azon11012004.outbound.protection.outlook.com [40.107.209.4])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C4263CCFD9;\n\tMon, 27 Apr 2026 13:43:41 +0000 (UTC)", "from BY3PR03CA0024.namprd03.prod.outlook.com (2603:10b6:a03:39a::29)\n by SA0PR12MB4462.namprd12.prod.outlook.com (2603:10b6:806:95::22) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.26; Mon, 27 Apr\n 2026 13:43:30 +0000", "from SJ1PEPF000023D1.namprd02.prod.outlook.com\n (2603:10b6:a03:39a:cafe::18) by BY3PR03CA0024.outlook.office365.com\n (2603:10b6:a03:39a::29) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.26 via Frontend Transport; Mon,\n 27 Apr 2026 13:43:30 +0000", "from mail.nvidia.com (216.228.117.160) by\n SJ1PEPF000023D1.mail.protection.outlook.com (10.167.244.7) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Mon, 27 Apr 2026 13:43:30 +0000", "from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 27 Apr\n 2026 06:43:14 -0700", "from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com\n (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 27 Apr\n 2026 06:43:13 -0700", "from build-pshete-noble-20260401.internal (10.127.8.11) by\n mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.2562.20 via\n Frontend Transport; Mon, 27 Apr 2026 06:43:09 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777297423; cv=fail;\n b=f+4ONEqIX3/MoQk9Cb4M6FHTyqXoXQuz50Cti6mwkc+YAmHybJR5ChGw8hYqicHxUPnE6PJbsF33izcuaKxX0Woz+v6gjga5aQ/SJwV9SIAiD+I1MBOCbIiAwiOjrjENi/MMzEnm8MMq1Tdp6rz9GTy6km1udo7d9zZGDHJm6qo=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=wOhY9CSMArjTG2imW5nM317Ohfu6J/RMmp8XqbSGleRkrEdSz5kYg8Ibu3fpzmtuQCTagVIx/mdhkvTSLYFSv3Xbca0+k7qy3KeQtwHGCMeyi1Wz2m1yyLBkC981b2bBFm9+O0+AFSHANaQr36FaJw9yAEAD26KAy+wWM6j9gbkTIFIbqwGnsJXJqhqWRDHeMe8ZIwoVO7lTr6i93rFXA2YdnABhYZ5eOLBifP+kDziXHE2XNE5rF46qDLgJTOxsxBAuoo8Vp28RceN0yxmSh7NQvERMWBhahtfq9E4YSnTC++LcCYO7i2aqgKCNC26J8DHD+PgZZ0NQm67vk0CbvA==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777297423; c=relaxed/simple;\n\tbh=EoJG6G1gZFxzsGMmh6REr9yS7X5nU/zMXpN3a7f1aCs=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=nteOko0N5OS6xwE1O0Jb/hHW7/y7tq08TFRlpTyemCZYiSw8TCeIdVv0eKK7HUZpFGqJNOffZjTVRPXprOqDWRczu10P3D5IMm6A40Rdzx7QAdIAqUuCxVkxYU6NbvM90ASkZQsmTF4G+vNmnkK8d/CwjS1ga2ZIAAs0uqs0Mws=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=vwO5PlIHOsLkcoXVOQin0O4yMq+6KW+XAMFQkGgp5Do=;\n b=SK56o11suk/rfrgzGGD9WQSsDlHo93n7Wz55ndAX/IQlaPPe/RxZlaWuC9f735+nX7Fkoaw6Ot8syP2+D4e0KajBYgfAR3f6oTchxH2SZ2Zh3wc7etgDmXDoBejQLcsRoDdNZ85Zgr0zYYGt3iPxRp3MAuEmUgLzDrZpxS7T6oJHRSMhuYkilLXXZwepRSqS8eFsvtuzrmLv8fvRX99GbSldB734w9Xu6356d6kHlgAylQXKD3W55wRKipCzWbY3tRHv3t0gNaypObY8Kq9ZJ8cbKXzmmvRlCMK1Sg5JUew2YWy2+kGByh8KcRsvvE4MmNmiyt7FslVgwGK7EEJniw==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=Hseq+ZAh; arc=fail smtp.client-ip=40.107.209.4", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=vwO5PlIHOsLkcoXVOQin0O4yMq+6KW+XAMFQkGgp5Do=;\n b=Hseq+ZAhwwyl5iF/RTj0itxlYIk5QRe3Mb37fzLOghMdWBIt752h+qLWF4U/vwYsWL8MjlbwQTlMWeFPD01ZDrCZ1t7Xj/C4vqDZ8UybQOvqBP4tC8vA4G93OLYr8xkikiXlIWSEIc2B6akMVuixDvHcIxIyAR+TsYegS+NmLm3VO1iKf5LBVnVcy1ZMcutBy2yNzwCSy7TLD6QN3nkOaADD6Tgr8tVM1+KOwKifXWWAfb5WlVQgAu/ZvCk63jgf0heYovU+KhrTdUlY5BPLmOoPAvB0DkkwhwaZNwKW3NfT7N3Nzuj2npM+6jKSvYMwA99O4xdIuy6hCeifDWOphw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "<pshete@nvidia.com>", "To": "<linusw@kernel.org>, <thierry.reding@kernel.org>, <pshete@nvidia.com>,\n\t<jonathanh@nvidia.com>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>", "CC": "<webgeek1234@gmail.com>, <rosenp@gmail.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-gpio@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Krzysztof\n Kozlowski\" <krzysztof.kozlowski@oss.qualcomm.com>", "Subject": "[PATCH v3 4/6] dt-bindings: pinctrl: Document Tegra264 pin\n controllers", "Date": "Mon, 27 Apr 2026 13:42:29 +0000", "Message-ID": "<20260427134231.531222-5-pshete@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260427134231.531222-1-pshete@nvidia.com>", "References": "<20260427134231.531222-1-pshete@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ1PEPF000023D1:EE_|SA0PR12MB4462:EE_", "X-MS-Office365-Filtering-Correlation-Id": "82bbaa7a-d2ac-46ec-dea5-08dea462f80f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|376014|36860700016|7416014|1800799024|56012099003|18002099003|22082099003|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n\tdGBhlTXSlGdz2VZldNs0EoAygECdZZ5v1vDIWJNarzjLEvNTDSNAZwKQxiwADLX2k6oSC+DZhH1mkj386swy5qksjmv2khwHcqpHdEEihECjZ9yhbepiCJpExvjZIBwl8sWnE6K1cVzY8MsVmOLL/k5m1WlHaE/aw5Nfu4isQfXfU5avlBkpyWlLlCV0Enz4DTmvzUGizfwMb2e6kslsmfNhzimIHddryy8R/1jKixef3E23TrBdUv23MZipk1XdJWH0P8jxbroqUiu8ho6ZrTBAaDPVtOV9J4ux5MX9caFWgpldueqBzEc6epuqtWm4WKKZnNCV6kCL6s9cSRFY213pj3dfZn0N+iVp7zFF49Ak59Vz6JhBVOuMMRHq9sQXCmjK6cl7U5Boxq5MnayGdAk7m/FpQmcFbgx69A/in2HUJJ95OxeBMozAdGZiLveHm1BZHlT9Mq9IY0J3uJ1YjihFW+dKbD/GiVvjT16bT/i7tCrFHPLCTjxKlPXPlApFZUGW65UoIgJgsrLZt2g9ZnK/YFEsTtnkq3LlWzLbXp0wSQDJEU5bj9zzFDFCsCreRNpwsM6LlzLMF2+Pb9Nv1/Q0dYlHQ7tvtYrJRAaR7XaRGMaIsD181ALc0IfSJWMIMiUCXvez0sMDV57j4SnmquszafLhp5kCe4jEMWhZSWs1gANiXj8sPZcO4NxinF79tiNKQU89tj4ubocElGibYCkA4BLEWIeKdj1TJ8V3J8dvwwBhRPr4R0TvbMy0UCEz4TOiZka8vvEYE/RWObfQGA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(7416014)(1800799024)(56012099003)(18002099003)(22082099003)(13003099007);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tb4aHpOAFdA3K5TCLfva8yV68KY47gmyREVxGIUe1QH4JwdiT3ek375jeflrbTBIYyAJiwRWyRMyWJ60JhjuOrwZqEol8dZ/ux26nm5MTHYolcXrS48v/1KO+/na2hKNY9xGzvoAzOVGyfaJRvuZSQtyx92IHlTMhAj4YIwu35QNY8HQFtBIYrQZw/GtQcgHxW9mkUInmwuHFztqOFHo/MuQlNH899uhDoV2KUHtak2L06DmZEuooVmzOvltc6/8GQlS5coMEWKFouIr/CFPgNyXmnIw5DIuWYv9UITfxI04h0c6JSRtu8GIdGrJID66soEw66Ljv694Z4PI6HjNWs53zcxA9ISMfL/GG3vSxY2r16gfTlLo7bf0ckKjIpYgGpHFIC67gamRAuQ+Xujrb7aMKq9AHWWxFyB3gGltGMULrcXPjSqMiUpVq1J/gnhd+", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 13:43:30.7922\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 82bbaa7a-d2ac-46ec-dea5-08dea462f80f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D1.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4462" }, "content": "From: Prathamesh Shete <pshete@nvidia.com>\n\nTegra264 contains three pin controllers. Document their compatible strings\nand describe the list of pins and functions that they provide.\n\nSigned-off-by: Prathamesh Shete <pshete@nvidia.com>\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\nChanges in v3:\n - Wrap commit message to 75 chars per line (v2 was too short).\nChanges in v2:\n - Add a 'required:' block listing 'compatible' and 'reg'.\n - Switch top-level 'unevaluatedProperties: false' to\n 'additionalProperties: false'.\n---\n .../pinctrl/nvidia,tegra264-pinmux-aon.yaml | 80 +++++++++\n .../nvidia,tegra264-pinmux-common.yaml | 84 +++++++++\n .../pinctrl/nvidia,tegra264-pinmux-main.yaml | 167 ++++++++++++++++++\n .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml | 78 ++++++++\n 4 files changed, 409 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml\n create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml\nnew file mode 100644\nindex 000000000000..682e6510ed45\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml\n@@ -0,0 +1,80 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 AON Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra264-pinmux-aon\n+\n+ reg:\n+ maxItems: 1\n+\n+patternProperties:\n+ \"^pinmux(-[a-z0-9-]+)?$\":\n+ type: object\n+\n+ # pin groups\n+ additionalProperties:\n+ $ref: nvidia,tegra264-pinmux-common.yaml\n+\n+ properties:\n+ nvidia,pins:\n+ items:\n+ enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,\n+ batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,\n+ hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,\n+ soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,\n+ gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,\n+ uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,\n+ spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,\n+ soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,\n+ soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,\n+ soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,\n+ drive_ao_retention_n_paa2, drive_batt_oc_paa3,\n+ drive_power_on_paa5, drive_vcomp_alert_paa1,\n+ drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,\n+ drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,\n+ drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,\n+ drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,\n+ drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,\n+ drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,\n+ drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,\n+ drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,\n+ drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,\n+ drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,\n+ drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,\n+ drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,\n+ drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]\n+\n+required:\n+ - compatible\n+ - reg\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>\n+\n+ pinmux@c7a2000 {\n+ compatible = \"nvidia,tegra264-pinmux-aon\";\n+ reg = <0xc7a2000 0x2000>;\n+\n+ pinctrl-names = \"default\";\n+ pinctrl-0 = <&state_default>;\n+\n+ state_default: pinmux-default {\n+ uart0 {\n+ nvidia,pins = \"uart0_tx_pcc5\";\n+ nvidia,function = \"uarta_txd\";\n+ };\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml\nnew file mode 100644\nindex 000000000000..d644c496d8a5\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml\n@@ -0,0 +1,84 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 Pinmux Common Properties\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+$ref: nvidia,tegra-pinmux-common.yaml\n+\n+properties:\n+ nvidia,function:\n+ enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd,\n+ dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk,\n+ i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd,\n+ uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck,\n+ uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1,\n+ spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk,\n+ i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts,\n+ uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk,\n+ i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in,\n+ gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat,\n+ i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk,\n+ i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0,\n+ spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in,\n+ i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig,\n+ gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l,\n+ pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio,\n+ sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l,\n+ pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc,\n+ eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0,\n+ qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd,\n+ sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0,\n+ qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync,\n+ dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en,\n+ bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in,\n+ extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck,\n+ sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0,\n+ spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out,\n+ i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk,\n+ i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0,\n+ qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync,\n+ rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0,\n+ soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat,\n+ nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck,\n+ ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat,\n+ dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync,\n+ dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n,\n+ soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a,\n+ tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk,\n+ i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din,\n+ spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0,\n+ tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0,\n+ l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk,\n+ i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk,\n+ tsc_edge_out2 ]\n+\n+ # out of the common properties, only these are allowed for Tegra264\n+ nvidia,pins: true\n+ nvidia,pull: true\n+ nvidia,tristate: true\n+ nvidia,schmitt: true\n+ nvidia,enable-input: true\n+ nvidia,open-drain: true\n+ nvidia,lock: true\n+ nvidia,drive-type: true\n+ nvidia,io-hv: true\n+\n+required:\n+ - nvidia,pins\n+\n+# We would typically use unevaluatedProperties here but that has the\n+# downside that all the properties in the common bindings become valid\n+# for all chip generations. In this case, however, we want the per-SoC\n+# bindings to be able to override which of the common properties are\n+# allowed, since not all pinmux generations support the same sets of\n+# properties. This way, the common bindings define the format of the\n+# properties but the per-SoC bindings define which of them apply to a\n+# given chip.\n+additionalProperties: false\ndiff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml\nnew file mode 100644\nindex 000000000000..c40409d3263c\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml\n@@ -0,0 +1,167 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 Main Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra264-pinmux-main\n+\n+ reg:\n+ maxItems: 1\n+\n+patternProperties:\n+ \"^pinmux(-[a-z0-9-]+)?$\":\n+ type: object\n+\n+ # pin groups\n+ additionalProperties:\n+ $ref: nvidia,tegra264-pinmux-common.yaml\n+\n+ properties:\n+ nvidia,pins:\n+ items:\n+ enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4,\n+ ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1,\n+ soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4,\n+ dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0,\n+ gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3,\n+ gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1,\n+ sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4,\n+ sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0,\n+ soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3,\n+ soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6,\n+ soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2,\n+ uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5,\n+ soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2,\n+ soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,\n+ soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,\n+ pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,\n+ uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,\n+ dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3,\n+ gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6,\n+ pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1,\n+ dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5,\n+ dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1,\n+ spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5,\n+ soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0,\n+ soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4,\n+ dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7,\n+ soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0,\n+ qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4,\n+ qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0,\n+ soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3,\n+ soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6,\n+ soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1,\n+ xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4,\n+ soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7,\n+ soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2,\n+ cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2,\n+ uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5,\n+ spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1,\n+ spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5,\n+ uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1,\n+ spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4,\n+ extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7,\n+ drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1,\n+ drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4,\n+ drive_uart10_rx_ph3, drive_uart10_tx_ph2,\n+ drive_spi3_cs0_pj1, drive_spi3_cs3_pj2,\n+ drive_spi3_miso_ph7, drive_spi3_mosi_pj0,\n+ drive_spi3_sck_ph6, drive_uart5_cts_n_pj6,\n+ drive_uart5_rts_n_pj5, drive_uart5_rx_pj4,\n+ drive_uart5_tx_pj3, drive_spi1_cs0_pk2,\n+ drive_spi1_cs1_pk3, drive_spi1_miso_pk0,\n+ drive_spi1_mosi_pk1, drive_spi1_sck_pj7,\n+ drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4,\n+ drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7,\n+ drive_soc_gpio124_pl0, drive_soc_gpio125_pl1,\n+ drive_fan_tach0_pl2, drive_soc_gpio127_pl3,\n+ drive_soc_gpio128_pl4, drive_soc_gpio129_pl5,\n+ drive_soc_gpio130_pl6, drive_soc_gpio131_pl7,\n+ drive_gp_pwm9_pm0, drive_soc_gpio133_pm1,\n+ drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4,\n+ drive_uart9_rx_pm3, drive_uart9_tx_pm2,\n+ drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1,\n+ drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4,\n+ drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2,\n+ drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2,\n+ drive_qspi0_io1_pt3, drive_qspi0_io2_pt4,\n+ drive_qspi0_io3_pt5, drive_qspi0_sck_pt0,\n+ drive_soc_gpio192_pt6, drive_soc_gpio138_pp0,\n+ drive_soc_gpio139_pp1, drive_dap6_din_pp4,\n+ drive_dap6_dout_pp3, drive_dap6_fs_pp5,\n+ drive_dap6_sclk_pp2, drive_dap4_dout_pp7,\n+ drive_dap4_sclk_pp6, drive_dap4_din_pq0,\n+ drive_dap4_fs_pq1, drive_spi5_cs0_pq5,\n+ drive_spi5_miso_pq3, drive_spi5_mosi_pq4,\n+ drive_spi5_sck_pq2, drive_soc_gpio152_pq6,\n+ drive_soc_gpio153_pq7, drive_soc_gpio155_pr1,\n+ drive_aud_mclk_pr0, drive_dap1_sclk_pr2,\n+ drive_dap1_in_pr4, drive_dap1_out_pr3,\n+ drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6,\n+ drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0,\n+ drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4,\n+ drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2,\n+ drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1,\n+ drive_dap2_clk_pv6, drive_dap2_din_pv7,\n+ drive_dap2_dout_pw0, drive_pwm10_pv1,\n+ drive_soc_gpio170_pu0, drive_soc_gpio171_pu1,\n+ drive_soc_gpio172_pu2, drive_soc_gpio173_pu3,\n+ drive_soc_gpio174_pu4, drive_soc_gpio175_pu5,\n+ drive_soc_gpio176_pu6, drive_soc_gpio177_pu7,\n+ drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5,\n+ drive_uart4_rts_n_pv4, drive_uart4_rx_pv3,\n+ drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7,\n+ drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0,\n+ drive_soc_gpio251_pf1, drive_soc_gpio252_pf2,\n+ drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4,\n+ drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6,\n+ drive_pwm2_pf7, drive_pwm3_pg0,\n+ drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2,\n+ drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4,\n+ drive_soc_gpio270_py0, drive_soc_gpio271_py1,\n+ drive_soc_gpio272_py2, drive_soc_gpio273_py3,\n+ drive_soc_gpio274_py4, drive_soc_gpio275_py5,\n+ drive_soc_gpio276_py6, drive_soc_gpio277_py7,\n+ drive_soc_gpio278_pz0, drive_soc_gpio279_pz1,\n+ drive_soc_gpio282_pz4, drive_soc_gpio283_pz5,\n+ drive_soc_gpio284_pz6, drive_soc_gpio285_pz7,\n+ drive_soc_gpio286_pal0, drive_soc_gpio287_pal1,\n+ drive_soc_gpio288_pal2, drive_xhalt_trig_pz2,\n+ drive_soc_gpio281_pz3 ]\n+\n+required:\n+ - compatible\n+ - reg\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>\n+\n+ pinmux@c281000 {\n+ compatible = \"nvidia,tegra264-pinmux-main\";\n+ reg = <0xc281000 0xc000>;\n+\n+ pinctrl-names = \"default\";\n+ pinctrl-0 = <&state_default>;\n+\n+ state_default: pinmux-default {\n+ sdmmc1 {\n+ nvidia,pins = \"sdmmc1_clk_px0\";\n+ nvidia,function = \"sdmmc1_cd\";\n+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;\n+ nvidia,tristate = <TEGRA_PIN_DISABLE>;\n+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;\n+ };\n+ };\n+ };\ndiff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml\nnew file mode 100644\nindex 000000000000..9a54795d9cc5\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml\n@@ -0,0 +1,78 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 UPHY Pinmux Controller\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra264-pinmux-uphy\n+\n+ reg:\n+ maxItems: 1\n+\n+patternProperties:\n+ \"^pinmux(-[a-z0-9-]+)?$\":\n+ type: object\n+\n+ # pin groups\n+ additionalProperties:\n+ $ref: nvidia,tegra264-pinmux-common.yaml\n+\n+ properties:\n+ nvidia,pins:\n+ items:\n+ enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,\n+ pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,\n+ eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,\n+ eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,\n+ pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,\n+ pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,\n+ sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,\n+ soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,\n+ ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,\n+ drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,\n+ drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,\n+ drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,\n+ drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,\n+ drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,\n+ drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,\n+ drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,\n+ drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,\n+ drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,\n+ drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,\n+ drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,\n+ drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]\n+\n+required:\n+ - compatible\n+ - reg\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>\n+\n+ pinmux@82e0000 {\n+ compatible = \"nvidia,tegra264-pinmux-uphy\";\n+ reg = <0x82e0000 0x4000>;\n+\n+ pinctrl-names = \"default\";\n+ pinctrl-0 = <&pinmux_default>;\n+\n+ pinmux_default: pinmux-default {\n+ pex {\n+ nvidia,pins = \"pex_l1_rst_n_pb1\";\n+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;\n+ nvidia,tristate = <TEGRA_PIN_DISABLE>;\n+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;\n+ };\n+ };\n+ };\n", "prefixes": [ "v3", "4/6" ] }