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GET /api/1.1/patches/2228646/?format=api
{ "id": 2228646, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228646/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427073419.567360-2-amhetre@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260427073419.567360-2-amhetre@nvidia.com>", "date": "2026-04-27T07:34:18", "name": "[V2,1/2] dt-bindings: memory: tegra: Add nvidia,tegra238-mc compatible", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a6ffe62bb1b348db919c91abf9488786cbc7ba1e", "submitter": { "id": 75198, "url": "http://patchwork.ozlabs.org/api/1.1/people/75198/?format=api", "name": "Ashish Mhetre", "email": "amhetre@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427073419.567360-2-amhetre@nvidia.com/mbox/", "series": [ { "id": 501592, "url": "http://patchwork.ozlabs.org/api/1.1/series/501592/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501592", "date": "2026-04-27T07:34:19", "name": "memory: tegra: Add Tegra238 memory controller support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501592/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228646/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228646/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-13992-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com 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216.228.118.232 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C", "From": "Ashish Mhetre <amhetre@nvidia.com>", "To": "<krzk@kernel.org>, <robh@kernel.org>, <conor+dt@kernel.org>,\n\t<=thierry.reding@kernel.org>, <jonathanh@nvidia.com>, <sumitg@nvidia.com>", "CC": "<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Ashish Mhetre <amhetre@nvidia.com>", "Subject": "[PATCH V2 1/2] dt-bindings: memory: tegra: Add nvidia,tegra238-mc\n compatible", "Date": "Mon, 27 Apr 2026 07:34:18 +0000", "Message-ID": "<20260427073419.567360-2-amhetre@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260427073419.567360-1-amhetre@nvidia.com>", "References": "<20260427073419.567360-1-amhetre@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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"\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tOMrakO0cT8gUD0uWs/7oRS4tHdjqES9/gJLIoHGappgJN1LdA9q5zurBFB+trh1EL2F6p7RJt3ouAWgK/P0Xxxov7Wz9o9Dl/AJTfQkPXWO2IJc/E+30/Y0nLK28t8ZYNIj/Lk8drpUz9bSbGS5Q8iuxJP1ALf/oc8OTnH3WDeS2MGNe+2w0x8WEgTi1eyl9RA7BWMsXPv25wtNK8q9y5bBkeCQUMYlywIIP4WHrSgbr+0LMvmtSblwdDwMch9tykjGmQ3HBK+qWr9hxilypp1XceG9gXo4o2KTvN2EUmkOMwolpyCDy/rr6F144gPgjb1Vme9oqwZQN6h7VOXp4chwSL9iVJy8FoR6AlDNDn3v8jIIALkCVQZRRtvD6phYabPvdTAheMsRtWV28mGVlYV37nuxidB5HaOAtSWNwf+R1b5FJnp8tUNZWiTZvsYT4", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 07:34:35.6893\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a3a1ba8a-f088-4ca2-bbc1-08dea42f6e7b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D7.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4094" }, "content": "Document the device tree binding for the Tegra238 memory controller.\nTegra238 has 8 memory controller channels plus broadcast and stream-id\nregisters.\n\nAdd the stream ID header (nvidia,tegra238-mc.h) defining ISO and NISO\nstream IDs for SMMU configuration.\n\nSigned-off-by: Ashish Mhetre <amhetre@nvidia.com>\n---\n .../nvidia,tegra186-mc.yaml | 31 ++++++++\n .../dt-bindings/memory/nvidia,tegra238-mc.h | 74 +++++++++++++++++++\n 2 files changed, 105 insertions(+)\n create mode 100644 include/dt-bindings/memory/nvidia,tegra238-mc.h", "diff": "diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\nindex 7b03b589168b..6c374e2b1543 100644\n--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\n+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\n@@ -32,6 +32,7 @@ properties:\n - nvidia,tegra186-mc\n - nvidia,tegra194-mc\n - nvidia,tegra234-mc\n+ - nvidia,tegra238-mc\n - nvidia,tegra264-mc\n \n reg:\n@@ -266,6 +267,36 @@ allOf:\n \n interrupt-names: false\n \n+ - if:\n+ properties:\n+ compatible:\n+ const: nvidia,tegra238-mc\n+ then:\n+ properties:\n+ reg:\n+ minItems: 10\n+ maxItems: 10\n+ description: 9 memory controller channels and 1 for stream-id registers\n+\n+ reg-names:\n+ items:\n+ - const: sid\n+ - const: broadcast\n+ - const: ch0\n+ - const: ch1\n+ - const: ch2\n+ - const: ch3\n+ - const: ch4\n+ - const: ch5\n+ - const: ch6\n+ - const: ch7\n+\n+ interrupts:\n+ items:\n+ - description: MC general interrupt\n+\n+ interrupt-names: false\n+\n - if:\n properties:\n compatible:\ndiff --git a/include/dt-bindings/memory/nvidia,tegra238-mc.h b/include/dt-bindings/memory/nvidia,tegra238-mc.h\nnew file mode 100644\nindex 000000000000..be24c0eb3f15\n--- /dev/null\n+++ b/include/dt-bindings/memory/nvidia,tegra238-mc.h\n@@ -0,0 +1,74 @@\n+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */\n+\n+#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H\n+#define DT_BINDINGS_MEMORY_TEGRA238_MC_H\n+\n+/* special clients */\n+#define TEGRA238_SID_INVALID\t\t0x0\n+#define TEGRA238_SID_PASSTHROUGH\t0x7f\n+\n+/* ISO stream IDs */\n+#define TEGRA238_SID_ISO_NVDISPLAY\t0x1\n+#define TEGRA238_SID_ISO_APE0\t\t0x2\n+#define TEGRA238_SID_ISO_APE1\t\t0x3\n+\n+/* NISO stream IDs */\n+#define TEGRA238_SID_AON\t\t0x1\n+#define TEGRA238_SID_BPMP\t\t0x2\n+#define TEGRA238_SID_ETR\t\t0x3\n+#define TEGRA238_SID_FDE\t\t0x4\n+#define TEGRA238_SID_HC\t\t0x5\n+#define TEGRA238_SID_HDA\t\t0x6\n+#define TEGRA238_SID_NVDEC\t\t0x7\n+#define TEGRA238_SID_NVDISPLAY\t\t0x8\n+#define TEGRA238_SID_NVENC\t\t0x9\n+#define TEGRA238_SID_OFA\t\t0xa\n+#define TEGRA238_SID_PCIE0\t\t0xb\n+#define TEGRA238_SID_PCIE1\t\t0xc\n+#define TEGRA238_SID_PCIE2\t\t0xd\n+#define TEGRA238_SID_PCIE3\t\t0xe\n+#define TEGRA238_SID_HWMP_PMA\t\t0xf\n+#define TEGRA238_SID_PSC\t\t0x10\n+#define TEGRA238_SID_SDMMC1A\t\t0x11\n+#define TEGRA238_SID_SDMMC4A\t\t0x12\n+#define TEGRA238_SID_SES_SE0\t\t0x13\n+#define TEGRA238_SID_SES_SE1\t\t0x14\n+#define TEGRA238_SID_SES_SE2\t\t0x15\n+#define TEGRA238_SID_SEU1_SE0\t\t0x16\n+#define TEGRA238_SID_SEU1_SE1\t\t0x17\n+#define TEGRA238_SID_SEU1_SE2\t\t0x18\n+#define TEGRA238_SID_TSEC\t\t0x19\n+#define TEGRA238_SID_UFSHC\t\t0x1a\n+#define TEGRA238_SID_VIC\t\t0x1b\n+#define TEGRA238_SID_XUSB_HOST\t\t0x1c\n+#define TEGRA238_SID_XUSB_DEV\t\t0x1d\n+#define TEGRA238_SID_GPCDMA_0\t\t0x1e\n+#define TEGRA238_SID_SMMU_TEST\t\t0x1f\n+\n+/* Host1x virtualization clients. */\n+#define TEGRA238_SID_HOST1X_CTX0\t0x20\n+#define TEGRA238_SID_HOST1X_CTX1\t0x21\n+#define TEGRA238_SID_HOST1X_CTX2\t0x22\n+#define TEGRA238_SID_HOST1X_CTX3\t0x23\n+#define TEGRA238_SID_HOST1X_CTX4\t0x24\n+#define TEGRA238_SID_HOST1X_CTX5\t0x25\n+#define TEGRA238_SID_HOST1X_CTX6\t0x26\n+#define TEGRA238_SID_HOST1X_CTX7\t0x27\n+\n+#define TEGRA238_SID_XUSB_VF0\t\t0x28\n+#define TEGRA238_SID_XUSB_VF1\t\t0x29\n+#define TEGRA238_SID_XUSB_VF2\t\t0x2a\n+#define TEGRA238_SID_XUSB_VF3\t\t0x2b\n+\n+/* Host1x command buffers */\n+#define TEGRA238_SID_HC_VM0\t\t0x2c\n+#define TEGRA238_SID_HC_VM1\t\t0x2d\n+#define TEGRA238_SID_HC_VM2\t\t0x2e\n+#define TEGRA238_SID_HC_VM3\t\t0x2f\n+#define TEGRA238_SID_HC_VM4\t\t0x30\n+#define TEGRA238_SID_HC_VM5\t\t0x31\n+#define TEGRA238_SID_HC_VM6\t\t0x32\n+#define TEGRA238_SID_HC_VM7\t\t0x33\n+\n+#endif\n", "prefixes": [ "V2", "1/2" ] }