[{"id":3683952,"web_url":"http://patchwork.ozlabs.org/comment/3683952/","msgid":"<8e873293-0f56-4ec9-a469-ea5d0fddebd2@nvidia.com>","list_archive_url":null,"date":"2026-04-29T09:27:28","subject":"Re: [PATCH V2 1/2] dt-bindings: memory: tegra: Add nvidia,tegra238-mc\n compatible","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 27/04/2026 08:34, Ashish Mhetre wrote:\n> Document the device tree binding for the Tegra238 memory controller.\n> Tegra238 has 8 memory controller channels plus broadcast and stream-id\n> registers.\n> \n> Add the stream ID header (nvidia,tegra238-mc.h) defining ISO and NISO\n> stream IDs for SMMU configuration.\n> \n> Signed-off-by: Ashish Mhetre \n> ---\n> .../nvidia,tegra186-mc.yaml | 31 ++++++++\n> .../dt-bindings/memory/nvidia,tegra238-mc.h | 74 +++++++++++++++++++\n> 2 files changed, 105 insertions(+)\n> create mode 100644 include/dt-bindings/memory/nvidia,tegra238-mc.h\n> \n> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\n> index 7b03b589168b..6c374e2b1543 100644\n> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\n> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml\n> @@ -32,6 +32,7 @@ properties:\n> - nvidia,tegra186-mc\n> - nvidia,tegra194-mc\n> - nvidia,tegra234-mc\n> + - nvidia,tegra238-mc\n> - nvidia,tegra264-mc\n> \n> reg:\n> @@ -266,6 +267,36 @@ allOf:\n> \n> interrupt-names: false\n> \n> + - if:\n> + properties:\n> + compatible:\n> + const: nvidia,tegra238-mc\n> + then:\n> + properties:\n> + reg:\n> + minItems: 10\n> + maxItems: 10\n> + description: 9 memory controller channels and 1 for stream-id registers\n> +\n> + reg-names:\n> + items:\n> + - const: sid\n> + - const: broadcast\n> + - const: ch0\n> + - const: ch1\n> + - const: ch2\n> + - const: ch3\n> + - const: ch4\n> + - const: ch5\n> + - const: ch6\n> + - const: ch7\n> +\n> + interrupts:\n> + items:\n> + - description: MC general interrupt\n> +\n> + interrupt-names: false\n> +\n> - if:\n> properties:\n> compatible:\n> diff --git a/include/dt-bindings/memory/nvidia,tegra238-mc.h b/include/dt-bindings/memory/nvidia,tegra238-mc.h\n> new file mode 100644\n> index 000000000000..be24c0eb3f15\n> --- /dev/null\n> +++ b/include/dt-bindings/memory/nvidia,tegra238-mc.h\n> @@ -0,0 +1,74 @@\n> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */\n> +/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */\n> +\n> +#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H\n> +#define DT_BINDINGS_MEMORY_TEGRA238_MC_H\n> +\n> +/* special clients */\n> +#define TEGRA238_SID_INVALID\t\t0x0\n> +#define TEGRA238_SID_PASSTHROUGH\t0x7f\n> +\n> +/* ISO stream IDs */\n> +#define TEGRA238_SID_ISO_NVDISPLAY\t0x1\n> +#define TEGRA238_SID_ISO_APE0\t\t0x2\n> +#define TEGRA238_SID_ISO_APE1\t\t0x3\n> +\n> +/* NISO stream IDs */\n> +#define TEGRA238_SID_AON\t\t0x1\n> +#define TEGRA238_SID_BPMP\t\t0x2\n> +#define TEGRA238_SID_ETR\t\t0x3\n> +#define TEGRA238_SID_FDE\t\t0x4\n> +#define TEGRA238_SID_HC\t\t0x5\n> +#define TEGRA238_SID_HDA\t\t0x6\n> +#define TEGRA238_SID_NVDEC\t\t0x7\n> +#define TEGRA238_SID_NVDISPLAY\t\t0x8\n> +#define TEGRA238_SID_NVENC\t\t0x9\n> +#define TEGRA238_SID_OFA\t\t0xa\n> +#define TEGRA238_SID_PCIE0\t\t0xb\n> +#define TEGRA238_SID_PCIE1\t\t0xc\n> +#define TEGRA238_SID_PCIE2\t\t0xd\n> +#define TEGRA238_SID_PCIE3\t\t0xe\n> +#define TEGRA238_SID_HWMP_PMA\t\t0xf\n> +#define TEGRA238_SID_PSC\t\t0x10\n> +#define TEGRA238_SID_SDMMC1A\t\t0x11\n> +#define TEGRA238_SID_SDMMC4A\t\t0x12\n> +#define TEGRA238_SID_SES_SE0\t\t0x13\n> +#define TEGRA238_SID_SES_SE1\t\t0x14\n> +#define TEGRA238_SID_SES_SE2\t\t0x15\n> +#define TEGRA238_SID_SEU1_SE0\t\t0x16\n> +#define TEGRA238_SID_SEU1_SE1\t\t0x17\n> +#define TEGRA238_SID_SEU1_SE2\t\t0x18\n> +#define TEGRA238_SID_TSEC\t\t0x19\n> +#define TEGRA238_SID_UFSHC\t\t0x1a\n> +#define TEGRA238_SID_VIC\t\t0x1b\n> +#define TEGRA238_SID_XUSB_HOST\t\t0x1c\n> +#define TEGRA238_SID_XUSB_DEV\t\t0x1d\n> +#define TEGRA238_SID_GPCDMA_0\t\t0x1e\n> +#define TEGRA238_SID_SMMU_TEST\t\t0x1f\n> +\n> +/* Host1x virtualization clients. */\n> +#define TEGRA238_SID_HOST1X_CTX0\t0x20\n> +#define TEGRA238_SID_HOST1X_CTX1\t0x21\n> +#define TEGRA238_SID_HOST1X_CTX2\t0x22\n> +#define TEGRA238_SID_HOST1X_CTX3\t0x23\n> +#define TEGRA238_SID_HOST1X_CTX4\t0x24\n> +#define TEGRA238_SID_HOST1X_CTX5\t0x25\n> +#define TEGRA238_SID_HOST1X_CTX6\t0x26\n> +#define TEGRA238_SID_HOST1X_CTX7\t0x27\n> +\n> +#define TEGRA238_SID_XUSB_VF0\t\t0x28\n> +#define TEGRA238_SID_XUSB_VF1\t\t0x29\n> +#define TEGRA238_SID_XUSB_VF2\t\t0x2a\n> +#define TEGRA238_SID_XUSB_VF3\t\t0x2b\n> +\n> +/* Host1x command buffers */\n> +#define TEGRA238_SID_HC_VM0\t\t0x2c\n> +#define TEGRA238_SID_HC_VM1\t\t0x2d\n> +#define TEGRA238_SID_HC_VM2\t\t0x2e\n> +#define TEGRA238_SID_HC_VM3\t\t0x2f\n> +#define TEGRA238_SID_HC_VM4\t\t0x30\n> +#define TEGRA238_SID_HC_VM5\t\t0x31\n> +#define TEGRA238_SID_HC_VM6\t\t0x32\n> +#define TEGRA238_SID_HC_VM7\t\t0x33\n> +\n> +#endif\n\nReviewed-by: Jon Hunter \n\nThanks!\nJon","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Za4cQI65;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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