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GET /api/1.1/patches/2228644/?format=api
{ "id": 2228644, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228644/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427073419.567360-3-amhetre@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260427073419.567360-3-amhetre@nvidia.com>", "date": "2026-04-27T07:34:19", "name": "[V2,2/2] memory: tegra: Add T238 MC support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1d8304be0c3dd7c2d3cae95d578efc14f620e0e3", "submitter": { "id": 75198, "url": "http://patchwork.ozlabs.org/api/1.1/people/75198/?format=api", "name": "Ashish Mhetre", "email": "amhetre@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260427073419.567360-3-amhetre@nvidia.com/mbox/", "series": [ { "id": 501592, "url": "http://patchwork.ozlabs.org/api/1.1/series/501592/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501592", "date": "2026-04-27T07:34:19", "name": "memory: tegra: Add Tegra238 memory controller support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501592/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228644/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228644/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-13994-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com 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216.228.118.232 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C", "From": "Ashish Mhetre <amhetre@nvidia.com>", "To": "<krzk@kernel.org>, <robh@kernel.org>, <conor+dt@kernel.org>,\n\t<=thierry.reding@kernel.org>, <jonathanh@nvidia.com>, <sumitg@nvidia.com>", "CC": "<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Ashish Mhetre <amhetre@nvidia.com>", "Subject": "[PATCH V2 2/2] memory: tegra: Add T238 MC support", "Date": "Mon, 27 Apr 2026 07:34:19 +0000", "Message-ID": "<20260427073419.567360-3-amhetre@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260427073419.567360-1-amhetre@nvidia.com>", "References": "<20260427073419.567360-1-amhetre@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": 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"\n\t6FZIqyCWZ92yFunjxM8mLCg7/GZPreUv5NMSkolFi3AAPExxHsj16GvA4zqDCu1U8xWTywe02tzQljiwXEiHdhrl2faHtcbxlPL0LEJcGbbWKxcDi1nKPgT0lvvRQc1zmQEhATfdIKDZMNHbaEy+HPh/7ChdMf1DjLJOPDf2/oZL4esXDsugRNyoKrhKF8pjpuZqzKhphDJwuCMWojfI+XzR3cN3y5eD0DmZEXCqdC2144IZKYdjeGDI5dp86zMzYhBVqtZ5EhPUb72nkSe+DqUNGNYXlYEWkvQMNy88PHUpgmDOwgjx8j3mtWgfkiGPzTLZWgF4oOK8q6kOSdykF7CmIqH30xpYcU2fxNRcu1nQiMKz6RYAsYZnTyWk0o25m20MZnUJRZKrnfSnBqdy3N4GbFQw+LsDa5OLvlE9YR0qiRbQTnZ2fB5WiXFUKjDeV9Q98iEUvpI5wiR5au4Wky9bk13cjQHGF8jZDINKUWw8xc4zY+oUbr8ms5K3LL60H40WDY2qcmQUztHLJybq9QhGtCRFe7Pxsvu8F58q9fXMIYF6ihsU7T8a9PudYE4ZFW8/sXfkF6gr2WnxNsPGZt9UbwGCgsnEAhc23KAX3tDfZDr5j9sdDXSiZfkoU/bsYuXdyrNv8xC18+Tq0AlFeVax6OQDxNBtAeieu/+cvHAb9gBblLK+OhgMYw8J66+2d6hiLtljPnadSlOBD94pW2GNQq75qb1hHALbV/CXlHeRb2kyGbyOOrVIsz+QHVUSM0EjeSg22AVpCu1pEMQOvw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\taL3DhKnURcR1R28x1Ok4QUiHXnnFRdYIKNiptZClGzxHmaCNk8KrwTHVHXNdPlssqGgwsXdextfwkrAGp9AP5+nrutJgP/dgRjwRxPgXC9N6bjSg6o50QsWbDEf/QW+syFmhpSQrrA3/06juZo7YCszRMIWRaQN1Bcn17aeIBFocF3Edbdi0mo3CloaB4NL9Pl6GQR9IoF5XQpw8zkuFLSiTD2nXEoodEpC72OXbz8Yr4xNOIiwiuZ36qEWMubXZwiwpBZ7X52aGsIR/rKHXs+35R49IUuaACV9Dnq29qy5QPwBSUr7j8NdzI3smyrv1UwY/WYykJXoyFLc0DSUvFnOA6MHh+HPOYu7BXTAu7IUjn4+cAeqo1kRrDxrIbjVwxcp14ALEKqv4WA8mYDfORQikb4+TDMFJvgo+Sdo6K5QP+s3+IucSH7Y7QygUjoTp", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 07:34:42.2540\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f21a712f-5609-423a-9f94-08dea42f7263", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D7.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB6056" }, "content": "Add Memory Controller driver support for Tegra238 SOC, including:\n- MC client definitions with Tegra238-specific stream IDs\n- Reuse of Tegra234 ICC operations for bandwidth management via BPMP-FW\n- Device tree compatible string \"nvidia,tegra238-mc\"\n\nExport tegra234_mc_icc_ops so it can be shared with the Tegra238 MC\ndriver, as both SoCs use the same ICC aggregation and bandwidth\nmanagement logic.\n\nSigned-off-by: Ashish Mhetre <amhetre@nvidia.com>\n---\n drivers/memory/tegra/Makefile | 1 +\n drivers/memory/tegra/mc.c | 3 +\n drivers/memory/tegra/mc.h | 9 +\n drivers/memory/tegra/tegra234.c | 2 +-\n drivers/memory/tegra/tegra238.c | 391 ++++++++++++++++++++++++++++++++\n 5 files changed, 405 insertions(+), 1 deletion(-)\n create mode 100644 drivers/memory/tegra/tegra238.c", "diff": "diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile\nindex 6334601e6120..7c2fca12076b 100644\n--- a/drivers/memory/tegra/Makefile\n+++ b/drivers/memory/tegra/Makefile\n@@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o\n tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o\n tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o\n tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o\n+tegra-mc-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra186.o tegra234.o tegra238.o\n tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186.o tegra264.o\n \n obj-$(CONFIG_TEGRA_MC) += tegra-mc.o\ndiff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\nindex d620660da331..10ef3c323e22 100644\n--- a/drivers/memory/tegra/mc.c\n+++ b/drivers/memory/tegra/mc.c\n@@ -49,6 +49,9 @@ static const struct of_device_id tegra_mc_of_match[] = {\n #ifdef CONFIG_ARCH_TEGRA_234_SOC\n \t{ .compatible = \"nvidia,tegra234-mc\", .data = &tegra234_mc_soc },\n #endif\n+#ifdef CONFIG_ARCH_TEGRA_238_SOC\n+\t{ .compatible = \"nvidia,tegra238-mc\", .data = &tegra238_mc_soc },\n+#endif\n #ifdef CONFIG_ARCH_TEGRA_264_SOC\n \t{ .compatible = \"nvidia,tegra264-mc\", .data = &tegra264_mc_soc },\n #endif\ndiff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h\nindex 649b54369263..e94d265d7b67 100644\n--- a/drivers/memory/tegra/mc.h\n+++ b/drivers/memory/tegra/mc.h\n@@ -240,6 +240,14 @@ extern const struct tegra_mc_soc tegra194_mc_soc;\n extern const struct tegra_mc_soc tegra234_mc_soc;\n #endif\n \n+#if defined(CONFIG_ARCH_TEGRA_234_SOC) || defined(CONFIG_ARCH_TEGRA_238_SOC)\n+extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops;\n+#endif\n+\n+#ifdef CONFIG_ARCH_TEGRA_238_SOC\n+extern const struct tegra_mc_soc tegra238_mc_soc;\n+#endif\n+\n #ifdef CONFIG_ARCH_TEGRA_264_SOC\n extern const struct tegra_mc_soc tegra264_mc_soc;\n #endif\n@@ -256,6 +264,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops;\n #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \\\n defined(CONFIG_ARCH_TEGRA_194_SOC) || \\\n defined(CONFIG_ARCH_TEGRA_234_SOC) || \\\n+ defined(CONFIG_ARCH_TEGRA_238_SOC) || \\\n defined(CONFIG_ARCH_TEGRA_264_SOC)\n extern const struct tegra_mc_ops tegra186_mc_ops;\n #endif\ndiff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c\nindex 87b22038a5fb..9fbd34d4abe0 100644\n--- a/drivers/memory/tegra/tegra234.c\n+++ b/drivers/memory/tegra/tegra234.c\n@@ -1125,7 +1125,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea\n \treturn 0;\n }\n \n-static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {\n+const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {\n \t.xlate = tegra_mc_icc_xlate,\n \t.aggregate = tegra234_mc_icc_aggregate,\n \t.get_bw = tegra234_mc_icc_get_init_bw,\ndiff --git a/drivers/memory/tegra/tegra238.c b/drivers/memory/tegra/tegra238.c\nnew file mode 100644\nindex 000000000000..938c8985600e\n--- /dev/null\n+++ b/drivers/memory/tegra/tegra238.c\n@@ -0,0 +1,391 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved.\n+ */\n+\n+#include <soc/tegra/mc.h>\n+\n+#include <dt-bindings/memory/tegra234-mc.h>\n+#include <dt-bindings/memory/nvidia,tegra238-mc.h>\n+#include <linux/interconnect.h>\n+#include <linux/tegra-icc.h>\n+\n+#include <soc/tegra/bpmp.h>\n+#include \"mc.h\"\n+\n+static const struct tegra_mc_client tegra238_mc_clients[] = {\n+\t{\n+\t\t.id = TEGRA234_MEMORY_CLIENT_HDAR,\n+\t\t.name = \"hdar\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_HDA,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_HDA,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0xa8,\n+\t\t\t\t.security = 0xac,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_HDAW,\n+\t\t.name = \"hdaw\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_HDA,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_HDA,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x1a8,\n+\t\t\t\t.security = 0x1ac,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,\n+\t\t.name = \"sdmmcrab\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_SDMMC4A,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x318,\n+\t\t\t\t.security = 0x31c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,\n+\t\t.name = \"sdmmcwab\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_SDMMC4A,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x338,\n+\t\t\t\t.security = 0x33c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_APER,\n+\t\t.name = \"aper\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_APE,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_ISO_APE0,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x3d0,\n+\t\t\t\t.security = 0x3d4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_APEW,\n+\t\t.name = \"apew\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_APE,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_ISO_APE0,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x3d8,\n+\t\t\t\t.security = 0x3dc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,\n+\t\t.name = \"nvdisplayr\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,\n+\t\t.type = TEGRA_ICC_ISO_DISPLAY,\n+\t\t.sid = TEGRA238_SID_ISO_NVDISPLAY,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x490,\n+\t\t\t\t.security = 0x494,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,\n+\t\t.name = \"nvdisplayr1\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,\n+\t\t.type = TEGRA_ICC_ISO_DISPLAY,\n+\t\t.sid = TEGRA238_SID_ISO_NVDISPLAY,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x508,\n+\t\t\t\t.security = 0x50c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPR,\n+\t\t.name = \"bpmpr\",\n+\t\t.sid = TEGRA238_SID_BPMP,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x498,\n+\t\t\t\t.security = 0x49c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPW,\n+\t\t.name = \"bpmpw\",\n+\t\t.sid = TEGRA238_SID_BPMP,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x4a0,\n+\t\t\t\t.security = 0x4a4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,\n+\t\t.name = \"bpmpdmar\",\n+\t\t.sid = TEGRA238_SID_BPMP,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x4a8,\n+\t\t\t\t.security = 0x4ac,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,\n+\t\t.name = \"bpmpdmaw\",\n+\t\t.sid = TEGRA238_SID_BPMP,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x4b0,\n+\t\t\t\t.security = 0x4b4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_APEDMAR,\n+\t\t.name = \"apedmar\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_APEDMA,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_ISO_APE1,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x4f8,\n+\t\t\t\t.security = 0x4fc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_APEDMAW,\n+\t\t.name = \"apedmaw\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_APEDMA,\n+\t\t.type = TEGRA_ICC_ISO_AUDIO,\n+\t\t.sid = TEGRA238_SID_ISO_APE1,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x500,\n+\t\t\t\t.security = 0x504,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_VICSRD,\n+\t\t.name = \"vicsrd\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_VIC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_VIC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x360,\n+\t\t\t\t.security = 0x364,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_VICSWR,\n+\t\t.name = \"vicswr\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_VIC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_VIC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x368,\n+\t\t\t\t.security = 0x36c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,\n+\t\t.name = \"nvdecsrd\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_NVDEC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_NVDEC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x3c0,\n+\t\t\t\t.security = 0x3c4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,\n+\t\t.name = \"nvdecswr\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_NVDEC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_NVDEC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x3c8,\n+\t\t\t\t.security = 0x3cc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,\n+\t\t.name = \"nvencsrd\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_NVENC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_NVENC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0xe0,\n+\t\t\t\t.security = 0xe4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,\n+\t\t.name = \"nvencswr\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_NVENC,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_NVENC,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x158,\n+\t\t\t\t.security = 0x15c,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE0R,\n+\t\t.name = \"pcie0r\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE0,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6c0,\n+\t\t\t\t.security = 0x6c4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE0W,\n+\t\t.name = \"pcie0w\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE0,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6c8,\n+\t\t\t\t.security = 0x6cc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE1R,\n+\t\t.name = \"pcie1r\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE1,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6d0,\n+\t\t\t\t.security = 0x6d4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE1W,\n+\t\t.name = \"pcie1w\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE1,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6d8,\n+\t\t\t\t.security = 0x6dc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,\n+\t\t.name = \"pcie2ar\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE2,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6e0,\n+\t\t\t\t.security = 0x6e4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,\n+\t\t.name = \"pcie2aw\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE2,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6e8,\n+\t\t\t\t.security = 0x6ec,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE3R,\n+\t\t.name = \"pcie3r\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE3,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6f0,\n+\t\t\t\t.security = 0x6f4,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE3W,\n+\t\t.name = \"pcie3w\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t\t.sid = TEGRA238_SID_PCIE3,\n+\t\t.regs = {\n+\t\t\t.sid = {\n+\t\t\t\t.override = 0x6f8,\n+\t\t\t\t.security = 0x6fc,\n+\t\t\t},\n+\t\t},\n+\t}, {\n+\t\t.id = TEGRA_ICC_MC_CPU_CLUSTER0,\n+\t\t.name = \"sw_cluster0\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVL1R,\n+\t\t.name = \"nvl1r\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_GPU,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t}, {\n+\t\t.id = TEGRA234_MEMORY_CLIENT_NVL1W,\n+\t\t.name = \"nvl1w\",\n+\t\t.bpmp_id = TEGRA_ICC_BPMP_GPU,\n+\t\t.type = TEGRA_ICC_NISO,\n+\t}\n+};\n+\n+static const struct tegra_mc_intmask tegra238_mc_intmasks[] = {\n+\t{\n+\t\t.reg = MC_INTMASK,\n+\t\t.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |\n+\t\t\tMC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |\n+\t\t\tMC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,\n+\t},\n+};\n+\n+const struct tegra_mc_soc tegra238_mc_soc = {\n+\t.num_clients = ARRAY_SIZE(tegra238_mc_clients),\n+\t.clients = tegra238_mc_clients,\n+\t.num_address_bits = 40,\n+\t.num_channels = 8,\n+\t.client_id_mask = 0x1ff,\n+\t.intmasks = tegra238_mc_intmasks,\n+\t.num_intmasks = ARRAY_SIZE(tegra238_mc_intmasks),\n+\t.has_addr_hi_reg = true,\n+\t.ops = &tegra186_mc_ops,\n+\t.icc_ops = &tegra234_mc_icc_ops,\n+\t.ch_intmask = 0x0000ff00,\n+\t.global_intstatus_channel_shift = 8,\n+\t.num_carveouts = 32,\n+\t.regs = &tegra20_mc_regs,\n+\t.handle_irq = tegra30_mc_irq_handlers,\n+\t.num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),\n+\t.mc_addr_hi_mask = 0x3,\n+\t.mc_err_status_type_mask = (0x7 << 28),\n+};\n", "prefixes": [ "V2", "2/2" ] }