[{"id":3683953,"web_url":"http://patchwork.ozlabs.org/comment/3683953/","msgid":"","list_archive_url":null,"date":"2026-04-29T09:29:28","subject":"Re: [PATCH V2 2/2] memory: tegra: Add T238 MC support","submitter":{"id":66273,"url":"http://patchwork.ozlabs.org/api/people/66273/","name":"Jon Hunter","email":"jonathanh@nvidia.com"},"content":"On 27/04/2026 08:34, Ashish Mhetre wrote:\n\nWe prefer to use 'Tegra238' and not T238. However, don't worry too much \nabout that unless there are other comments.\n\n> Add Memory Controller driver support for Tegra238 SOC, including:\n> - MC client definitions with Tegra238-specific stream IDs\n> - Reuse of Tegra234 ICC operations for bandwidth management via BPMP-FW\n> - Device tree compatible string \"nvidia,tegra238-mc\"\n> \n> Export tegra234_mc_icc_ops so it can be shared with the Tegra238 MC\n> driver, as both SoCs use the same ICC aggregation and bandwidth\n> management logic.\n> \n> Signed-off-by: Ashish Mhetre \n> ---\n> drivers/memory/tegra/Makefile | 1 +\n> drivers/memory/tegra/mc.c | 3 +\n> drivers/memory/tegra/mc.h | 9 +\n> drivers/memory/tegra/tegra234.c | 2 +-\n> drivers/memory/tegra/tegra238.c | 391 ++++++++++++++++++++++++++++++++\n> 5 files changed, 405 insertions(+), 1 deletion(-)\n> create mode 100644 drivers/memory/tegra/tegra238.c\n> \n> diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile\n> index 6334601e6120..7c2fca12076b 100644\n> --- a/drivers/memory/tegra/Makefile\n> +++ b/drivers/memory/tegra/Makefile\n> @@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o\n> tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o\n> tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o\n> tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o\n> +tegra-mc-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra186.o tegra234.o tegra238.o\n> tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186.o tegra264.o\n> \n> obj-$(CONFIG_TEGRA_MC) += tegra-mc.o\n> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\n> index d620660da331..10ef3c323e22 100644\n> --- a/drivers/memory/tegra/mc.c\n> +++ b/drivers/memory/tegra/mc.c\n> @@ -49,6 +49,9 @@ static const struct of_device_id tegra_mc_of_match[] = {\n> #ifdef CONFIG_ARCH_TEGRA_234_SOC\n> \t{ .compatible = \"nvidia,tegra234-mc\", .data = &tegra234_mc_soc },\n> #endif\n> +#ifdef CONFIG_ARCH_TEGRA_238_SOC\n> +\t{ .compatible = \"nvidia,tegra238-mc\", .data = &tegra238_mc_soc },\n> +#endif\n> #ifdef CONFIG_ARCH_TEGRA_264_SOC\n> \t{ .compatible = \"nvidia,tegra264-mc\", .data = &tegra264_mc_soc },\n> #endif\n> diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h\n> index 649b54369263..e94d265d7b67 100644\n> --- a/drivers/memory/tegra/mc.h\n> +++ b/drivers/memory/tegra/mc.h\n> @@ -240,6 +240,14 @@ extern const struct tegra_mc_soc tegra194_mc_soc;\n> extern const struct tegra_mc_soc tegra234_mc_soc;\n> #endif\n> \n> +#if defined(CONFIG_ARCH_TEGRA_234_SOC) || defined(CONFIG_ARCH_TEGRA_238_SOC)\n> +extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops;\n> +#endif\n> +\n> +#ifdef CONFIG_ARCH_TEGRA_238_SOC\n> +extern const struct tegra_mc_soc tegra238_mc_soc;\n> +#endif\n> +\n> #ifdef CONFIG_ARCH_TEGRA_264_SOC\n> extern const struct tegra_mc_soc tegra264_mc_soc;\n> #endif\n> @@ -256,6 +264,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops;\n> #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \\\n> defined(CONFIG_ARCH_TEGRA_194_SOC) || \\\n> defined(CONFIG_ARCH_TEGRA_234_SOC) || \\\n> + defined(CONFIG_ARCH_TEGRA_238_SOC) || \\\n> defined(CONFIG_ARCH_TEGRA_264_SOC)\n> extern const struct tegra_mc_ops tegra186_mc_ops;\n> #endif\n> diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c\n> index 87b22038a5fb..9fbd34d4abe0 100644\n> --- a/drivers/memory/tegra/tegra234.c\n> +++ b/drivers/memory/tegra/tegra234.c\n> @@ -1125,7 +1125,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea\n> \treturn 0;\n> }\n> \n> -static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {\n> +const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {\n> \t.xlate = tegra_mc_icc_xlate,\n> \t.aggregate = tegra234_mc_icc_aggregate,\n> \t.get_bw = tegra234_mc_icc_get_init_bw,\n> diff --git a/drivers/memory/tegra/tegra238.c b/drivers/memory/tegra/tegra238.c\n> new file mode 100644\n> index 000000000000..938c8985600e\n> --- /dev/null\n> +++ b/drivers/memory/tegra/tegra238.c\n> @@ -0,0 +1,391 @@\n> +// SPDX-License-Identifier: GPL-2.0-only\n> +/*\n> + * Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved.\n> + */\n> +\n> +#include \n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +#include \"mc.h\"\n> +\n> +static const struct tegra_mc_client tegra238_mc_clients[] = {\n> +\t{\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_HDAR,\n> +\t\t.name = \"hdar\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_HDA,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_HDA,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0xa8,\n> +\t\t\t\t.security = 0xac,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_HDAW,\n> +\t\t.name = \"hdaw\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_HDA,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_HDA,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x1a8,\n> +\t\t\t\t.security = 0x1ac,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,\n> +\t\t.name = \"sdmmcrab\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_SDMMC4A,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x318,\n> +\t\t\t\t.security = 0x31c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,\n> +\t\t.name = \"sdmmcwab\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_SDMMC4A,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x338,\n> +\t\t\t\t.security = 0x33c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_APER,\n> +\t\t.name = \"aper\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_APE,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_ISO_APE0,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x3d0,\n> +\t\t\t\t.security = 0x3d4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_APEW,\n> +\t\t.name = \"apew\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_APE,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_ISO_APE0,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x3d8,\n> +\t\t\t\t.security = 0x3dc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,\n> +\t\t.name = \"nvdisplayr\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,\n> +\t\t.type = TEGRA_ICC_ISO_DISPLAY,\n> +\t\t.sid = TEGRA238_SID_ISO_NVDISPLAY,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x490,\n> +\t\t\t\t.security = 0x494,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,\n> +\t\t.name = \"nvdisplayr1\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,\n> +\t\t.type = TEGRA_ICC_ISO_DISPLAY,\n> +\t\t.sid = TEGRA238_SID_ISO_NVDISPLAY,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x508,\n> +\t\t\t\t.security = 0x50c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPR,\n> +\t\t.name = \"bpmpr\",\n> +\t\t.sid = TEGRA238_SID_BPMP,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x498,\n> +\t\t\t\t.security = 0x49c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPW,\n> +\t\t.name = \"bpmpw\",\n> +\t\t.sid = TEGRA238_SID_BPMP,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x4a0,\n> +\t\t\t\t.security = 0x4a4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,\n> +\t\t.name = \"bpmpdmar\",\n> +\t\t.sid = TEGRA238_SID_BPMP,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x4a8,\n> +\t\t\t\t.security = 0x4ac,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,\n> +\t\t.name = \"bpmpdmaw\",\n> +\t\t.sid = TEGRA238_SID_BPMP,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x4b0,\n> +\t\t\t\t.security = 0x4b4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_APEDMAR,\n> +\t\t.name = \"apedmar\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_APEDMA,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_ISO_APE1,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x4f8,\n> +\t\t\t\t.security = 0x4fc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_APEDMAW,\n> +\t\t.name = \"apedmaw\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_APEDMA,\n> +\t\t.type = TEGRA_ICC_ISO_AUDIO,\n> +\t\t.sid = TEGRA238_SID_ISO_APE1,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x500,\n> +\t\t\t\t.security = 0x504,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_VICSRD,\n> +\t\t.name = \"vicsrd\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_VIC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_VIC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x360,\n> +\t\t\t\t.security = 0x364,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_VICSWR,\n> +\t\t.name = \"vicswr\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_VIC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_VIC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x368,\n> +\t\t\t\t.security = 0x36c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,\n> +\t\t.name = \"nvdecsrd\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_NVDEC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_NVDEC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x3c0,\n> +\t\t\t\t.security = 0x3c4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,\n> +\t\t.name = \"nvdecswr\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_NVDEC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_NVDEC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x3c8,\n> +\t\t\t\t.security = 0x3cc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,\n> +\t\t.name = \"nvencsrd\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_NVENC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_NVENC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0xe0,\n> +\t\t\t\t.security = 0xe4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,\n> +\t\t.name = \"nvencswr\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_NVENC,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_NVENC,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x158,\n> +\t\t\t\t.security = 0x15c,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE0R,\n> +\t\t.name = \"pcie0r\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE0,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6c0,\n> +\t\t\t\t.security = 0x6c4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE0W,\n> +\t\t.name = \"pcie0w\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE0,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6c8,\n> +\t\t\t\t.security = 0x6cc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE1R,\n> +\t\t.name = \"pcie1r\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE1,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6d0,\n> +\t\t\t\t.security = 0x6d4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE1W,\n> +\t\t.name = \"pcie1w\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE1,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6d8,\n> +\t\t\t\t.security = 0x6dc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,\n> +\t\t.name = \"pcie2ar\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE2,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6e0,\n> +\t\t\t\t.security = 0x6e4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,\n> +\t\t.name = \"pcie2aw\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE2,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6e8,\n> +\t\t\t\t.security = 0x6ec,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE3R,\n> +\t\t.name = \"pcie3r\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE3,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6f0,\n> +\t\t\t\t.security = 0x6f4,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_PCIE3W,\n> +\t\t.name = \"pcie3w\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t\t.sid = TEGRA238_SID_PCIE3,\n> +\t\t.regs = {\n> +\t\t\t.sid = {\n> +\t\t\t\t.override = 0x6f8,\n> +\t\t\t\t.security = 0x6fc,\n> +\t\t\t},\n> +\t\t},\n> +\t}, {\n> +\t\t.id = TEGRA_ICC_MC_CPU_CLUSTER0,\n> +\t\t.name = \"sw_cluster0\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVL1R,\n> +\t\t.name = \"nvl1r\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_GPU,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t}, {\n> +\t\t.id = TEGRA234_MEMORY_CLIENT_NVL1W,\n> +\t\t.name = \"nvl1w\",\n> +\t\t.bpmp_id = TEGRA_ICC_BPMP_GPU,\n> +\t\t.type = TEGRA_ICC_NISO,\n> +\t}\n> +};\n> +\n> +static const struct tegra_mc_intmask tegra238_mc_intmasks[] = {\n> +\t{\n> +\t\t.reg = MC_INTMASK,\n> +\t\t.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |\n> +\t\t\tMC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |\n> +\t\t\tMC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,\n> +\t},\n> +};\n> +\n> +const struct tegra_mc_soc tegra238_mc_soc = {\n> +\t.num_clients = ARRAY_SIZE(tegra238_mc_clients),\n> +\t.clients = tegra238_mc_clients,\n> +\t.num_address_bits = 40,\n> +\t.num_channels = 8,\n> +\t.client_id_mask = 0x1ff,\n> +\t.intmasks = tegra238_mc_intmasks,\n> +\t.num_intmasks = ARRAY_SIZE(tegra238_mc_intmasks),\n> +\t.has_addr_hi_reg = true,\n> +\t.ops = &tegra186_mc_ops,\n> +\t.icc_ops = &tegra234_mc_icc_ops,\n> +\t.ch_intmask = 0x0000ff00,\n> +\t.global_intstatus_channel_shift = 8,\n> +\t.num_carveouts = 32,\n> +\t.regs = &tegra20_mc_regs,\n> +\t.handle_irq = tegra30_mc_irq_handlers,\n> +\t.num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),\n> +\t.mc_addr_hi_mask = 0x3,\n> +\t.mc_err_status_type_mask = (0x7 << 28),\n> +};\n\nReviewed-by: Jon Hunter \n\nThanks!\nJon","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=GBONFiVQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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