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GET /api/1.1/patches/2228637/?format=api
{ "id": 2228637, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228637/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org>", "date": "2026-04-27T05:52:49", "name": "[1/4] mmc: exynos_dw_mmc: add proper init sequence for HS400 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9598b878935c6faa9e0ffb4cd177ffc4e85e45f0", "submitter": { "id": 88698, "url": "http://patchwork.ozlabs.org/api/1.1/people/88698/?format=api", "name": "Kaustabh Chakraborty", "email": "kauschluss@disroot.org" }, "delegate": { "id": 1728, "url": "http://patchwork.ozlabs.org/api/1.1/users/1728/?format=api", "username": "prom", "first_name": "Minkyu", "last_name": "Kang", "email": "promsoft@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org/mbox/", "series": [ { "id": 501590, "url": "http://patchwork.ozlabs.org/api/1.1/series/501590/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501590", "date": "2026-04-27T05:52:48", "name": "HS400 and HS400ES support for Exynos DW-MMC drivers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501590/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228637/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228637/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=disroot.org header.i=@disroot.org header.a=rsa-sha256\n header.s=mail header.b=RK8NTBKB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=disroot.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n secure) header.d=disroot.org header.i=@disroot.org header.b=\"RK8NTBKB\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=disroot.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=kauschluss@disroot.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g3wDG3jqBz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 27 Apr 2026 17:29:02 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C8B9D83FDB;\n\tMon, 27 Apr 2026 09:28:51 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id ACBDB839D9; Mon, 27 Apr 2026 07:53:05 +0200 (CEST)", "from layka.disroot.org (layka.disroot.org [178.21.23.139])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 9C05480077\n for <u-boot@lists.denx.de>; Mon, 27 Apr 2026 07:53:03 +0200 (CEST)", "from mail01.disroot.lan (localhost [127.0.0.1])\n by disroot.org (Postfix) with ESMTP id 675B02763D;\n Mon, 27 Apr 2026 07:53:03 +0200 (CEST)", "from layka.disroot.org ([127.0.0.1])\n by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id tE88srMVEeqv; Mon, 27 Apr 2026 07:53:02 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail;\n t=1777269182; bh=/g0d0DyCdcytgaW5sWw4W3COrOHoHradKWnRLv8iz1o=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc;\n b=RK8NTBKBh2T4R2NerVCp/PZ8RXFC/uunW94g8ZOmz8I36yH+mzAnTAnYVonGIhcRC\n r2fs1FYI5Jueb2n9CVmoL/Icv4aXyrbZNRTZHtp8wfOYtUpS4bD4r51VrZc1ZlP1ZT\n U4E8H/7fq4KFJnDoyseztCMR+OSAhWPiquSFpWr+9Gh4V9YPxuaNcLGlC45wkhSE/J\n U8hRxab0iVg90NRn2SdE3FTi1yBJeY2O3gJRfVV0Jsp2a6FCIQczna39DVjPpOglO7\n i4beU5faFqpV/r/x+NWC5z36Ty3FA/mhudM5tD6f2J3bZDV+cm1Bv0D8V0xdFnVHqQ\n 0WElwAGkfIyxA==", "From": "Kaustabh Chakraborty <kauschluss@disroot.org>", "Date": "Mon, 27 Apr 2026 11:22:49 +0530", "Subject": "[PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for HS400\n support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org>", "References": "<20260427-dwmmc-exynos-hs400-es-v1-0-3495df40a9ac@disroot.org>", "In-Reply-To": "<20260427-dwmmc-exynos-hs400-es-v1-0-3495df40a9ac@disroot.org>", "To": "Peng Fan <peng.fan@nxp.com>, u-boot@lists.denx.de", "Cc": "Minkyu Kang <mk7.kang@samsung.com>, Tom Rini <trini@konsulko.com>,\n Jaehoon Chung <jh80.chung@samsung.com>, Anand Moon <linux.amoon@gmail.com>,\n Sam Protsenko <semen.protsenko@linaro.org>,\n Lukas Timmermann <uboot@timmermann.space>,\n Henrik Grimler <henrik@grimler.se>,\n Kaustabh Chakraborty <kauschluss@disroot.org>", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 09:28:50 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "HS400 support was added, but configuration necessary for HS400 support\nwas left out. Add necessary changes, which includes:\n- Device tree properties, such as \"samsung,dw-mshc-hs400-timing\" and\n \"samsung,read-strobe-delay\", which function as per dt-bindings.\n- Registers related to HS400, which are necessary to enable HS400+ support.\n- Appropriate timing tunings for the HS400 mode.\n\nNote that these changes are loosely based off of its Linux kernel\ncounterpart.\n\nFixes: bbe3b9fa0922 (\"mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes\")\nSigned-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>\n---\n arch/arm/mach-exynos/include/mach/dwmmc.h | 5 ++\n drivers/mmc/exynos_dw_mmc.c | 80 +++++++++++++++++++++++++++++++\n 2 files changed, 85 insertions(+)", "diff": "diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h\nindex 4432deedef7..50081326c25 100644\n--- a/arch/arm/mach-exynos/include/mach/dwmmc.h\n+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h\n@@ -15,6 +15,11 @@\n #define DWMCI_SET_DRV_CLK(x)\t\t((x) << 16)\n #define DWMCI_SET_DIV_RATIO(x)\t\t((x) << 24)\n \n+/* HS400 Related Registers */\n+#define DWMCI_HS400_DQS_EN\t\t0x180\n+#define DWMCI_HS400_ASYNC_FIFO_CTRL\t0x184\n+#define DWMCI_HS400_DLINE_CTRL\t\t0x188\n+\n /* Protector Register */\n #define DWMCI_EMMCP_BASE\t\t0x1000\n #define EMMCP_MPSECURITY\t\t(DWMCI_EMMCP_BASE + 0x0010)\ndiff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c\nindex 7ccd113bd79..d5e90a9bd5c 100644\n--- a/drivers/mmc/exynos_dw_mmc.c\n+++ b/drivers/mmc/exynos_dw_mmc.c\n@@ -8,6 +8,7 @@\n #include <dwmmc.h>\n #include <asm/global_data.h>\n #include <malloc.h>\n+#include <mmc.h>\n #include <errno.h>\n #include <asm/arch/dwmmc.h>\n #include <asm/arch/clk.h>\n@@ -30,6 +31,14 @@\n #define CLKSEL_UP_SAMPLE(x, y)\t\t(((x) & ~CLKSEL_CCLK_SAMPLE(7)) | \\\n \t\t\t\t\t CLKSEL_CCLK_SAMPLE(y))\n \n+/* RCLK_EN register defines */\n+#define DATA_STROBE_EN\t\t\tBIT(0)\n+#define AXI_NON_BLOCKING_WR\tBIT(7)\n+\n+/* DLINE_CTRL register defines */\n+#define DQS_CTRL_RD_DELAY(x, y)\t\t(((x) & ~0x3FF) | ((y) & 0x3FF))\n+#define DQS_CTRL_GET_RD_DELAY(x)\t((x) & 0x3FF)\n+\n /**\n * DOC: Quirk flags for different Exynos DW MMC blocks\n *\n@@ -71,6 +80,11 @@ struct dwmci_exynos_priv_data {\n \tstruct clk clk;\n \tu32 sdr_timing;\n \tu32 ddr_timing;\n+\tu32 hs400_timing;\n+\tu32 tuned_sample;\n+\tu32 dqs_delay;\n+\tu32 saved_dqs_en;\n+\tu32 saved_strobe_ctrl;\n \tconst struct exynos_dwmmc_variant *chip;\n };\n \n@@ -162,6 +176,27 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)\n \t\t\t\t& DWMCI_DIVRATIO_MASK) + 1;\n }\n \n+static void exynos_config_hs400(struct dwmci_host *host, enum bus_mode mode)\n+{\n+\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n+\tu32 dqs, strobe;\n+\n+\tdqs = priv->saved_dqs_en;\n+\tstrobe = priv->saved_strobe_ctrl;\n+\n+\tswitch (mode) {\n+\tcase MMC_HS_400:\n+\t\tdqs |= DATA_STROBE_EN;\n+\t\tstrobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);\n+\t\tbreak;\n+\tdefault:\n+\t\tdqs &= ~DATA_STROBE_EN;\n+\t}\n+\n+\tdwmci_writel(host, DWMCI_HS400_DQS_EN, dqs);\n+\tdwmci_writel(host, DWMCI_HS400_DLINE_CTRL, strobe);\n+}\n+\n /* Configure CLKSEL register with chosen timing values */\n static int exynos_dwmci_clksel(struct dwmci_host *host)\n {\n@@ -170,6 +205,9 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n \tu32 timing;\n \n \tswitch (host->mmc->selected_mode) {\n+\tcase MMC_HS_400:\n+\t\ttiming = CLKSEL_UP_SAMPLE(priv->hs400_timing, priv->tuned_sample);\n+\t\tbreak;\n \tcase MMC_DDR_52:\n \t\ttiming = priv->ddr_timing;\n \t\tbreak;\n@@ -186,6 +224,8 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n \n \tdwmci_writel(host, priv->chip->clksel, timing);\n \n+\texynos_config_hs400(host, host->mmc->selected_mode);\n+\n \treturn 0;\n }\n \n@@ -223,6 +263,16 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)\n {\n \tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n \n+\tif (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) {\n+\t\tpriv->saved_strobe_ctrl = dwmci_readl(host, DWMCI_HS400_DLINE_CTRL);\n+\t\tpriv->saved_dqs_en = dwmci_readl(host, DWMCI_HS400_DQS_EN);\n+\t\tpriv->saved_dqs_en |= AXI_NON_BLOCKING_WR;\n+\t\tdwmci_writel(host, DWMCI_HS400_DQS_EN, priv->saved_dqs_en);\n+\t\tif (!priv->dqs_delay)\n+\t\t\tpriv->dqs_delay =\n+\t\t\t\tDQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);\n+\t}\n+\n \tif (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) {\n \t\tdwmci_writel(host, EMMCP_MPSBEGIN0, 0);\n \t\tdwmci_writel(host, EMMCP_SEND0, 0);\n@@ -319,6 +369,22 @@ static int exynos_dwmmc_of_to_plat(struct udevice *dev)\n \t\t\t\t DWMCI_SET_DIV_RATIO(div);\n \t}\n \n+\terr = dev_read_u32_array(dev, \"samsung,dw-mshc-hs400-timing\", timing, 2);\n+\tif (err) {\n+\t\tdebug(\"DWMMC%d: Can't get hs400-timings, using ddr-timings\\n\",\n+\t\t host->dev_index);\n+\t\tpriv->hs400_timing = priv->ddr_timing;\n+\t} else {\n+\t\tpriv->hs400_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |\n+\t\t\t\t DWMCI_SET_DRV_CLK(timing[1]) |\n+\t\t\t\t DWMCI_SET_DIV_RATIO(1);\n+\t\tif (dev_read_u32(dev, \"samsung,read-strobe-delay\", &priv->dqs_delay)) {\n+\t\t\tpriv->dqs_delay = 0;\n+\t\t\tdebug(\"DWMMC%d: read-strobe-delay is not found, assuming usage of default value\\n\",\n+\t\t\t host->dev_index);\n+\t\t}\n+\t}\n+\n \thost->buswidth = dev_read_u32_default(dev, \"bus-width\", 4);\n \thost->fifo_depth = dev_read_u32_default(dev, \"fifo-depth\", 0);\n \thost->bus_hz = dev_read_u32_default(dev, \"clock-frequency\", 0);\n@@ -356,6 +422,16 @@ static int exynos_dwmmc_get_best_clksmpl(u8 candidates)\n \treturn -EIO;\n }\n \n+static int dw_mci_exynos_prepare_hs400_tuning(struct dwmci_host *host)\n+{\n+\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n+\n+\tdwmci_writel(host, priv->chip->clksel, priv->hs400_timing);\n+\thost->bus_hz = exynos_dwmci_get_clk(host, host->clock);\n+\n+\treturn 0;\n+}\n+\n static int exynos_dwmmc_execute_tuning(struct udevice *dev, u32 opcode)\n {\n \tstruct dwmci_exynos_priv_data *priv = dev_get_priv(dev);\n@@ -365,6 +441,9 @@ static int exynos_dwmmc_execute_tuning(struct udevice *dev, u32 opcode)\n \tu32 clksel;\n \tint ret;\n \n+\tif (mmc->hs400_tuning)\n+\t\tdw_mci_exynos_prepare_hs400_tuning(host);\n+\n \tclksel = dwmci_readl(host, priv->chip->clksel);\n \tstart_smpl = CLKSEL_CCLK_SAMPLE(clksel);\n \n@@ -387,6 +466,7 @@ static int exynos_dwmmc_execute_tuning(struct udevice *dev, u32 opcode)\n \t\treturn ret;\n \t}\n \n+\tpriv->tuned_sample = ret;\n \tdwmci_writel(host, priv->chip->clksel, CLKSEL_UP_SAMPLE(clksel, ret));\n \n \treturn 0;\n", "prefixes": [ "1/4" ] }