[{"id":3684861,"web_url":"http://patchwork.ozlabs.org/comment/3684861/","msgid":"<20260430172638.GA17167@localhost>","list_archive_url":null,"date":"2026-04-30T17:26:38","subject":"Re: [PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for\n HS400 support","submitter":{"id":83221,"url":"http://patchwork.ozlabs.org/api/people/83221/","name":"Henrik Grimler","email":"henrik@grimler.se"},"content":"Hi Kaustabh,\n\nOn Mon, Apr 27, 2026 at 11:22:49AM +0530, Kaustabh Chakraborty wrote:\n> HS400 support was added, but configuration necessary for HS400 support\n> was left out. Add necessary changes, which includes:\n> - Device tree properties, such as \"samsung,dw-mshc-hs400-timing\" and\n> \"samsung,read-strobe-delay\", which function as per dt-bindings.\n> - Registers related to HS400, which are necessary to enable HS400+ support.\n> - Appropriate timing tunings for the HS400 mode.\n> \n> Note that these changes are loosely based off of its Linux kernel\n> counterpart.\n> \n> Fixes: bbe3b9fa0922 (\"mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes\")\n> Signed-off-by: Kaustabh Chakraborty \n> ---\n> arch/arm/mach-exynos/include/mach/dwmmc.h | 5 ++\n> drivers/mmc/exynos_dw_mmc.c | 80 +++++++++++++++++++++++++++++++\n> 2 files changed, 85 insertions(+)\n> \n> diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h\n> index 4432deedef7..50081326c25 100644\n> --- a/arch/arm/mach-exynos/include/mach/dwmmc.h\n> +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h\n> @@ -15,6 +15,11 @@\n> #define DWMCI_SET_DRV_CLK(x)\t\t((x) << 16)\n> #define DWMCI_SET_DIV_RATIO(x)\t\t((x) << 24)\n> \n> +/* HS400 Related Registers */\n> +#define DWMCI_HS400_DQS_EN\t\t0x180\n> +#define DWMCI_HS400_ASYNC_FIFO_CTRL\t0x184\n> +#define DWMCI_HS400_DLINE_CTRL\t\t0x188\n> +\n> /* Protector Register */\n> #define DWMCI_EMMCP_BASE\t\t0x1000\n> #define EMMCP_MPSECURITY\t\t(DWMCI_EMMCP_BASE + 0x0010)\n> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c\n> index 7ccd113bd79..d5e90a9bd5c 100644\n> --- a/drivers/mmc/exynos_dw_mmc.c\n> +++ b/drivers/mmc/exynos_dw_mmc.c\n> @@ -8,6 +8,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -30,6 +31,14 @@\n> #define CLKSEL_UP_SAMPLE(x, y)\t\t(((x) & ~CLKSEL_CCLK_SAMPLE(7)) | \\\n> \t\t\t\t\t CLKSEL_CCLK_SAMPLE(y))\n> \n> +/* RCLK_EN register defines */\n> +#define DATA_STROBE_EN\t\t\tBIT(0)\n> +#define AXI_NON_BLOCKING_WR\tBIT(7)\n> +\n> +/* DLINE_CTRL register defines */\n> +#define DQS_CTRL_RD_DELAY(x, y)\t\t(((x) & ~0x3FF) | ((y) & 0x3FF))\n> +#define DQS_CTRL_GET_RD_DELAY(x)\t((x) & 0x3FF)\n> +\n> /**\n> * DOC: Quirk flags for different Exynos DW MMC blocks\n> *\n> @@ -71,6 +80,11 @@ struct dwmci_exynos_priv_data {\n> \tstruct clk clk;\n> \tu32 sdr_timing;\n> \tu32 ddr_timing;\n> +\tu32 hs400_timing;\n> +\tu32 tuned_sample;\n> +\tu32 dqs_delay;\n> +\tu32 saved_dqs_en;\n> +\tu32 saved_strobe_ctrl;\n> \tconst struct exynos_dwmmc_variant *chip;\n> };\n> \n> @@ -162,6 +176,27 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)\n> \t\t\t\t& DWMCI_DIVRATIO_MASK) + 1;\n> }\n> \n> +static void exynos_config_hs400(struct dwmci_host *host, enum bus_mode mode)\n> +{\n> +\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n> +\tu32 dqs, strobe;\n> +\n> +\tdqs = priv->saved_dqs_en;\n> +\tstrobe = priv->saved_strobe_ctrl;\n> +\n> +\tswitch (mode) {\n> +\tcase MMC_HS_400:\n> +\t\tdqs |= DATA_STROBE_EN;\n> +\t\tstrobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);\n> +\t\tbreak;\n> +\tdefault:\n> +\t\tdqs &= ~DATA_STROBE_EN;\n> +\t}\n> +\n> +\tdwmci_writel(host, DWMCI_HS400_DQS_EN, dqs);\n> +\tdwmci_writel(host, DWMCI_HS400_DLINE_CTRL, strobe);\n> +}\n> +\n> /* Configure CLKSEL register with chosen timing values */\n> static int exynos_dwmci_clksel(struct dwmci_host *host)\n> {\n> @@ -170,6 +205,9 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n> \tu32 timing;\n> \n> \tswitch (host->mmc->selected_mode) {\n> +\tcase MMC_HS_400:\n> +\t\ttiming = CLKSEL_UP_SAMPLE(priv->hs400_timing, priv->tuned_sample);\n> +\t\tbreak;\n> \tcase MMC_DDR_52:\n> \t\ttiming = priv->ddr_timing;\n> \t\tbreak;\n> @@ -186,6 +224,8 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n> \n> \tdwmci_writel(host, priv->chip->clksel, timing);\n> \n> +\texynos_config_hs400(host, host->mmc->selected_mode);\n> +\n\nThis breaks emmc in Linux for existing devices without hs400 support:\nexynos_config_hs400 is run no matter if the dt has the hs400\nparameters, meaning 0x0 is written to DWMCI_HS400_DQS_EN and\nDWMCI_HS400_DLINE_CTRL. U-boot does not seem to care, it loads the\nkernel and initramfs without issues, but Linux later gives errors:\n\n```\n[ 20.741025] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)\n[ 20.886686] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n[ 20.895138] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)\n[ 20.905990] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n[ 20.914988] mmc_host mmc0: Bus speed (slot 0) = 400000000Hz (slot req 200000000Hz, actual 200000000HZ div = 1)\n[ 21.099546] I/O error, dev mmcblk0, sector 1000001 op 0x1:(WRITE) flags 0x800 phys_seg 16 prio class 2\n[ 21.099853] I/O error, dev mmcblk0, sector 1000825 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n[ 21.107443] Buffer I/O error on dev mmcblk0p2, logical block 0, lost async page write\n[ 21.107473] Buffer I/O error on dev mmcblk0p2, logical block 1, lost async page write\n[ 21.116657] Buffer I/O error on dev mmcblk0p2, logical block 824, lost async page write\n[ 21.124408] Buffer I/O error on dev mmcblk0p2, logical block 2, lost async page write\n[ 21.132206] Buffer I/O error on dev mmcblk0p2, logical block 825, lost async page write\n[ 21.140178] Buffer I/O error on dev mmcblk0p2, logical block 3, lost async page write\n[ 21.147973] Buffer I/O error on dev mmcblk0p2, logical block 826, lost async page write\n[ 21.155960] Buffer I/O error on dev mmcblk0p2, logical block 4, lost async page write\n[ 21.163749] Buffer I/O error on dev mmcblk0p2, logical block 827, lost async page write\n[ 21.171720] Buffer I/O error on dev mmcblk0p2, logical block 5, lost async page write\n[ 21.200708] I/O error, dev mmcblk0, sector 1000873 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n[ 21.201043] I/O error, dev mmcblk0, sector 1000929 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n[ 21.218287] I/O error, dev mmcblk0, sector 1000945 op 0x1:(WRITE) flags 0x800 phys_seg 80 prio class 2\n[ 21.218623] I/O error, dev mmcblk0, sector 1001033 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n[ 21.236813] I/O error, dev mmcblk0, sector 1001097 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n[ 21.237146] I/O error, dev mmcblk0, sector 1001121 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n[ 21.255370] I/O error, dev mmcblk0, sector 1001161 op 0x1:(WRITE) flags 0x800 phys_seg 56 prio class 2\n[ 21.256253] I/O error, dev mmcblk0, sector 1001249 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n```\n\nSpecifically it seems to be writing 0x0 to DWMCI_HS400_DQS_EN that is\nthe issue, if I comment out that line it works also for my odroid-xu4\nin non-hs400 mode.\n\nTested on odroid-xu4 with odroid-xu3_defconfig after applying the\nentire series, without any other changes.\n\nBest regards,\nHenrik Grimler","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n secure) header.d=grimler.se header.i=@grimler.se header.a=rsa-sha256\n header.s=key1 header.b=iNOtzVSk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org>","X-Migadu-Flow":"FLOW_OUT","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3684923,"web_url":"http://patchwork.ozlabs.org/comment/3684923/","msgid":"","list_archive_url":null,"date":"2026-04-30T19:41:29","subject":"Re: [PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for\n HS400 support","submitter":{"id":88698,"url":"http://patchwork.ozlabs.org/api/people/88698/","name":"Kaustabh Chakraborty","email":"kauschluss@disroot.org"},"content":"On 2026-04-30 19:26 +02:00, Henrik Grimler wrote:\n> Hi Kaustabh,\n>\n> On Mon, Apr 27, 2026 at 11:22:49AM +0530, Kaustabh Chakraborty wrote:\n>> HS400 support was added, but configuration necessary for HS400 support\n>> was left out. Add necessary changes, which includes:\n>> - Device tree properties, such as \"samsung,dw-mshc-hs400-timing\" and\n>> \"samsung,read-strobe-delay\", which function as per dt-bindings.\n>> - Registers related to HS400, which are necessary to enable HS400+ support.\n>> - Appropriate timing tunings for the HS400 mode.\n>> \n>> Note that these changes are loosely based off of its Linux kernel\n>> counterpart.\n>> \n>> Fixes: bbe3b9fa0922 (\"mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes\")\n>> Signed-off-by: Kaustabh Chakraborty \n>> ---\n>> arch/arm/mach-exynos/include/mach/dwmmc.h | 5 ++\n>> drivers/mmc/exynos_dw_mmc.c | 80 +++++++++++++++++++++++++++++++\n>> 2 files changed, 85 insertions(+)\n>> \n>> diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> index 4432deedef7..50081326c25 100644\n>> --- a/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> @@ -15,6 +15,11 @@\n>> #define DWMCI_SET_DRV_CLK(x)\t\t((x) << 16)\n>> #define DWMCI_SET_DIV_RATIO(x)\t\t((x) << 24)\n>> \n>> +/* HS400 Related Registers */\n>> +#define DWMCI_HS400_DQS_EN\t\t0x180\n>> +#define DWMCI_HS400_ASYNC_FIFO_CTRL\t0x184\n>> +#define DWMCI_HS400_DLINE_CTRL\t\t0x188\n>> +\n>> /* Protector Register */\n>> #define DWMCI_EMMCP_BASE\t\t0x1000\n>> #define EMMCP_MPSECURITY\t\t(DWMCI_EMMCP_BASE + 0x0010)\n>> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c\n>> index 7ccd113bd79..d5e90a9bd5c 100644\n>> --- a/drivers/mmc/exynos_dw_mmc.c\n>> +++ b/drivers/mmc/exynos_dw_mmc.c\n>> @@ -8,6 +8,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> #include \n>> #include \n>> #include \n>> @@ -30,6 +31,14 @@\n>> #define CLKSEL_UP_SAMPLE(x, y)\t\t(((x) & ~CLKSEL_CCLK_SAMPLE(7)) | \\\n>> \t\t\t\t\t CLKSEL_CCLK_SAMPLE(y))\n>> \n>> +/* RCLK_EN register defines */\n>> +#define DATA_STROBE_EN\t\t\tBIT(0)\n>> +#define AXI_NON_BLOCKING_WR\tBIT(7)\n>> +\n>> +/* DLINE_CTRL register defines */\n>> +#define DQS_CTRL_RD_DELAY(x, y)\t\t(((x) & ~0x3FF) | ((y) & 0x3FF))\n>> +#define DQS_CTRL_GET_RD_DELAY(x)\t((x) & 0x3FF)\n>> +\n>> /**\n>> * DOC: Quirk flags for different Exynos DW MMC blocks\n>> *\n>> @@ -71,6 +80,11 @@ struct dwmci_exynos_priv_data {\n>> \tstruct clk clk;\n>> \tu32 sdr_timing;\n>> \tu32 ddr_timing;\n>> +\tu32 hs400_timing;\n>> +\tu32 tuned_sample;\n>> +\tu32 dqs_delay;\n>> +\tu32 saved_dqs_en;\n>> +\tu32 saved_strobe_ctrl;\n>> \tconst struct exynos_dwmmc_variant *chip;\n>> };\n>> \n>> @@ -162,6 +176,27 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)\n>> \t\t\t\t& DWMCI_DIVRATIO_MASK) + 1;\n>> }\n>> \n>> +static void exynos_config_hs400(struct dwmci_host *host, enum bus_mode mode)\n>> +{\n>> +\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n>> +\tu32 dqs, strobe;\n>> +\n>> +\tdqs = priv->saved_dqs_en;\n>> +\tstrobe = priv->saved_strobe_ctrl;\n>> +\n>> +\tswitch (mode) {\n>> +\tcase MMC_HS_400:\n>> +\t\tdqs |= DATA_STROBE_EN;\n>> +\t\tstrobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);\n>> +\t\tbreak;\n>> +\tdefault:\n>> +\t\tdqs &= ~DATA_STROBE_EN;\n>> +\t}\n>> +\n>> +\tdwmci_writel(host, DWMCI_HS400_DQS_EN, dqs);\n>> +\tdwmci_writel(host, DWMCI_HS400_DLINE_CTRL, strobe);\n>> +}\n>> +\n>> /* Configure CLKSEL register with chosen timing values */\n>> static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> {\n>> @@ -170,6 +205,9 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> \tu32 timing;\n>> \n>> \tswitch (host->mmc->selected_mode) {\n>> +\tcase MMC_HS_400:\n>> +\t\ttiming = CLKSEL_UP_SAMPLE(priv->hs400_timing, priv->tuned_sample);\n>> +\t\tbreak;\n>> \tcase MMC_DDR_52:\n>> \t\ttiming = priv->ddr_timing;\n>> \t\tbreak;\n>> @@ -186,6 +224,8 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> \n>> \tdwmci_writel(host, priv->chip->clksel, timing);\n>> \n>> +\texynos_config_hs400(host, host->mmc->selected_mode);\n>> +\n>\n> This breaks emmc in Linux for existing devices without hs400 support:\n> exynos_config_hs400 is run no matter if the dt has the hs400\n> parameters, meaning 0x0 is written to DWMCI_HS400_DQS_EN and\n> DWMCI_HS400_DLINE_CTRL. U-boot does not seem to care, it loads the\n> kernel and initramfs without issues, but Linux later gives errors:\n\nIs it that the same defconfig is used for two devices, one with and one\nwithout HS400 support? If that's the case, guarding the call with\nHS400_SUPPORT config options won't be a real fix.\n\nmmc_of_parse() in mmc-uclass.h seems promising, this needs to be\nintegrated with dwmci_setup_cfg() in dw_mmc.c, and this change _may_ be\nregressive in nature, so I may also need to add some safety guards for\nthis.\n\nI will thus add this patch in the next rev. Would you be up to test the patch\nfor the concerned devices too?\n\n>\n> ```\n> [ 20.741025] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)\n> [ 20.886686] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n> [ 20.895138] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)\n> [ 20.905990] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n> [ 20.914988] mmc_host mmc0: Bus speed (slot 0) = 400000000Hz (slot req 200000000Hz, actual 200000000HZ div = 1)\n> [ 21.099546] I/O error, dev mmcblk0, sector 1000001 op 0x1:(WRITE) flags 0x800 phys_seg 16 prio class 2\n> [ 21.099853] I/O error, dev mmcblk0, sector 1000825 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> [ 21.107443] Buffer I/O error on dev mmcblk0p2, logical block 0, lost async page write\n> [ 21.107473] Buffer I/O error on dev mmcblk0p2, logical block 1, lost async page write\n> [ 21.116657] Buffer I/O error on dev mmcblk0p2, logical block 824, lost async page write\n> [ 21.124408] Buffer I/O error on dev mmcblk0p2, logical block 2, lost async page write\n> [ 21.132206] Buffer I/O error on dev mmcblk0p2, logical block 825, lost async page write\n> [ 21.140178] Buffer I/O error on dev mmcblk0p2, logical block 3, lost async page write\n> [ 21.147973] Buffer I/O error on dev mmcblk0p2, logical block 826, lost async page write\n> [ 21.155960] Buffer I/O error on dev mmcblk0p2, logical block 4, lost async page write\n> [ 21.163749] Buffer I/O error on dev mmcblk0p2, logical block 827, lost async page write\n> [ 21.171720] Buffer I/O error on dev mmcblk0p2, logical block 5, lost async page write\n> [ 21.200708] I/O error, dev mmcblk0, sector 1000873 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> [ 21.201043] I/O error, dev mmcblk0, sector 1000929 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> [ 21.218287] I/O error, dev mmcblk0, sector 1000945 op 0x1:(WRITE) flags 0x800 phys_seg 80 prio class 2\n> [ 21.218623] I/O error, dev mmcblk0, sector 1001033 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n> [ 21.236813] I/O error, dev mmcblk0, sector 1001097 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> [ 21.237146] I/O error, dev mmcblk0, sector 1001121 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n> [ 21.255370] I/O error, dev mmcblk0, sector 1001161 op 0x1:(WRITE) flags 0x800 phys_seg 56 prio class 2\n> [ 21.256253] I/O error, dev mmcblk0, sector 1001249 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> ```\n>\n> Specifically it seems to be writing 0x0 to DWMCI_HS400_DQS_EN that is\n> the issue, if I comment out that line it works also for my odroid-xu4\n> in non-hs400 mode.\n>\n> Tested on odroid-xu4 with odroid-xu3_defconfig after applying the\n> entire series, without any other changes.\n>\n> Best regards,\n> Henrik Grimler","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=disroot.org header.i=@disroot.org header.a=rsa-sha256\n header.s=mail header.b=TO/UQiYk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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bh=qawlnzyBSBMS2JuYctE7lJOpfCOFHtpFRKp0Y5brhe4=;\n h=Date:To:Cc:Subject:From:References:In-Reply-To;\n b=TO/UQiYkvDK74V2JcqdOOZQip1jZxJ2NifyWLOpdZZ68Hhl+XcWwCRTFj/iV2HSdU\n tBnozJnJpuSH5aWeZtS/FSWNypYSK2QRXfwlaZy8ncBaEKbSeDjTvjCOFO9Zvh/LTA\n PyjT1JrnzY+ZBaIVbfMiUJVj9U2r6U/qLN5AFemNK6rcY/Uk1axwD5kqrhIDbN47ht\n b49fnHhE48Lk853mig7Zxe/riNmsXDZKocnoY+Tu/+16jA/2pQ4y0va956K4FaQNpZ\n QF3TZZSaTpKUOOHj0KKsPEeVQaHxWTHwbIPqIkJnPog+n4Z1abC+LPjRBPJwOibjG7\n l770x6QV74GRw==","Mime-Version":"1.0","Content-Transfer-Encoding":"quoted-printable","Content-Type":"text/plain; charset=UTF-8","Date":"Fri, 01 May 2026 01:11:29 +0530","Message-Id":"","To":"\"Henrik Grimler\" , \"Kaustabh Chakraborty\"\n ","Cc":"\"Peng Fan\" , , \"Minkyu Kang\"\n , \"Tom Rini\" , \"Jaehoon Chung\"\n , \"Anand Moon\" , \"Sam\n Protsenko\" , \"Lukas Timmermann\"\n ","Subject":"Re: [PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for\n HS400 support","From":"\"Kaustabh Chakraborty\" ","References":"<20260427-dwmmc-exynos-hs400-es-v1-0-3495df40a9ac@disroot.org>\n <20260427-dwmmc-exynos-hs400-es-v1-1-3495df40a9ac@disroot.org>\n <20260430172638.GA17167@localhost>","In-Reply-To":"<20260430172638.GA17167@localhost>","X-Mailman-Approved-At":"Thu, 30 Apr 2026 21:54:39 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3685036,"web_url":"http://patchwork.ozlabs.org/comment/3685036/","msgid":"<20260501065840.GA13244@grimfrac.localdomain>","list_archive_url":null,"date":"2026-05-01T06:58:40","subject":"Re: [PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for\n HS400 support","submitter":{"id":83221,"url":"http://patchwork.ozlabs.org/api/people/83221/","name":"Henrik Grimler","email":"henrik@grimler.se"},"content":"Hi Kaustabh,\n\nOn Fri, May 01, 2026 at 01:11:29AM +0530, Kaustabh Chakraborty wrote:\n> On 2026-04-30 19:26 +02:00, Henrik Grimler wrote:\n> > Hi Kaustabh,\n> >\n> > On Mon, Apr 27, 2026 at 11:22:49AM +0530, Kaustabh Chakraborty wrote:\n> >> HS400 support was added, but configuration necessary for HS400 support\n> >> was left out. Add necessary changes, which includes:\n> >> - Device tree properties, such as \"samsung,dw-mshc-hs400-timing\" and\n> >> \"samsung,read-strobe-delay\", which function as per dt-bindings.\n> >> - Registers related to HS400, which are necessary to enable HS400+ support.\n> >> - Appropriate timing tunings for the HS400 mode.\n> >> \n> >> Note that these changes are loosely based off of its Linux kernel\n> >> counterpart.\n> >> \n> >> Fixes: bbe3b9fa0922 (\"mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes\")\n> >> Signed-off-by: Kaustabh Chakraborty \n> >> ---\n> >> arch/arm/mach-exynos/include/mach/dwmmc.h | 5 ++\n> >> drivers/mmc/exynos_dw_mmc.c | 80 +++++++++++++++++++++++++++++++\n> >> 2 files changed, 85 insertions(+)\n> >> \n> >> diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h\n> >> index 4432deedef7..50081326c25 100644\n> >> --- a/arch/arm/mach-exynos/include/mach/dwmmc.h\n> >> +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h\n> >> @@ -15,6 +15,11 @@\n> >> #define DWMCI_SET_DRV_CLK(x)\t\t((x) << 16)\n> >> #define DWMCI_SET_DIV_RATIO(x)\t\t((x) << 24)\n> >> \n> >> +/* HS400 Related Registers */\n> >> +#define DWMCI_HS400_DQS_EN\t\t0x180\n> >> +#define DWMCI_HS400_ASYNC_FIFO_CTRL\t0x184\n> >> +#define DWMCI_HS400_DLINE_CTRL\t\t0x188\n> >> +\n> >> /* Protector Register */\n> >> #define DWMCI_EMMCP_BASE\t\t0x1000\n> >> #define EMMCP_MPSECURITY\t\t(DWMCI_EMMCP_BASE + 0x0010)\n> >> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c\n> >> index 7ccd113bd79..d5e90a9bd5c 100644\n> >> --- a/drivers/mmc/exynos_dw_mmc.c\n> >> +++ b/drivers/mmc/exynos_dw_mmc.c\n> >> @@ -8,6 +8,7 @@\n> >> #include \n> >> #include \n> >> #include \n> >> +#include \n> >> #include \n> >> #include \n> >> #include \n> >> @@ -30,6 +31,14 @@\n> >> #define CLKSEL_UP_SAMPLE(x, y)\t\t(((x) & ~CLKSEL_CCLK_SAMPLE(7)) | \\\n> >> \t\t\t\t\t CLKSEL_CCLK_SAMPLE(y))\n> >> \n> >> +/* RCLK_EN register defines */\n> >> +#define DATA_STROBE_EN\t\t\tBIT(0)\n> >> +#define AXI_NON_BLOCKING_WR\tBIT(7)\n> >> +\n> >> +/* DLINE_CTRL register defines */\n> >> +#define DQS_CTRL_RD_DELAY(x, y)\t\t(((x) & ~0x3FF) | ((y) & 0x3FF))\n> >> +#define DQS_CTRL_GET_RD_DELAY(x)\t((x) & 0x3FF)\n> >> +\n> >> /**\n> >> * DOC: Quirk flags for different Exynos DW MMC blocks\n> >> *\n> >> @@ -71,6 +80,11 @@ struct dwmci_exynos_priv_data {\n> >> \tstruct clk clk;\n> >> \tu32 sdr_timing;\n> >> \tu32 ddr_timing;\n> >> +\tu32 hs400_timing;\n> >> +\tu32 tuned_sample;\n> >> +\tu32 dqs_delay;\n> >> +\tu32 saved_dqs_en;\n> >> +\tu32 saved_strobe_ctrl;\n> >> \tconst struct exynos_dwmmc_variant *chip;\n> >> };\n> >> \n> >> @@ -162,6 +176,27 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)\n> >> \t\t\t\t& DWMCI_DIVRATIO_MASK) + 1;\n> >> }\n> >> \n> >> +static void exynos_config_hs400(struct dwmci_host *host, enum bus_mode mode)\n> >> +{\n> >> +\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n> >> +\tu32 dqs, strobe;\n> >> +\n> >> +\tdqs = priv->saved_dqs_en;\n> >> +\tstrobe = priv->saved_strobe_ctrl;\n> >> +\n> >> +\tswitch (mode) {\n> >> +\tcase MMC_HS_400:\n> >> +\t\tdqs |= DATA_STROBE_EN;\n> >> +\t\tstrobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);\n> >> +\t\tbreak;\n> >> +\tdefault:\n> >> +\t\tdqs &= ~DATA_STROBE_EN;\n> >> +\t}\n> >> +\n> >> +\tdwmci_writel(host, DWMCI_HS400_DQS_EN, dqs);\n> >> +\tdwmci_writel(host, DWMCI_HS400_DLINE_CTRL, strobe);\n> >> +}\n> >> +\n> >> /* Configure CLKSEL register with chosen timing values */\n> >> static int exynos_dwmci_clksel(struct dwmci_host *host)\n> >> {\n> >> @@ -170,6 +205,9 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n> >> \tu32 timing;\n> >> \n> >> \tswitch (host->mmc->selected_mode) {\n> >> +\tcase MMC_HS_400:\n> >> +\t\ttiming = CLKSEL_UP_SAMPLE(priv->hs400_timing, priv->tuned_sample);\n> >> +\t\tbreak;\n> >> \tcase MMC_DDR_52:\n> >> \t\ttiming = priv->ddr_timing;\n> >> \t\tbreak;\n> >> @@ -186,6 +224,8 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n> >> \n> >> \tdwmci_writel(host, priv->chip->clksel, timing);\n> >> \n> >> +\texynos_config_hs400(host, host->mmc->selected_mode);\n> >> +\n> >\n> > This breaks emmc in Linux for existing devices without hs400 support:\n> > exynos_config_hs400 is run no matter if the dt has the hs400\n> > parameters, meaning 0x0 is written to DWMCI_HS400_DQS_EN and\n> > DWMCI_HS400_DLINE_CTRL. U-boot does not seem to care, it loads the\n> > kernel and initramfs without issues, but Linux later gives errors:\n> \n> Is it that the same defconfig is used for two devices, one with and one\n> without HS400 support? If that's the case, guarding the call with\n> HS400_SUPPORT config options won't be a real fix.\n\nA family of devices are using the same defconfig. I assume the\nhardware in all of them supports hs400, but at the moment only one\ndevice seems to be configured to use hs400 _in Linux_, and none in\nu-boot.\n\nAdding a config guard around exynos_config_hs400() would probably\nwork. I see Linux uses a check like\nif (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420)\ninstead.\n\n> mmc_of_parse() in mmc-uclass.h seems promising, this needs to be\n> integrated with dwmci_setup_cfg() in dw_mmc.c, and this change _may_ be\n> regressive in nature, so I may also need to add some safety guards for\n> this.\n> \n> I will thus add this patch in the next rev. Would you be up to test the patch\n> for the concerned devices too?\n\nYeah I can test on these older devices.\n\nBest regards,\nHenrik Grimler\n\n> >\n> > ```\n> > [ 20.741025] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)\n> > [ 20.886686] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n> > [ 20.895138] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)\n> > [ 20.905990] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n> > [ 20.914988] mmc_host mmc0: Bus speed (slot 0) = 400000000Hz (slot req 200000000Hz, actual 200000000HZ div = 1)\n> > [ 21.099546] I/O error, dev mmcblk0, sector 1000001 op 0x1:(WRITE) flags 0x800 phys_seg 16 prio class 2\n> > [ 21.099853] I/O error, dev mmcblk0, sector 1000825 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> > [ 21.107443] Buffer I/O error on dev mmcblk0p2, logical block 0, lost async page write\n> > [ 21.107473] Buffer I/O error on dev mmcblk0p2, logical block 1, lost async page write\n> > [ 21.116657] Buffer I/O error on dev mmcblk0p2, logical block 824, lost async page write\n> > [ 21.124408] Buffer I/O error on dev mmcblk0p2, logical block 2, lost async page write\n> > [ 21.132206] Buffer I/O error on dev mmcblk0p2, logical block 825, lost async page write\n> > [ 21.140178] Buffer I/O error on dev mmcblk0p2, logical block 3, lost async page write\n> > [ 21.147973] Buffer I/O error on dev mmcblk0p2, logical block 826, lost async page write\n> > [ 21.155960] Buffer I/O error on dev mmcblk0p2, logical block 4, lost async page write\n> > [ 21.163749] Buffer I/O error on dev mmcblk0p2, logical block 827, lost async page write\n> > [ 21.171720] Buffer I/O error on dev mmcblk0p2, logical block 5, lost async page write\n> > [ 21.200708] I/O error, dev mmcblk0, sector 1000873 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> > [ 21.201043] I/O error, dev mmcblk0, sector 1000929 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> > [ 21.218287] I/O error, dev mmcblk0, sector 1000945 op 0x1:(WRITE) flags 0x800 phys_seg 80 prio class 2\n> > [ 21.218623] I/O error, dev mmcblk0, sector 1001033 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n> > [ 21.236813] I/O error, dev mmcblk0, sector 1001097 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> > [ 21.237146] I/O error, dev mmcblk0, sector 1001121 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n> > [ 21.255370] I/O error, dev mmcblk0, sector 1001161 op 0x1:(WRITE) flags 0x800 phys_seg 56 prio class 2\n> > [ 21.256253] I/O error, dev mmcblk0, sector 1001249 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n> > ```\n> >\n> > Specifically it seems to be writing 0x0 to DWMCI_HS400_DQS_EN that is\n> > the issue, if I comment out that line it works also for my odroid-xu4\n> > in non-hs400 mode.\n> >\n> > Tested on odroid-xu4 with odroid-xu3_defconfig after applying the\n> > entire series, without any other changes.\n> >\n> > Best regards,\n> > Henrik Grimler\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Migadu-Flow":"FLOW_OUT","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3685115,"web_url":"http://patchwork.ozlabs.org/comment/3685115/","msgid":"","list_archive_url":null,"date":"2026-05-01T09:02:50","subject":"Re: [PATCH 1/4] mmc: exynos_dw_mmc: add proper init sequence for\n HS400 support","submitter":{"id":88698,"url":"http://patchwork.ozlabs.org/api/people/88698/","name":"Kaustabh Chakraborty","email":"kauschluss@disroot.org"},"content":"On 2026-05-01 08:58 +02:00, Henrik Grimler wrote:\n> Hi Kaustabh,\n>\n> On Fri, May 01, 2026 at 01:11:29AM +0530, Kaustabh Chakraborty wrote:\n>> On 2026-04-30 19:26 +02:00, Henrik Grimler wrote:\n>> > Hi Kaustabh,\n>> >\n>> > On Mon, Apr 27, 2026 at 11:22:49AM +0530, Kaustabh Chakraborty wrote:\n>> >> HS400 support was added, but configuration necessary for HS400 support\n>> >> was left out. Add necessary changes, which includes:\n>> >> - Device tree properties, such as \"samsung,dw-mshc-hs400-timing\" and\n>> >> \"samsung,read-strobe-delay\", which function as per dt-bindings.\n>> >> - Registers related to HS400, which are necessary to enable HS400+ support.\n>> >> - Appropriate timing tunings for the HS400 mode.\n>> >> \n>> >> Note that these changes are loosely based off of its Linux kernel\n>> >> counterpart.\n>> >> \n>> >> Fixes: bbe3b9fa0922 (\"mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes\")\n>> >> Signed-off-by: Kaustabh Chakraborty \n>> >> ---\n>> >> arch/arm/mach-exynos/include/mach/dwmmc.h | 5 ++\n>> >> drivers/mmc/exynos_dw_mmc.c | 80 +++++++++++++++++++++++++++++++\n>> >> 2 files changed, 85 insertions(+)\n>> >> \n>> >> diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> >> index 4432deedef7..50081326c25 100644\n>> >> --- a/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> >> +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h\n>> >> @@ -15,6 +15,11 @@\n>> >> #define DWMCI_SET_DRV_CLK(x)\t\t((x) << 16)\n>> >> #define DWMCI_SET_DIV_RATIO(x)\t\t((x) << 24)\n>> >> \n>> >> +/* HS400 Related Registers */\n>> >> +#define DWMCI_HS400_DQS_EN\t\t0x180\n>> >> +#define DWMCI_HS400_ASYNC_FIFO_CTRL\t0x184\n>> >> +#define DWMCI_HS400_DLINE_CTRL\t\t0x188\n>> >> +\n>> >> /* Protector Register */\n>> >> #define DWMCI_EMMCP_BASE\t\t0x1000\n>> >> #define EMMCP_MPSECURITY\t\t(DWMCI_EMMCP_BASE + 0x0010)\n>> >> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c\n>> >> index 7ccd113bd79..d5e90a9bd5c 100644\n>> >> --- a/drivers/mmc/exynos_dw_mmc.c\n>> >> +++ b/drivers/mmc/exynos_dw_mmc.c\n>> >> @@ -8,6 +8,7 @@\n>> >> #include \n>> >> #include \n>> >> #include \n>> >> +#include \n>> >> #include \n>> >> #include \n>> >> #include \n>> >> @@ -30,6 +31,14 @@\n>> >> #define CLKSEL_UP_SAMPLE(x, y)\t\t(((x) & ~CLKSEL_CCLK_SAMPLE(7)) | \\\n>> >> \t\t\t\t\t CLKSEL_CCLK_SAMPLE(y))\n>> >> \n>> >> +/* RCLK_EN register defines */\n>> >> +#define DATA_STROBE_EN\t\t\tBIT(0)\n>> >> +#define AXI_NON_BLOCKING_WR\tBIT(7)\n>> >> +\n>> >> +/* DLINE_CTRL register defines */\n>> >> +#define DQS_CTRL_RD_DELAY(x, y)\t\t(((x) & ~0x3FF) | ((y) & 0x3FF))\n>> >> +#define DQS_CTRL_GET_RD_DELAY(x)\t((x) & 0x3FF)\n>> >> +\n>> >> /**\n>> >> * DOC: Quirk flags for different Exynos DW MMC blocks\n>> >> *\n>> >> @@ -71,6 +80,11 @@ struct dwmci_exynos_priv_data {\n>> >> \tstruct clk clk;\n>> >> \tu32 sdr_timing;\n>> >> \tu32 ddr_timing;\n>> >> +\tu32 hs400_timing;\n>> >> +\tu32 tuned_sample;\n>> >> +\tu32 dqs_delay;\n>> >> +\tu32 saved_dqs_en;\n>> >> +\tu32 saved_strobe_ctrl;\n>> >> \tconst struct exynos_dwmmc_variant *chip;\n>> >> };\n>> >> \n>> >> @@ -162,6 +176,27 @@ static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)\n>> >> \t\t\t\t& DWMCI_DIVRATIO_MASK) + 1;\n>> >> }\n>> >> \n>> >> +static void exynos_config_hs400(struct dwmci_host *host, enum bus_mode mode)\n>> >> +{\n>> >> +\tstruct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);\n>> >> +\tu32 dqs, strobe;\n>> >> +\n>> >> +\tdqs = priv->saved_dqs_en;\n>> >> +\tstrobe = priv->saved_strobe_ctrl;\n>> >> +\n>> >> +\tswitch (mode) {\n>> >> +\tcase MMC_HS_400:\n>> >> +\t\tdqs |= DATA_STROBE_EN;\n>> >> +\t\tstrobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);\n>> >> +\t\tbreak;\n>> >> +\tdefault:\n>> >> +\t\tdqs &= ~DATA_STROBE_EN;\n>> >> +\t}\n>> >> +\n>> >> +\tdwmci_writel(host, DWMCI_HS400_DQS_EN, dqs);\n>> >> +\tdwmci_writel(host, DWMCI_HS400_DLINE_CTRL, strobe);\n>> >> +}\n>> >> +\n>> >> /* Configure CLKSEL register with chosen timing values */\n>> >> static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> >> {\n>> >> @@ -170,6 +205,9 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> >> \tu32 timing;\n>> >> \n>> >> \tswitch (host->mmc->selected_mode) {\n>> >> +\tcase MMC_HS_400:\n>> >> +\t\ttiming = CLKSEL_UP_SAMPLE(priv->hs400_timing, priv->tuned_sample);\n>> >> +\t\tbreak;\n>> >> \tcase MMC_DDR_52:\n>> >> \t\ttiming = priv->ddr_timing;\n>> >> \t\tbreak;\n>> >> @@ -186,6 +224,8 @@ static int exynos_dwmci_clksel(struct dwmci_host *host)\n>> >> \n>> >> \tdwmci_writel(host, priv->chip->clksel, timing);\n>> >> \n>> >> +\texynos_config_hs400(host, host->mmc->selected_mode);\n>> >> +\n>> >\n>> > This breaks emmc in Linux for existing devices without hs400 support:\n>> > exynos_config_hs400 is run no matter if the dt has the hs400\n>> > parameters, meaning 0x0 is written to DWMCI_HS400_DQS_EN and\n>> > DWMCI_HS400_DLINE_CTRL. U-boot does not seem to care, it loads the\n>> > kernel and initramfs without issues, but Linux later gives errors:\n>> \n>> Is it that the same defconfig is used for two devices, one with and one\n>> without HS400 support? If that's the case, guarding the call with\n>> HS400_SUPPORT config options won't be a real fix.\n>\n> A family of devices are using the same defconfig. I assume the\n> hardware in all of them supports hs400, but at the moment only one\n> device seems to be configured to use hs400 _in Linux_, and none in\n> u-boot.\n\nIt won't. If one of the devices supports HS400 and others don't (not\nspecifically in your case, but a general scenario), then the config\nwould have HS400 support enabled. As a result non-HS400 hardware would\nalso try to assume HS400.\n\n>\n> Adding a config guard around exynos_config_hs400() would probably\n> work. I see Linux uses a check like\n> if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420)\n> instead.\n>\n>> mmc_of_parse() in mmc-uclass.h seems promising, this needs to be\n>> integrated with dwmci_setup_cfg() in dw_mmc.c, and this change _may_ be\n>> regressive in nature, so I may also need to add some safety guards for\n>> this.\n>> \n>> I will thus add this patch in the next rev. Would you be up to test the patch\n>> for the concerned devices too?\n>\n> Yeah I can test on these older devices.\n>\n> Best regards,\n> Henrik Grimler\n>\n>> >\n>> > ```\n>> > [ 20.741025] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)\n>> > [ 20.886686] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n>> > [ 20.895138] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)\n>> > [ 20.905990] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)\n>> > [ 20.914988] mmc_host mmc0: Bus speed (slot 0) = 400000000Hz (slot req 200000000Hz, actual 200000000HZ div = 1)\n>> > [ 21.099546] I/O error, dev mmcblk0, sector 1000001 op 0x1:(WRITE) flags 0x800 phys_seg 16 prio class 2\n>> > [ 21.099853] I/O error, dev mmcblk0, sector 1000825 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n>> > [ 21.107443] Buffer I/O error on dev mmcblk0p2, logical block 0, lost async page write\n>> > [ 21.107473] Buffer I/O error on dev mmcblk0p2, logical block 1, lost async page write\n>> > [ 21.116657] Buffer I/O error on dev mmcblk0p2, logical block 824, lost async page write\n>> > [ 21.124408] Buffer I/O error on dev mmcblk0p2, logical block 2, lost async page write\n>> > [ 21.132206] Buffer I/O error on dev mmcblk0p2, logical block 825, lost async page write\n>> > [ 21.140178] Buffer I/O error on dev mmcblk0p2, logical block 3, lost async page write\n>> > [ 21.147973] Buffer I/O error on dev mmcblk0p2, logical block 826, lost async page write\n>> > [ 21.155960] Buffer I/O error on dev mmcblk0p2, logical block 4, lost async page write\n>> > [ 21.163749] Buffer I/O error on dev mmcblk0p2, logical block 827, lost async page write\n>> > [ 21.171720] Buffer I/O error on dev mmcblk0p2, logical block 5, lost async page write\n>> > [ 21.200708] I/O error, dev mmcblk0, sector 1000873 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n>> > [ 21.201043] I/O error, dev mmcblk0, sector 1000929 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n>> > [ 21.218287] I/O error, dev mmcblk0, sector 1000945 op 0x1:(WRITE) flags 0x800 phys_seg 80 prio class 2\n>> > [ 21.218623] I/O error, dev mmcblk0, sector 1001033 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n>> > [ 21.236813] I/O error, dev mmcblk0, sector 1001097 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n>> > [ 21.237146] I/O error, dev mmcblk0, sector 1001121 op 0x1:(WRITE) flags 0x800 phys_seg 24 prio class 2\n>> > [ 21.255370] I/O error, dev mmcblk0, sector 1001161 op 0x1:(WRITE) flags 0x800 phys_seg 56 prio class 2\n>> > [ 21.256253] I/O error, dev mmcblk0, sector 1001249 op 0x1:(WRITE) flags 0x800 phys_seg 8 prio class 2\n>> > ```\n>> >\n>> > Specifically it seems to be writing 0x0 to DWMCI_HS400_DQS_EN that is\n>> > the issue, if I comment out that line it works also for my odroid-xu4\n>> > in non-hs400 mode.\n>> >\n>> > Tested on odroid-xu4 with odroid-xu3_defconfig after applying the\n>> > entire series, without any other changes.\n>> >\n>> > Best regards,\n>> > Henrik Grimler\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=disroot.org header.i=@disroot.org header.a=rsa-sha256\n header.s=mail header.b=X+SLOhzM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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