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GET /api/1.1/patches/2228584/?format=api
{ "id": 2228584, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2228584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/f6734b9dad0050138676f11ecd14e9db1cf6b697.1777269009.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<f6734b9dad0050138676f11ecd14e9db1cf6b697.1777269009.git.nicolinc@nvidia.com>", "date": "2026-04-27T05:54:00", "name": "[v4,1/3] PCI: Allow ATS to be always on for CXL.cache capable devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "87a0c659fa12968d8456c9d228b28c20524ccba1", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/1.1/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/f6734b9dad0050138676f11ecd14e9db1cf6b697.1777269009.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 501574, "url": "http://patchwork.ozlabs.org/api/1.1/series/501574/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501574", "date": "2026-04-27T05:53:59", "name": "Allow ATS to be always on for certain ATS-capable devices", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/501574/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2228584/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2228584/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53201-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=A2oqmxFw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "<jgg@nvidia.com>, <will@kernel.org>, <robin.murphy@arm.com>,\n\t<bhelgaas@google.com>", "CC": "<joro@8bytes.org>, <praan@google.com>, <baolu.lu@linux.intel.com>,\n\t<kevin.tian@intel.com>, <miko.lenczewski@arm.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,\n\t<vsethi@nvidia.com>, <linux-cxl@vger.kernel.org>, <nirmoyd@nvidia.com>", "Subject": "[PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable\n devices", "Date": "Sun, 26 Apr 2026 22:54:00 -0700", "Message-ID": "\n <f6734b9dad0050138676f11ecd14e9db1cf6b697.1777269009.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1777269009.git.nicolinc@nvidia.com>", "References": "<cover.1777269009.git.nicolinc@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE31:EE_|SJ1PR12MB6217:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f8d4a61f-6617-45f6-adcd-08dea4217359", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\t15lFeq2Ea+IMJWLXoTo0RqiZywHftBsfN7oV312QnMSidbgUeVGvH/A2fYeyDMaUkjNgGjwh8zBMjD2guOHlFin2WcngGcFPeX1oXFnus47dpLVb3Tki4ns8VR+T8QIvYrHcMYoBU/F4mNMr+6EAHdwMD6OR7QSjl8ZEKeo9nhdMYvoyWf4JEt+Kf0o4GT4nNzO8gcBSULF3x1PPvtw1mn2sqY0FmNC0clm/pVNR851msRfEOvXyOaNwy/0luJhQlpVJBatcUwUOyCYcRlRUqyg8GILvJelTlwGcZimpO9DqMaun9F+3pnVxpcF9FxnC31Ya9EfQjawmBSMh2s6caTgSnqk93xL6i2uKcT1LLHpOHGzAa+V1sSA46V+nyN0lhxrceSTunG20dDy7ApZhvxq0QcD6I2WZY7IwfKr+VJXlxVT4HCcYE9oaldDh4Ez9Cz/2HPPRNnT42PQ20unAGy1cdYZ2kfuMYUbHc7NdJ9jsoIJDgh7KLU3UpLc+JQbSHBUUp6o5VnpP8FRHiesvzDB7OUPoMULbhZd+uY8mRSleu02fuELYQPdlp78FfiFBZ2/NAhut0kzWz0sGikKLJU8MWoYxR10JACY+2kjLEucFDRYLIYOZEkH7YlQhC0qCYCUTrZGvvsML2x15UAXwHDlvKo7X0EN20oHSje3K6YET9JkzVuNc7nnFRv7AIybG0++zCXZO6NZHuKzbiKnQSzf+KO8UfYUp6jK6m2x3llZiqMvnJkmWj12qMHQK9bgVun1d/RiG/FcEQRhU8FIGbw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tseVfNbcnwrkSFIDUCqBZfuZqECxAjN9aCMN1w+GM9RXLySn/OCuR7WDcnYQC1tjdFUUGzG69Q5jYzth65M4etFr0nSmbgaCRwkKlEBLuFXi7ZsMBdidJKpw6bqAVpBC/pTgCkNWgQnnljEkfM6HhB7rzxV3VZC8oRjXLodHsQUzZ0ffo495qC6KZYwQINRJ1SPQodbNKDKwe+SCRHGNkVPFQ+7yLo8PXemp/GpW7piOglRnREHQpIlDO5Os3U1gnDUKMaKd/mPm4ul4C+qQ5QBRQSXYvif1UQAAdN89Z9iOKhU9sHro18KPNysZ8YK9yccbfkKeRJkmkj02EmQwWHW5+o6Qhs20ox865jLtYJ3T6kL/p72XND5j1Wne/L1Rl6fg6tw0J/cLUFb/Mj4/VAi6GXVFt+ebIyinqhB51Cwl47ZxesJZ6SIcd8iOWbzsx", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 05:54:30.8024\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f8d4a61f-6617-45f6-adcd-08dea4217359", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE31.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6217" }, "content": "Controlled by the IOMMU driver, ATS is usually enabled \"on demand\" when a\ngiven PASID on a device is attached to an I/O page table. This is working\neven when a device has no translation on its RID (i.e., the RID is IOMMU\nbypassed).\n\nHowever, certain PCIe devices require non-PASID ATS on their RID even when\nthe RID is IOMMU bypassed. Call this \"always on\".\n\nFor example, CXL spec r4.0 notes in sec 3.2.5.13 Memory Type on CXL.cache:\n \"To source requests on CXL.cache, devices need to get the Host Physical\n Address (HPA) from the Host by means of an ATS request on CXL.io.\"\n\nIn other words, the CXL.cache capability requires ATS; otherwise, it can't\naccess host physical memory.\n\nIntroduce a new pci_ats_always_on() helper for the IOMMU driver to scan a\nPCI device and shift ATS policies between \"on demand\" and \"always on\".\n\nAdd the support for CXL.cache devices first. Pre-CXL devices will be added\nin quirks.c file.\n\nNote that pci_ats_always_on() validates against pci_ats_supported(), so we\nensure that untrusted devices (e.g. external ports) will not be always on.\nThis maintains the existing ATS security policy regarding potential side-\nchannel attacks via ATS.\n\nCc: linux-cxl@vger.kernel.org\nSuggested-by: Vikram Sethi <vsethi@nvidia.com>\nSuggested-by: Jason Gunthorpe <jgg@nvidia.com>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\nReviewed-by: Jason Gunthorpe <jgg@nvidia.com>\nReviewed-by: Kevin Tian <kevin.tian@intel.com>\nTested-by: Nirmoy Das <nirmoyd@nvidia.com>\nAcked-by: Nirmoy Das <nirmoyd@nvidia.com>\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\n---\n include/linux/pci-ats.h | 3 +++\n include/uapi/linux/pci_regs.h | 1 +\n drivers/pci/ats.c | 43 +++++++++++++++++++++++++++++++++++\n 3 files changed, 47 insertions(+)", "diff": "diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h\nindex 75c6c86cf09dc..d14ba727d38b3 100644\n--- a/include/linux/pci-ats.h\n+++ b/include/linux/pci-ats.h\n@@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);\n void pci_disable_ats(struct pci_dev *dev);\n int pci_ats_queue_depth(struct pci_dev *dev);\n int pci_ats_page_aligned(struct pci_dev *dev);\n+bool pci_ats_always_on(struct pci_dev *dev);\n #else /* CONFIG_PCI_ATS */\n static inline bool pci_ats_supported(struct pci_dev *d)\n { return false; }\n@@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)\n { return -ENODEV; }\n static inline int pci_ats_page_aligned(struct pci_dev *dev)\n { return 0; }\n+static inline bool pci_ats_always_on(struct pci_dev *dev)\n+{ return false; }\n #endif /* CONFIG_PCI_ATS */\n \n #ifdef CONFIG_PCI_PRI\ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350d..6ac45be1008b8 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1349,6 +1349,7 @@\n /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */\n #define PCI_DVSEC_CXL_DEVICE\t\t\t\t0\n #define PCI_DVSEC_CXL_CAP\t\t\t\t0xA\n+#define PCI_DVSEC_CXL_CACHE_CAPABLE\t\t\t_BITUL(0)\n #define PCI_DVSEC_CXL_MEM_CAPABLE\t\t\t_BITUL(2)\n #define PCI_DVSEC_CXL_HDM_COUNT\t\t\t__GENMASK(5, 4)\n #define PCI_DVSEC_CXL_CTRL\t\t\t\t0xC\ndiff --git a/drivers/pci/ats.c b/drivers/pci/ats.c\nindex ec6c8dbdc5e9c..fc871858b65bc 100644\n--- a/drivers/pci/ats.c\n+++ b/drivers/pci/ats.c\n@@ -205,6 +205,49 @@ int pci_ats_page_aligned(struct pci_dev *pdev)\n \treturn 0;\n }\n \n+/*\n+ * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on\n+ * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host\n+ * by means of an ATS request on CXL.io.\n+ *\n+ * In other words, CXL.cache devices cannot access host physical memory without\n+ * ATS.\n+ */\n+static bool pci_cxl_ats_always_on(struct pci_dev *pdev)\n+{\n+\tint offset;\n+\tu16 cap;\n+\n+\toffset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n+\tif (!offset)\n+\t\treturn false;\n+\n+\tif (pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap))\n+\t\treturn false;\n+\n+\treturn cap & PCI_DVSEC_CXL_CACHE_CAPABLE;\n+}\n+\n+/**\n+ * pci_ats_always_on - Whether the PCI device requires ATS to be always enabled\n+ * @pdev: the PCI device\n+ *\n+ * Returns true, if the PCI device requires ATS for basic functional operation.\n+ */\n+bool pci_ats_always_on(struct pci_dev *pdev)\n+{\n+\tif (pci_ats_disabled() || !pci_ats_supported(pdev))\n+\t\treturn false;\n+\n+\t/* A VF inherits its PF's requirement for ATS function */\n+\tif (pdev->is_virtfn)\n+\t\tpdev = pci_physfn(pdev);\n+\n+\treturn pci_cxl_ats_always_on(pdev);\n+}\n+EXPORT_SYMBOL_GPL(pci_ats_always_on);\n+\n #ifdef CONFIG_PCI_PRI\n void pci_pri_init(struct pci_dev *pdev)\n {\n", "prefixes": [ "v4", "1/3" ] }