[{"id":3682824,"web_url":"http://patchwork.ozlabs.org/comment/3682824/","msgid":"<2efed1ea-e373-41d0-bc37-4adac8378169@intel.com>","list_archive_url":null,"date":"2026-04-27T16:31:39","subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 4/26/26 10:54 PM, Nicolin Chen wrote:\n> Controlled by the IOMMU driver, ATS is usually enabled \"on demand\" when a\n> given PASID on a device is attached to an I/O page table. This is working\n> even when a device has no translation on its RID (i.e., the RID is IOMMU\n> bypassed).\n> \n> However, certain PCIe devices require non-PASID ATS on their RID even when\n> the RID is IOMMU bypassed. Call this \"always on\".\n> \n> For example, CXL spec r4.0 notes in sec 3.2.5.13 Memory Type on CXL.cache:\n> \"To source requests on CXL.cache, devices need to get the Host Physical\n> Address (HPA) from the Host by means of an ATS request on CXL.io.\"\n> \n> In other words, the CXL.cache capability requires ATS; otherwise, it can't\n> access host physical memory.\n> \n> Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a\n> PCI device and shift ATS policies between \"on demand\" and \"always on\".\n> \n> Add the support for CXL.cache devices first. Pre-CXL devices will be added\n> in quirks.c file.\n> \n> Note that pci_ats_always_on() validates against pci_ats_supported(), so we\n> ensure that untrusted devices (e.g. external ports) will not be always on.\n> This maintains the existing ATS security policy regarding potential side-\n> channel attacks via ATS.\n> \n> Cc: linux-cxl@vger.kernel.org\n> Suggested-by: Vikram Sethi \n> Suggested-by: Jason Gunthorpe \n> Reviewed-by: Jonathan Cameron \n> Reviewed-by: Jason Gunthorpe \n> Reviewed-by: Kevin Tian \n> Tested-by: Nirmoy Das \n> Acked-by: Nirmoy Das \n> Signed-off-by: Nicolin Chen \n\nReviewed-by: Dave Jiang \n\n\n> ---\n> include/linux/pci-ats.h | 3 +++\n> include/uapi/linux/pci_regs.h | 1 +\n> drivers/pci/ats.c | 43 +++++++++++++++++++++++++++++++++++\n> 3 files changed, 47 insertions(+)\n> \n> diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h\n> index 75c6c86cf09dc..d14ba727d38b3 100644\n> --- a/include/linux/pci-ats.h\n> +++ b/include/linux/pci-ats.h\n> @@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);\n> void pci_disable_ats(struct pci_dev *dev);\n> int pci_ats_queue_depth(struct pci_dev *dev);\n> int pci_ats_page_aligned(struct pci_dev *dev);\n> +bool pci_ats_always_on(struct pci_dev *dev);\n> #else /* CONFIG_PCI_ATS */\n> static inline bool pci_ats_supported(struct pci_dev *d)\n> { return false; }\n> @@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)\n> { return -ENODEV; }\n> static inline int pci_ats_page_aligned(struct pci_dev *dev)\n> { return 0; }\n> +static inline bool pci_ats_always_on(struct pci_dev *dev)\n> +{ return false; }\n> #endif /* CONFIG_PCI_ATS */\n> \n> #ifdef CONFIG_PCI_PRI\n> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\n> index 14f634ab9350d..6ac45be1008b8 100644\n> --- a/include/uapi/linux/pci_regs.h\n> +++ b/include/uapi/linux/pci_regs.h\n> @@ -1349,6 +1349,7 @@\n> /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */\n> #define PCI_DVSEC_CXL_DEVICE\t\t\t\t0\n> #define PCI_DVSEC_CXL_CAP\t\t\t\t0xA\n> +#define PCI_DVSEC_CXL_CACHE_CAPABLE\t\t\t_BITUL(0)\n> #define PCI_DVSEC_CXL_MEM_CAPABLE\t\t\t_BITUL(2)\n> #define PCI_DVSEC_CXL_HDM_COUNT\t\t\t__GENMASK(5, 4)\n> #define PCI_DVSEC_CXL_CTRL\t\t\t\t0xC\n> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c\n> index ec6c8dbdc5e9c..fc871858b65bc 100644\n> --- a/drivers/pci/ats.c\n> +++ b/drivers/pci/ats.c\n> @@ -205,6 +205,49 @@ int pci_ats_page_aligned(struct pci_dev *pdev)\n> \treturn 0;\n> }\n> \n> +/*\n> + * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on\n> + * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host\n> + * by means of an ATS request on CXL.io.\n> + *\n> + * In other words, CXL.cache devices cannot access host physical memory without\n> + * ATS.\n> + */\n> +static bool pci_cxl_ats_always_on(struct pci_dev *pdev)\n> +{\n> +\tint offset;\n> +\tu16 cap;\n> +\n> +\toffset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n> +\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n> +\tif (!offset)\n> +\t\treturn false;\n> +\n> +\tif (pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap))\n> +\t\treturn false;\n> +\n> +\treturn cap & PCI_DVSEC_CXL_CACHE_CAPABLE;\n> +}\n> +\n> +/**\n> + * pci_ats_always_on - Whether the PCI device requires ATS to be always enabled\n> + * @pdev: the PCI device\n> + *\n> + * Returns true, if the PCI device requires ATS for basic functional operation.\n> + */\n> +bool pci_ats_always_on(struct pci_dev *pdev)\n> +{\n> +\tif (pci_ats_disabled() || !pci_ats_supported(pdev))\n> +\t\treturn false;\n> +\n> +\t/* A VF inherits its PF's requirement for ATS function */\n> +\tif (pdev->is_virtfn)\n> +\t\tpdev = pci_physfn(pdev);\n> +\n> +\treturn pci_cxl_ats_always_on(pdev);\n> +}\n> +EXPORT_SYMBOL_GPL(pci_ats_always_on);\n> +\n> #ifdef CONFIG_PCI_PRI\n> void pci_pri_init(struct pci_dev *pdev)\n> {","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=gmNEH+Mq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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a=\"78093619\"","E=Sophos;i=\"6.23,202,1770624000\";\n d=\"scan'208\";a=\"78093619\"","E=Sophos;i=\"6.23,202,1770624000\";\n d=\"scan'208\";a=\"271816236\""],"X-ExtLoop1":"1","Message-ID":"<2efed1ea-e373-41d0-bc37-4adac8378169@intel.com>","Date":"Mon, 27 Apr 2026 09:31:39 -0700","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","To":"Nicolin Chen , jgg@nvidia.com, will@kernel.org,\n robin.murphy@arm.com, bhelgaas@google.com","Cc":"joro@8bytes.org, praan@google.com, baolu.lu@linux.intel.com,\n kevin.tian@intel.com, miko.lenczewski@arm.com,\n linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n dan.j.williams@intel.com, jonathan.cameron@huawei.com, vsethi@nvidia.com,\n linux-cxl@vger.kernel.org, nirmoyd@nvidia.com","References":"\n ","Content-Language":"en-US","From":"Dave Jiang ","In-Reply-To":"\n ","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3684955,"web_url":"http://patchwork.ozlabs.org/comment/3684955/","msgid":"<69f3cc82926_3291a910039@djbw-dev.notmuch>","list_archive_url":null,"date":"2026-04-30T21:41:22","subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","submitter":{"id":93110,"url":"http://patchwork.ozlabs.org/api/people/93110/","name":"Dan Williams (nvidia)","email":"djbw@kernel.org"},"content":"Nicolin Chen wrote:\n> Controlled by the IOMMU driver, ATS is usually enabled \"on demand\" when a\n> given PASID on a device is attached to an I/O page table. This is working\n> even when a device has no translation on its RID (i.e., the RID is IOMMU\n> bypassed).\n> \n> However, certain PCIe devices require non-PASID ATS on their RID even when\n> the RID is IOMMU bypassed. Call this \"always on\".\n> \n> For example, CXL spec r4.0 notes in sec 3.2.5.13 Memory Type on CXL.cache:\n> \"To source requests on CXL.cache, devices need to get the Host Physical\n> Address (HPA) from the Host by means of an ATS request on CXL.io.\"\n> \n> In other words, the CXL.cache capability requires ATS; otherwise, it can't\n> access host physical memory.\n> \n> Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a\n> PCI device and shift ATS policies between \"on demand\" and \"always on\".\n> \n> Add the support for CXL.cache devices first. Pre-CXL devices will be added\n> in quirks.c file.\n> \n> Note that pci_ats_always_on() validates against pci_ats_supported(), so we\n> ensure that untrusted devices (e.g. external ports) will not be always on.\n> This maintains the existing ATS security policy regarding potential side-\n> channel attacks via ATS.\n> \n> Cc: linux-cxl@vger.kernel.org\n> Suggested-by: Vikram Sethi \n> Suggested-by: Jason Gunthorpe \n> Reviewed-by: Jonathan Cameron \n> Reviewed-by: Jason Gunthorpe \n> Reviewed-by: Kevin Tian \n> Tested-by: Nirmoy Das \n> Acked-by: Nirmoy Das \n> Signed-off-by: Nicolin Chen \n> ---\n> include/linux/pci-ats.h | 3 +++\n> include/uapi/linux/pci_regs.h | 1 +\n> drivers/pci/ats.c | 43 +++++++++++++++++++++++++++++++++++\n> 3 files changed, 47 insertions(+)\n> \n> diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h\n> index 75c6c86cf09dc..d14ba727d38b3 100644\n> --- a/include/linux/pci-ats.h\n> +++ b/include/linux/pci-ats.h\n> @@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);\n> void pci_disable_ats(struct pci_dev *dev);\n> int pci_ats_queue_depth(struct pci_dev *dev);\n> int pci_ats_page_aligned(struct pci_dev *dev);\n> +bool pci_ats_always_on(struct pci_dev *dev);\n> #else /* CONFIG_PCI_ATS */\n> static inline bool pci_ats_supported(struct pci_dev *d)\n> { return false; }\n> @@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)\n> { return -ENODEV; }\n> static inline int pci_ats_page_aligned(struct pci_dev *dev)\n> { return 0; }\n> +static inline bool pci_ats_always_on(struct pci_dev *dev)\n> +{ return false; }\n> #endif /* CONFIG_PCI_ATS */\n> \n> #ifdef CONFIG_PCI_PRI\n> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\n> index 14f634ab9350d..6ac45be1008b8 100644\n> --- a/include/uapi/linux/pci_regs.h\n> +++ b/include/uapi/linux/pci_regs.h\n> @@ -1349,6 +1349,7 @@\n> /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */\n> #define PCI_DVSEC_CXL_DEVICE\t\t\t\t0\n> #define PCI_DVSEC_CXL_CAP\t\t\t\t0xA\n> +#define PCI_DVSEC_CXL_CACHE_CAPABLE\t\t\t_BITUL(0)\n> #define PCI_DVSEC_CXL_MEM_CAPABLE\t\t\t_BITUL(2)\n> #define PCI_DVSEC_CXL_HDM_COUNT\t\t\t__GENMASK(5, 4)\n> #define PCI_DVSEC_CXL_CTRL\t\t\t\t0xC\n> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c\n> index ec6c8dbdc5e9c..fc871858b65bc 100644\n> --- a/drivers/pci/ats.c\n> +++ b/drivers/pci/ats.c\n> @@ -205,6 +205,49 @@ int pci_ats_page_aligned(struct pci_dev *pdev)\n> \treturn 0;\n> }\n> \n> +/*\n> + * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on\n> + * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host\n> + * by means of an ATS request on CXL.io.\n> + *\n> + * In other words, CXL.cache devices cannot access host physical memory without\n> + * ATS.\n> + */\n> +static bool pci_cxl_ats_always_on(struct pci_dev *pdev)\n> +{\n> +\tint offset;\n> +\tu16 cap;\n> +\n> +\toffset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n> +\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n> +\tif (!offset)\n> +\t\treturn false;\n> +\n> +\tif (pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap))\n> +\t\treturn false;\n> +\n> +\treturn cap & PCI_DVSEC_CXL_CACHE_CAPABLE;\n\nApologies for coming to this late and forgive me if the following has\nalready been asked and answered. Why not check for actual CXL.cache\nprotocol on the wire being present?\n\nI.e. replace pci_cxl_ats_always_on() with a pdev->is_cxl_cache and this\nincremental change (compile tested only):\n\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 2c4454583c11..45d87af4de63 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -483,7 +483,8 @@ struct pci_dev {\n \tunsigned int\tis_pciehp:1;\n \tunsigned int\tshpc_managed:1;\t\t/* SHPC owned by shpchp */\n \tunsigned int\tis_thunderbolt:1;\t/* Thunderbolt controller */\n-\tunsigned int\tis_cxl:1; /* Compute Express Link (CXL) */\n+\tunsigned int\tis_cxl_mem:1; /* Compute Express Link (CXL.mem) */\n+\tunsigned int\tis_cxl_cache:1; /* Compute Express Link (CXL.cache) */\n \t/*\n \t * Devices marked being untrusted are the ones that can potentially\n \t * execute DMA attacks and similar. They are typically connected\n@@ -809,7 +810,7 @@ static inline bool pci_is_display(struct pci_dev *pdev)\n \n static inline bool pcie_is_cxl(struct pci_dev *pci_dev)\n {\n-\treturn pci_dev->is_cxl;\n+\treturn pci_dev->is_cxl_mem || pci_dev->is_cxl_cache;\n }\n \n #define for_each_pci_bridge(dev, bus)\t\t\t\t\\\ndiff --git a/drivers/pci/probe.c b/drivers/pci/probe.c\nindex b63cd0c310bc..c01f0e8362f1 100644\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -1733,9 +1733,8 @@ static void set_pcie_cxl(struct pci_dev *dev)\n \tpci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS,\n \t\t\t &cap);\n \n-\tdev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap) ||\n-\t\tFIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n-\n+\tdev->is_cxl_cache = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap);\n+\tdev->is_cxl_mem = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n }\n \n static void set_pcie_untrusted(struct pci_dev *dev)","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=PsIch+r7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Why not check for actual CXL.cache\n> protocol on the wire being present?\n\nActually it would make the patch smaller. The thing is that this\nis_cxl property wasn't added when I started the series. So, it's\nnot using it. :)\n\n> @@ -1733,9 +1733,8 @@ static void set_pcie_cxl(struct pci_dev *dev)\n> \tpci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS,\n> \t\t\t &cap);\n> \n> -\tdev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap) ||\n> -\t\tFIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n> -\n> +\tdev->is_cxl_cache = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap);\n> +\tdev->is_cxl_mem = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n\nOne caveat is that:\n\nHere it checks the cap from:\n\tPCI_DVSEC_CXL_FLEXBUS_PORT_STATUS (0xE) via\n\t\tPCI_DVSEC_CXL_FLEXBUS_PORT_STATUS (0x7)\n\nOn the other hand, mine checks from:\n\tPCI_DVSEC_CXL_CAP (0xA) via\n\t\tPCI_DVSEC_CXL_DEVICE (0x0)\n\nThe spec mentions in 8.2.1.3.1 DVSEC Flex Bus Port Capability: \"\n Note: The Mem_Capable, IO_Capable, and Cache_Capable fields are\n also present in the DVSEC Flex Bus for the device [which is the\n legacy name for DVSEC 0x0]. This allows for future scalability\n where multiple devices, each with potentially different\n capabilities, may be populated behind a single Port.\n\"\n\nNot arguing that set_pcie_cxl() is wrong, but I am not sure if there\nwould be any side effect to rely on the \"legacy name\" over DVSEC 0x0.\n\nIs there any CXL expert who can help confirm?\n\nThanks!\nNicolin","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=mMLBm6kV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-53556-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"mMLBm6kV\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.201.58","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g69Nm3tglz1y1d\n\tfor ; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C","Date":"Thu, 30 Apr 2026 16:28:17 -0700","From":"Nicolin Chen ","To":"\"Dan Williams (nvidia)\" ","CC":", , ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","Subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","Message-ID":"","References":"\n \n <69f3cc82926_3291a910039@djbw-dev.notmuch>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Disposition":"inline","In-Reply-To":"<69f3cc82926_3291a910039@djbw-dev.notmuch>","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL6PEPF0001AB4B:EE_|CYYPR12MB8890:EE_","X-MS-Office365-Filtering-Correlation-Id":"23c0172c-c533-40ce-6828-08dea710366b","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700016|22082099003|18002099003|56012099003;","X-Microsoft-Antispam-Message-Info":"\n\tPa5XL9cSlKqDuP7K5er0RtlkfJlY6adNW4aBqIePvmlGlf2io5JMLUpDrZMmdQCur3kdjKuKsbw+2PBDs+vWOXxC7HDq6oqqUdS5Zf4lsh9yCoL1tgkKZ0Zk+CfpKPzqNYFkzrq2xjVgHcBbquKg3o8QJuKC7d5Pce/b5InXoVQ7UUw58WAVmGFA1j1KMC3fD/Sg9twNxRIf+5jgXNx4xq7ot/gEgiidMJwMmcMKrjhSuABFeCwkHSY5rbP3LZrxEUaEsKY/swl/TBkd9VJgoBKwutwRHBEMMr4hh6jw3NCPSQ0MP279pS+hbV67Tjc/6uzTB7dFchhVPoFJ7mLuyhLtlpFd7gGgZC32H36FKdTOYr/s9vW8VCf0K+q5E3M26QDnEqL5Zrbyt1u1eM3Xlzgwg/SalaFaO5A8feXpVicq18t9kRy5W7sXYkQShKQOCQw8VXqrFQu6MkFVbbVqaQZ3gbdxG6p9SppQdg+Ce9AgX7Ax+PuIgH7LzQaCgBmBpZZk3mr4PBcfze4eTUdhAJfMHFJUgN85lL7kO17xprhTqPKI9oagtLzBE81dJR+7NxosDbKEH1Cnb4CuskLgpEduiwXIHObnCBmR88VGCgSAQRkl6uqpv1MebVQBU/3uPJuxYXlC7QsTcrRex+XSdgssRX5RVRYkrc3ncp55Nh/hryWNXxV+mnoqzN9SC0NfIYbsFk4zSWuSqV+fCf4S/WD3DVhHFz5ZCnLog8eFES8=","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\t5QRvdu2tsMZaZN6LaVF5mfJKTnQpODLoriiYBkjWTsLktvO7JrdjeDySsyOcq+ZSbIbea/2/wMMiUp3qI/TmGNNtk0phWymDrrdWo4AJpPyKM5Mi1oZRe16vqbQ1AIOzxtEfhN+IOcZAwsqQ5M9Ka6FjB5Ddy+i7rreix7amE3EoJQywtaWvJGx5ZoGzAdgmpDcMZBAaRHGfpFPFAA0Aag5WcwpfPpElHrg6+viV9PBu7bskH2EXw3+rOuwHFDQ+p7so24CPzX2Jc8bGmEtGw/dFSMtvw3dX/jos/Ra2Ad4ncIv5ILL8egmbbzTOh/e367j/Bj500kSv7oSlgcRlcIcHTZVtwNBDBM82yNmqjrekRkbYDYO1mcOtL9tzY5HKdNU0z7ti4PE0fcjbuapGKbdA6cagOm54xxrC0Q4opB8n7e2kdOpNIl4pPvil7MNL","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"30 Apr 2026 23:28:40.5541\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 23c0172c-c533-40ce-6828-08dea710366b","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tBL6PEPF0001AB4B.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CYYPR12MB8890"}},{"id":3685243,"web_url":"http://patchwork.ozlabs.org/comment/3685243/","msgid":"<69f536ed263dd_3291a910017@djbw-dev.notmuch>","list_archive_url":null,"date":"2026-05-01T23:27:41","subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","submitter":{"id":93110,"url":"http://patchwork.ozlabs.org/api/people/93110/","name":"Dan Williams (nvidia)","email":"djbw@kernel.org"},"content":"Nicolin Chen wrote:\n> On Thu, Apr 30, 2026 at 02:41:22PM -0700, Dan Williams (nvidia) wrote:\n> > > +static bool pci_cxl_ats_always_on(struct pci_dev *pdev)\n> > > +{\n> > > +\tint offset;\n> > > +\tu16 cap;\n> > > +\n> > > +\toffset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n> > > +\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n> > > +\tif (!offset)\n> > > +\t\treturn false;\n> > > +\n> > > +\tif (pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap))\n> > > +\t\treturn false;\n> > > +\n> > > +\treturn cap & PCI_DVSEC_CXL_CACHE_CAPABLE;\n> [...]\n> > Apologies for coming to this late and forgive me if the following has\n> > already been asked and answered. Why not check for actual CXL.cache\n> > protocol on the wire being present?\n> \n> Actually it would make the patch smaller. The thing is that this\n> is_cxl property wasn't added when I started the series. So, it's\n> not using it. :)\n> \n> > @@ -1733,9 +1733,8 @@ static void set_pcie_cxl(struct pci_dev *dev)\n> > \tpci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS,\n> > \t\t\t &cap);\n> > \n> > -\tdev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap) ||\n> > -\t\tFIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n> > -\n> > +\tdev->is_cxl_cache = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap);\n> > +\tdev->is_cxl_mem = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap);\n> \n> One caveat is that:\n> \n> Here it checks the cap from:\n> \tPCI_DVSEC_CXL_FLEXBUS_PORT_STATUS (0xE) via\n> \t\tPCI_DVSEC_CXL_FLEXBUS_PORT_STATUS (0x7)\n> \n> On the other hand, mine checks from:\n> \tPCI_DVSEC_CXL_CAP (0xA) via\n> \t\tPCI_DVSEC_CXL_DEVICE (0x0)\n> \n> The spec mentions in 8.2.1.3.1 DVSEC Flex Bus Port Capability: \"\n> Note: The Mem_Capable, IO_Capable, and Cache_Capable fields are\n> also present in the DVSEC Flex Bus for the device [which is the\n> legacy name for DVSEC 0x0]. This allows for future scalability\n> where multiple devices, each with potentially different\n> capabilities, may be populated behind a single Port.\n> \"\n> \n> Not arguing that set_pcie_cxl() is wrong, but I am not sure if there\n> would be any side effect to rely on the \"legacy name\" over DVSEC 0x0.\n> \n> Is there any CXL expert who can help confirm?\n\nYou appear to be confusing Cache_Capable and Cache_Enabled.\n\n\"8.2.1.3.1 DVSEC Flex Bus Port Capability\" != \"8.2.1.3.3 DVSEC Flex Bus Port Status\"\n\nCache_Capable is only a capability. To check that the device has\nactually trained the CXL.cache alternate protocol you need to look at\nthe status register.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=GpK1WTsd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-53611-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"GpK1WTsd\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6nJk1C0Nz1yHZ\n\tfor ; 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To check that the device has\n> actually trained the CXL.cache alternate protocol you need to look at\n> the status register.\n\nThe capable is probably a reasonable choice here unless you are\nconfident the status will never change after the device is first\ndiscovered? ATS is being set early in the boot sequence.\n\nIt is pretty safe to be over eager with the ATS enablement, less safe\nto get it off when it needs to be on.\n\nJason","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bn/J6+ms;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53613-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"bn/J6+ms\"","smtp.subspace.kernel.org;\n arc=fail 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dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=bn/J6+ms; arc=fail smtp.client-ip=40.93.201.51","i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=XOW+3LD3hVmaVzm1BjhUO50sBN+CcYoYiT5kIe678Gs=;\n b=bn/J6+ms8QQwa5/ZxOikHQ1+zDaE+op2Ld+S8HzJiJDL5qkaOv7wAuV3AyjSK5Ikp9WHGMdUA23LL8oL5MUvvJo2qtTY5rBuCOKrbyBtHM1iilRr8aAB53Cv+tyoYqGifeCneuOx5c+asEujzQcQ5dOyJhyx7mVKgaF3znh+FFEdRgD7USiQBTxIm215ugNrNP/6/vcy3clorRaP+XY2QaxcyilZNPUC+6JqthBsgnjrMqM17wq7gAo3EtR+goqGEa9WA7PJ8vpynx8HKzxBOUm9WdyPYtYYkRKFOSiaFeZzHJQPObBkp3lf7gUcEp3wGQZ5qQi80LohW7AkSN+I3A==","Date":"Fri, 1 May 2026 20:46:41 -0300","From":"Jason Gunthorpe ","To":"\"Dan Williams (nvidia)\" ","Cc":"Nicolin Chen , will@kernel.org,\n\trobin.murphy@arm.com, bhelgaas@google.com, joro@8bytes.org,\n\tpraan@google.com, baolu.lu@linux.intel.com, kevin.tian@intel.com,\n\tmiko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org,\n\tiommu@lists.linux.dev, linux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, dan.j.williams@intel.com,\n\tjonathan.cameron@huawei.com, vsethi@nvidia.com,\n\tlinux-cxl@vger.kernel.org, nirmoyd@nvidia.com","Subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","Message-ID":"<20260501234641.GB1381708@nvidia.com>","References":"\n \n <69f3cc82926_3291a910039@djbw-dev.notmuch>\n \n <69f536ed263dd_3291a910017@djbw-dev.notmuch>","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<69f536ed263dd_3291a910017@djbw-dev.notmuch>","X-ClientProxiedBy":"BYAPR05CA0029.namprd05.prod.outlook.com\n (2603:10b6:a03:c0::42) To LV8PR12MB9620.namprd12.prod.outlook.com\n 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JHzNKDww8fbfTiSI1pTp+Mmbej/3EBeRSXlML8XpoD4w4WQpQ4xlPxssV4R5G5qapwUgsHhVwqeD1d3q/rxNa7Fft/W/6h8zVzzgPpvW1oN2Ukdjwsf0lx09ZCsDvjiFlT8uII5Gl3ODPkj5N9+zeodNrZNEr08lPpDAOnNIDHx5vjzIiIjkBguBpPTkI2R0a0Ad+gJCKPQOhgMgCbvIpW9foShPJdnEGuLBToA3pap9pmpsymtLzjkmPoEpy4vmewZmRhiEq+jYvoTNODOnk/72XEBb+sGU0k5uVGXCB2rS4bnOkR+/hQtBeBsd0/Rv1fqbVMala7rf4C5bduy2CS+kl8xemhZP/TEBQCtGgA/YAgLLy2600bifdbFbzO09GDa0kvYDz8fdJ4LVIkvT3Azps83rvjkdohhP1IfqH8wluitigdlkpz1P9p+bkBVd6eHTAlkkgkZuUjEsnYbjuwKdCWlUEsEuHu4LHuXdtkO4k2TyVdzbO2/EyjQk7mlPsteqCitTXwaDvibQWpQiGEnYY5pPfs0rVbWd8DjBlueHISxoRbTHVghgj8woXmUdomeeU8LRz+6y6AsX+SJJt+FZJokj8D1DDIPL7xVeoCZ1v5FYySjutoEg2jemkdsV21oJyZnc2GyUbSxpT/9j9Uf9Wa4Gc7Q2kXq+KTT7eICOEXIEH2s3Sl/bGJfk479P0ACuyroK3xMglecw4nTyEZ2uAoMruG7w+LOHqiuriXYjEmBmAXvt6tnN43NW57tQLX2OivNW9Fz87rQiW312mhxJHfrP3R6k1V0BVK4dk4RcG1Gy7R5YyBR6VWCi5hvd08uf11FRx2qBm45d046D13Qep0RBzmSi/blXLmkfogdS9Z33udHLovlLvUZbpK2nYo3znu7oI1Zl8Vdfq8q2Yb4nqokeB/HxeCJzzR5iOtNtwA2bFDJSMN996AvYynFRYo0+gDNrq4wm/5tNysmw4F+EP9Y7B4mPUuOtR6E4VYz6mMNS2+bVxbSObLY6lEU++OlfgBQn1fI9qAGgAqWuQL6sHF/JgEO9lPAxcm4d4DgNmMsXmLUCQ9pZbkyKzBnIoWfRmwJKbTex13ygVr1bG0LL9ibcwMtwmWZiAQ1aRUihZNbbV3AJ/oZJskSnUyr2GjA4r+p3unmgf3t9l7Htfg6p2ygZwO8yVJqYYMvd2si/Hpqi/W0YT34tWIE0aEk73+3jBs0uwj7OYe11msXH8JJXBOYQu9OlwDdU2I8Gp1hS8JI15SPP+uibV1kNx8lONur/6X9Kk+fOAd6wtkxor/lPRak+qC68/w9O5tkdiJEWrMUbXrwqWpAxoIJF+Z3nbV1yxG84BH1V+GR/GNqxxNIlsrZeWAOY4yzwyDbFzBzJyrQ90Lx92AFUyvkEWwbxMoxgaPEjsXZIoJnXFSjrULYo+VvPPZskMTKcVt3M28KRLLZBloMf/ZcgVcSINxwWTfYYFLq44pudaG0Y3B4/AiitabBigyxG29WBfO7d2uYe80VKLK+cjgQWc9NAKu5cRKgMyd4BKKSKNfx7wIIJ2kIbgcE++xGHh6Zu+3m6C93s73AHqYIUD1khzQdU+sjTw3EHIXnYHZEu8hBJmXYbnSOG2M3cRDWFaXPhuFP9eYXTvYeB7aYrNW5F3XBJKWIkqe2eGfvOQLInE6Y38ZXJjYcUB7lAJjpu0+2veOC3K78V9NO/oPqTzjjNch/W6Dtu","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n beb77938-ca07-4a0f-0309-08dea7dbe68e","X-MS-Exchange-CrossTenant-AuthSource":"LV8PR12MB9620.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"01 May 2026 23:46:44.3134\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n yAW3b12MGineqXgNod5Q1XfQUYPCDZ05OZlESTx1zOKn2nNm4Ya4TDfSFlTkK4o9","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS0PR12MB7511"}},{"id":3685248,"web_url":"http://patchwork.ozlabs.org/comment/3685248/","msgid":"<69f542f92e36e_3291a910052@djbw-dev.notmuch>","list_archive_url":null,"date":"2026-05-02T00:19:05","subject":"Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache\n capable devices","submitter":{"id":93110,"url":"http://patchwork.ozlabs.org/api/people/93110/","name":"Dan Williams (nvidia)","email":"djbw@kernel.org"},"content":"Jason Gunthorpe wrote:\n> On Fri, May 01, 2026 at 04:27:41PM -0700, Dan Williams (nvidia) wrote:\n> \n> > You appear to be confusing Cache_Capable and Cache_Enabled.\n> > \n> > \"8.2.1.3.1 DVSEC Flex Bus Port Capability\" != \"8.2.1.3.3 DVSEC Flex Bus Port Status\"\n> > \n> > Cache_Capable is only a capability. To check that the device has\n> > actually trained the CXL.cache alternate protocol you need to look at\n> > the status register.\n> \n> The capable is probably a reasonable choice here unless you are\n> confident the status will never change after the device is first\n> discovered? ATS is being set early in the boot sequence.\n> \n> It is pretty safe to be over eager with the ATS enablement, less safe\n> to get it off when it needs to be on.\n\nTrue, a reset could turn on CXL.cache. Ok, stick with what you have.\n\nThe present state of alternate protocol negotiation is still relevant\nthough for distinguishing CXL protocol errors from other PCIe AER\n\"internal\" errors.\n\nNeed a bit of fixup work for that to refresh the status bit after reset.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=UR5aMexr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-53614-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"UR5aMexr\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6pVN2H9Zz1yJ0\n\tfor ; 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