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GET /api/1.1/patches/2225940/?format=api
{ "id": 2225940, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225940/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260421203856.3539186-1-bwicaksono@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260421203856.3539186-1-bwicaksono@nvidia.com>", "date": "2026-04-21T20:38:56", "name": "[v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "be084ffa00afa9a18fc67f9c7bc8f54345b15a19", "submitter": { "id": 83903, "url": "http://patchwork.ozlabs.org/api/1.1/people/83903/?format=api", "name": "Besar Wicaksono", "email": "bwicaksono@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260421203856.3539186-1-bwicaksono@nvidia.com/mbox/", "series": [ { "id": 500891, "url": "http://patchwork.ozlabs.org/api/1.1/series/500891/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=500891", "date": "2026-04-21T20:38:56", "name": "[v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500891/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225940/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225940/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-13842-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=oRNR9hgB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Besar Wicaksono <bwicaksono@nvidia.com>", "To": "<will@kernel.org>, <mark.rutland@arm.com>, <james.clark@linaro.org>", "CC": "<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <treding@nvidia.com>, <jonathanh@nvidia.com>,\n\t<vsethi@nvidia.com>, <rwiley@nvidia.com>, <sdonthineni@nvidia.com>,\n\t<mochs@nvidia.com>, <nirmoyd@nvidia.com>, <skelley@nvidia.com>, \"Besar\n Wicaksono\" <bwicaksono@nvidia.com>", "Subject": "[PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus", "Date": "Tue, 21 Apr 2026 20:38:56 +0000", "Message-ID": "<20260421203856.3539186-1-bwicaksono@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE37:EE_|SJ5PPFFA661D690:EE_", "X-MS-Office365-Filtering-Correlation-Id": "133db09d-71f4-4876-ef98-08de9fe6109a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tWXc5LZB8bkvMXw6BYm8Et+H5QdeNguJCX8AB0r2bDQHsvW9YMILVQIEtVnbUHo8DfLsWHL5jLIFwbKlWdB8aZYb+mzBHc7SvPW7rVN9W3sGqfN7nUpNjTsDF3ohT0LBQwCTe4Lax/P9lPs7O66foEVGRYd+m28YWJw3ATNcasRr+Xm3cDeXOrMZyDLpMi9Vn89rHWbXXPYecIeX4pImOtTTSisS4qOL1II3mALGKreZLG5IYPM4Bi6dYHa+z8e6WSMMcBAjWTTWPAWj+6Z8ts/3mz0U38pg8muW7k6srh77/zl7W8GTGCYWrHpAsVX+XtxPVYddLJZvt0IeGKuuMiohdllFMdRLFJTZaOJM6bX1E6fApgHdrrJ2IardzvTIuvOOs+Q1FvojoViGwd7VVEkILVw/9CAZ5L1NtsJK2fIlcAP3W/kTM9rHmFvstS+IXWwBFqJX2avDeTP3T1J9PHbCps9xYXvrGy0J0Px4tQqz03i3outesgOH115HkI9pfmWueNOlWjr9fFg4hzxoM0GO4d5GsK6l2bMcqzW7K1pHZlc/Hmajb98FyXlz5efYK+GzlIruWry9qPaBhYBIRS08esvggB/ddPti62SVbL9l0CuTDocsNSpPxJEFJIG75z5ThAm52FCdtUyrSY1g81UkmnChG1/ssBRxyywTEL5jj5Swc1smuVTjjEYySTJAxdj4K4331M6pO4aqwFGHmmBfPwN+6NcNU6oc452tMzf/uGws1kMaIMrhfqfMsnwdeG5EmBzZnvjT2v4RSnvkvrA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tcocbFsb2GU6PKGP0KuzZMaxOfTNwBsqJ7tlKAjggLnKWu2LjnY/jRHWvar99VWE5/KYatWhY3fRywoPgL1VtW94B413GCAgwBUwBvVbtlRUsrjoh3nE+yz6EO+hc814R/mssidBzF/KTGKd35ME5NC0cZ7x6zvFoyxtaCKnAybN2byI756rEGpCqeeTwH7iSblXbLLe91pXWJTRgjKyB3pPSfsZuGbV2E+GwPW7SBIpRGUD1tBs7UmGw+lnA31X0rkJM8zfi13gAXR3/1dPv0Wkib4dzRTr7pFu70sypjRH5O6eSwhYTRVeN9UNMdTHzAhpCp81gQeDof4Vt4i+5JJhQChz6GCZW3CxjDTXijh0Lxi4KbhpmU0xUFwNqnlXb3k0sN23fEf+frBhOYK9I3K48e0VJgTpifBF23UtTHswVYEvv2SAihx6eqs+gsCw1", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 20:39:20.1956\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 133db09d-71f4-4876-ef98-08de9fe6109a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE37.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ5PPFFA661D690" }, "content": "The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while\nin WFI/WFE, which does not align with counting CPU_CYCLES\non a programmable counter. Add a MIDR range entry and\nrefuse PMCCNTR_EL0 for cycle events on affected parts so\nperf does not mix the two behaviors.\n\nSigned-off-by: Besar Wicaksono <bwicaksono@nvidia.com>\n---\n\nChanges from v1:\n * add CONFIG_ARM64 check to fix build error found by kernel test robot\n * add explicit include of <asm/cputype.h>\nv1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-bwicaksono@nvidia.com/\n\n---\n drivers/perf/arm_pmuv3.c | 44 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 44 insertions(+)", "diff": "diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\nindex 8014ff766cff..7c39d0804b9f 100644\n--- a/drivers/perf/arm_pmuv3.c\n+++ b/drivers/perf/arm_pmuv3.c\n@@ -8,6 +8,7 @@\n * This code is based heavily on the ARMv7 perf event code.\n */\n \n+#include <asm/cputype.h>\n #include <asm/irq_regs.h>\n #include <asm/perf_event.h>\n #include <asm/virt.h>\n@@ -978,6 +979,41 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,\n \treturn -EAGAIN;\n }\n \n+#ifdef CONFIG_ARM64\n+/*\n+ * List of CPUs that should avoid using PMCCNTR_EL0.\n+ */\n+static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = {\n+\t/*\n+\t * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state.\n+\t * This is an implementation specific behavior and not an erratum.\n+\t *\n+\t * From ARM DDI0487 D14.4:\n+\t * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count\n+\t * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n+\t *\n+\t * From ARM DDI0487 D24.5.2:\n+\t * All counters are subject to any changes in clock frequency, including\n+\t * clock stopping caused by the WFI and WFE instructions.\n+\t * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n+\t * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and\n+\t * WFE instructions.\n+\t */\n+\tMIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n+\t{}\n+};\n+\n+static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n+{\n+\treturn is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus);\n+}\n+#else\n+static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n+{\n+\treturn false;\n+}\n+#endif\n+\n static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n \t\t\t\t struct perf_event *event)\n {\n@@ -1011,6 +1047,14 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n \tif (cpu_pmu->has_smt)\n \t\treturn false;\n \n+\t/*\n+\t * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES\n+\t * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to\n+\t * prevent inconsistency in the results.\n+\t */\n+\tif (armv8pmu_is_in_avoid_pmccntr_cpus())\n+\t\treturn false;\n+\n \treturn true;\n }\n \n", "prefixes": [ "v2" ] }