[{"id":3680448,"web_url":"http://patchwork.ozlabs.org/comment/3680448/","msgid":"","list_archive_url":null,"date":"2026-04-22T10:32:39","subject":"Re: [PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":88902,"url":"http://patchwork.ozlabs.org/api/people/88902/","name":"James Clark","email":"james.clark@linaro.org"},"content":"On 21/04/2026 21:38, Besar Wicaksono wrote:\n> The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while\n> in WFI/WFE, which does not align with counting CPU_CYCLES\n> on a programmable counter. Add a MIDR range entry and\n> refuse PMCCNTR_EL0 for cycle events on affected parts so\n> perf does not mix the two behaviors.\n> \n> Signed-off-by: Besar Wicaksono \n> ---\n> \n> Changes from v1:\n> * add CONFIG_ARM64 check to fix build error found by kernel test robot\n> * add explicit include of \n> v1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-bwicaksono@nvidia.com/\n> \n> ---\n> drivers/perf/arm_pmuv3.c | 44 ++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 44 insertions(+)\n> \n> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\n> index 8014ff766cff..7c39d0804b9f 100644\n> --- a/drivers/perf/arm_pmuv3.c\n> +++ b/drivers/perf/arm_pmuv3.c\n> @@ -8,6 +8,7 @@\n> * This code is based heavily on the ARMv7 perf event code.\n> */\n> \n> +#include \n> #include \n> #include \n> #include \n> @@ -978,6 +979,41 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,\n> \treturn -EAGAIN;\n> }\n> \n> +#ifdef CONFIG_ARM64\n> +/*\n> + * List of CPUs that should avoid using PMCCNTR_EL0.\n> + */\n> +static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = {\n> +\t/*\n> +\t * The PMCCNTR_EL0 in Olympus CPU may still increment while in WFI/WFE state.\n> +\t * This is an implementation specific behavior and not an erratum.\n> +\t *\n> +\t * From ARM DDI0487 D14.4:\n> +\t * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count\n> +\t * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n> +\t *\n> +\t * From ARM DDI0487 D24.5.2:\n> +\t * All counters are subject to any changes in clock frequency, including\n> +\t * clock stopping caused by the WFI and WFE instructions.\n> +\t * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n> +\t * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and\n> +\t * WFE instructions.\n> +\t */\n> +\tMIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n> +\t{}\n> +};\n> +\n> +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n> +{\n> +\treturn is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus);\n> +}\n> +#else\n> +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n> +{\n> +\treturn false;\n> +}\n> +#endif\n> +\n> static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n> \t\t\t\t struct perf_event *event)\n> {\n> @@ -1011,6 +1047,14 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n> \tif (cpu_pmu->has_smt)\n> \t\treturn false;\n> \n> +\t/*\n> +\t * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES\n> +\t * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to\n> +\t * prevent inconsistency in the results.\n> +\t */\n> +\tif (armv8pmu_is_in_avoid_pmccntr_cpus())\n> +\t\treturn false;\n> +\n\nHi Besar,\n\nThis is called from armpmu_event_init() before the event is scheduled on \nthe CPU so I don't think reading the MIDR at this point is safe.\n\nWhen the PMU is probed you probably need to do an SMP call to get the \nMIDR of CPUs in that PMU's mask and then cache the \"avoid pmccntr\" \nresult like has_smt. Or even rename has_smt to avoid_pmccntr and combine \nthe two results there.\n\nI don't know what will happen if none of those CPUs are online when the \nPMU is probed though...\n\nJames\n\n\n\n> \treturn true;\n> }\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=o0PStOUV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13847-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org\n header.b=\"o0PStOUV\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.44","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linaro.org","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linaro.org"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0wbP16G6z1yD5\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":3681025,"web_url":"http://patchwork.ozlabs.org/comment/3681025/","msgid":"","list_archive_url":null,"date":"2026-04-22T20:17:11","subject":"RE: [PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":83903,"url":"http://patchwork.ozlabs.org/api/people/83903/","name":"Besar Wicaksono","email":"bwicaksono@nvidia.com"},"content":"> -----Original Message-----\n> From: James Clark \n> Sent: Wednesday, April 22, 2026 5:33 AM\n> To: Besar Wicaksono ; will@kernel.org;\n> mark.rutland@arm.com\n> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-\n> tegra@vger.kernel.org; Thierry Reding ; Jon Hunter\n> ; Vikram Sethi ; Rich Wiley\n> ; Shanker Donthineni ; Matt\n> Ochs ; Nirmoy Das ; Sean Kelley\n> \n> Subject: Re: [PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA\n> Olympus\n> \n> External email: Use caution opening links or attachments\n> \n> \n> On 21/04/2026 21:38, Besar Wicaksono wrote:\n> > The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while\n> > in WFI/WFE, which does not align with counting CPU_CYCLES\n> > on a programmable counter. Add a MIDR range entry and\n> > refuse PMCCNTR_EL0 for cycle events on affected parts so\n> > perf does not mix the two behaviors.\n> >\n> > Signed-off-by: Besar Wicaksono \n> > ---\n> >\n> > Changes from v1:\n> > * add CONFIG_ARM64 check to fix build error found by kernel test robot\n> > * add explicit include of \n> > v1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-\n> bwicaksono@nvidia.com/\n> >\n> > ---\n> > drivers/perf/arm_pmuv3.c | 44\n> ++++++++++++++++++++++++++++++++++++++++\n> > 1 file changed, 44 insertions(+)\n> >\n> > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\n> > index 8014ff766cff..7c39d0804b9f 100644\n> > --- a/drivers/perf/arm_pmuv3.c\n> > +++ b/drivers/perf/arm_pmuv3.c\n> > @@ -8,6 +8,7 @@\n> > * This code is based heavily on the ARMv7 perf event code.\n> > */\n> >\n> > +#include \n> > #include \n> > #include \n> > #include \n> > @@ -978,6 +979,41 @@ static int armv8pmu_get_chain_idx(struct\n> pmu_hw_events *cpuc,\n> > return -EAGAIN;\n> > }\n> >\n> > +#ifdef CONFIG_ARM64\n> > +/*\n> > + * List of CPUs that should avoid using PMCCNTR_EL0.\n> > + */\n> > +static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = {\n> > + /*\n> > + * The PMCCNTR_EL0 in Olympus CPU may still increment while in\n> WFI/WFE state.\n> > + * This is an implementation specific behavior and not an erratum.\n> > + *\n> > + * From ARM DDI0487 D14.4:\n> > + * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR\n> count\n> > + * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n> > + *\n> > + * From ARM DDI0487 D24.5.2:\n> > + * All counters are subject to any changes in clock frequency, including\n> > + * clock stopping caused by the WFI and WFE instructions.\n> > + * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n> > + * PMCCNTR_EL0 continues to increment when clocks are stopped by\n> WFI and\n> > + * WFE instructions.\n> > + */\n> > + MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n> > + {}\n> > +};\n> > +\n> > +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n> > +{\n> > + return is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus);\n> > +}\n> > +#else\n> > +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n> > +{\n> > + return false;\n> > +}\n> > +#endif\n> > +\n> > static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n> > struct perf_event *event)\n> > {\n> > @@ -1011,6 +1047,14 @@ static bool armv8pmu_can_use_pmccntr(struct\n> pmu_hw_events *cpuc,\n> > if (cpu_pmu->has_smt)\n> > return false;\n> >\n> > + /*\n> > + * On some CPUs, PMCCNTR_EL0 does not match the behavior of\n> CPU_CYCLES\n> > + * programmable counter, so avoid routing cycles through PMCCNTR_EL0\n> to\n> > + * prevent inconsistency in the results.\n> > + */\n> > + if (armv8pmu_is_in_avoid_pmccntr_cpus())\n> > + return false;\n> > +\n> \n> Hi Besar,\n> \n> This is called from armpmu_event_init() before the event is scheduled on\n> the CPU so I don't think reading the MIDR at this point is safe.\n> \n> When the PMU is probed you probably need to do an SMP call to get the\n> MIDR of CPUs in that PMU's mask and then cache the \"avoid pmccntr\"\n> result like has_smt. Or even rename has_smt to avoid_pmccntr and combine\n> the two results there.\n> \n> I don't know what will happen if none of those CPUs are online when the\n> PMU is probed though...\n> \n\nHi James,\n\nhas_smt, iiuc, is common to all the supported CPUs of the PMU context.\nIt is configured based on the first CPU in supported cpu list.\n\n pmu->has_smt = topology_core_has_smt(cpumask_first(&pmu->supported_cpus));\n\nIs it okay to use same approach? Can we assume all CPUs in supported_cpus have same midr?\n\nThanks,\nBesar","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=S8/azgFC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13852-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"S8/azgFC\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.209.25","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g19W90Smnz1yHB\n\tfor ; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"SN7PR12MB7226.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 64451d39-6758-4441-748c-08dea0ac2340","X-MS-Exchange-CrossTenant-originalarrivaltime":"22 Apr 2026 20:17:11.9271\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n /wQULhOH9e78yv5KZJaLFVWGmTb+sar8oPL6hSDq7cikvcxM1csRTjVmPuiJ77HE2vYx0HyATmFpvUxHarvqRg==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MN0PR12MB6102"}},{"id":3681329,"web_url":"http://patchwork.ozlabs.org/comment/3681329/","msgid":"<5cc2f7b0-852d-4feb-8d47-39aac44e0093@linaro.org>","list_archive_url":null,"date":"2026-04-23T08:29:42","subject":"Re: [PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus","submitter":{"id":88902,"url":"http://patchwork.ozlabs.org/api/people/88902/","name":"James Clark","email":"james.clark@linaro.org"},"content":"On 22/04/2026 21:17, Besar Wicaksono wrote:\n> \n> \n>> -----Original Message-----\n>> From: James Clark \n>> Sent: Wednesday, April 22, 2026 5:33 AM\n>> To: Besar Wicaksono ; will@kernel.org;\n>> mark.rutland@arm.com\n>> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-\n>> tegra@vger.kernel.org; Thierry Reding ; Jon Hunter\n>> ; Vikram Sethi ; Rich Wiley\n>> ; Shanker Donthineni ; Matt\n>> Ochs ; Nirmoy Das ; Sean Kelley\n>> \n>> Subject: Re: [PATCH v2] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA\n>> Olympus\n>>\n>> External email: Use caution opening links or attachments\n>>\n>>\n>> On 21/04/2026 21:38, Besar Wicaksono wrote:\n>>> The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while\n>>> in WFI/WFE, which does not align with counting CPU_CYCLES\n>>> on a programmable counter. Add a MIDR range entry and\n>>> refuse PMCCNTR_EL0 for cycle events on affected parts so\n>>> perf does not mix the two behaviors.\n>>>\n>>> Signed-off-by: Besar Wicaksono \n>>> ---\n>>>\n>>> Changes from v1:\n>>> * add CONFIG_ARM64 check to fix build error found by kernel test robot\n>>> * add explicit include of \n>>> v1: https://lore.kernel.org/linux-arm-kernel/20260406232034.2566133-1-\n>> bwicaksono@nvidia.com/\n>>>\n>>> ---\n>>> drivers/perf/arm_pmuv3.c | 44\n>> ++++++++++++++++++++++++++++++++++++++++\n>>> 1 file changed, 44 insertions(+)\n>>>\n>>> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c\n>>> index 8014ff766cff..7c39d0804b9f 100644\n>>> --- a/drivers/perf/arm_pmuv3.c\n>>> +++ b/drivers/perf/arm_pmuv3.c\n>>> @@ -8,6 +8,7 @@\n>>> * This code is based heavily on the ARMv7 perf event code.\n>>> */\n>>>\n>>> +#include \n>>> #include \n>>> #include \n>>> #include \n>>> @@ -978,6 +979,41 @@ static int armv8pmu_get_chain_idx(struct\n>> pmu_hw_events *cpuc,\n>>> return -EAGAIN;\n>>> }\n>>>\n>>> +#ifdef CONFIG_ARM64\n>>> +/*\n>>> + * List of CPUs that should avoid using PMCCNTR_EL0.\n>>> + */\n>>> +static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = {\n>>> + /*\n>>> + * The PMCCNTR_EL0 in Olympus CPU may still increment while in\n>> WFI/WFE state.\n>>> + * This is an implementation specific behavior and not an erratum.\n>>> + *\n>>> + * From ARM DDI0487 D14.4:\n>>> + * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR\n>> count\n>>> + * when the PE is in WFI or WFE state, even if the clocks are not stopped.\n>>> + *\n>>> + * From ARM DDI0487 D24.5.2:\n>>> + * All counters are subject to any changes in clock frequency, including\n>>> + * clock stopping caused by the WFI and WFE instructions.\n>>> + * This means that it is CONSTRAINED UNPREDICTABLE whether or not\n>>> + * PMCCNTR_EL0 continues to increment when clocks are stopped by\n>> WFI and\n>>> + * WFE instructions.\n>>> + */\n>>> + MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),\n>>> + {}\n>>> +};\n>>> +\n>>> +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n>>> +{\n>>> + return is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus);\n>>> +}\n>>> +#else\n>>> +static bool armv8pmu_is_in_avoid_pmccntr_cpus(void)\n>>> +{\n>>> + return false;\n>>> +}\n>>> +#endif\n>>> +\n>>> static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,\n>>> struct perf_event *event)\n>>> {\n>>> @@ -1011,6 +1047,14 @@ static bool armv8pmu_can_use_pmccntr(struct\n>> pmu_hw_events *cpuc,\n>>> if (cpu_pmu->has_smt)\n>>> return false;\n>>>\n>>> + /*\n>>> + * On some CPUs, PMCCNTR_EL0 does not match the behavior of\n>> CPU_CYCLES\n>>> + * programmable counter, so avoid routing cycles through PMCCNTR_EL0\n>> to\n>>> + * prevent inconsistency in the results.\n>>> + */\n>>> + if (armv8pmu_is_in_avoid_pmccntr_cpus())\n>>> + return false;\n>>> +\n>>\n>> Hi Besar,\n>>\n>> This is called from armpmu_event_init() before the event is scheduled on\n>> the CPU so I don't think reading the MIDR at this point is safe.\n>>\n>> When the PMU is probed you probably need to do an SMP call to get the\n>> MIDR of CPUs in that PMU's mask and then cache the \"avoid pmccntr\"\n>> result like has_smt. Or even rename has_smt to avoid_pmccntr and combine\n>> the two results there.\n>>\n>> I don't know what will happen if none of those CPUs are online when the\n>> PMU is probed though...\n>>\n> \n> Hi James,\n> \n> has_smt, iiuc, is common to all the supported CPUs of the PMU context.\n> It is configured based on the first CPU in supported cpu list.\n> \n> pmu->has_smt = topology_core_has_smt(cpumask_first(&pmu->supported_cpus));\n> \n> Is it okay to use same approach? Can we assume all CPUs in supported_cpus have same midr?\n> \n\nThey should have the same MIDR otherwise it would be misconfigured, or \nat least the PMUs should behave exactly the same way for all CPUs in the \nmask. I think the whole point of separate PMUs is for heterogeneous systems.\n\nAs long as all CPUs in that mask behave the same way, then reading the \nMIDR from any CPU in that mask should be ok. We do it that way for SPE \nas well:\n\n /* Make sure we probe the hardware on a relevant CPU */\n ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1);\n\n\n> Thanks,\n> Besar\n> \n> \n> \n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=LWYSpM2R;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13853-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org\n header.b=\"LWYSpM2R\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.221.46","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linaro.org","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linaro.org"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1TnM1NLwz1yD5\n\tfor ; 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