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GET /api/1.1/patches/2225736/?format=api
{ "id": 2225736, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225736/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260421140659.748577-1-ankita@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260421140659.748577-1-ankita@nvidia.com>", "date": "2026-04-21T14:06:59", "name": "[v4,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eec38b9f97270b279ecaad83330696f7c9922ffd", "submitter": { "id": 86155, "url": "http://patchwork.ozlabs.org/api/1.1/people/86155/?format=api", "name": "Ankit Agrawal", "email": "ankita@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260421140659.748577-1-ankita@nvidia.com/mbox/", "series": [ { "id": 500817, "url": "http://patchwork.ozlabs.org/api/1.1/series/500817/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500817", "date": "2026-04-21T14:06:59", "name": "[v4,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500817/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225736/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225736/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52835-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=XyEXdC8b;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Ankit Agrawal <ankita@nvidia.com>", "To": "<alex@shazbot.org>, <kvm@vger.kernel.org>", "CC": "<jgg@ziepe.ca>, <yishaih@nvidia.com>, <skolothumtho@nvidia.com>,\n\t<kevin.tian@intel.com>, <ankita@nvidia.com>, <bhelgaas@google.com>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v4 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC", "Date": "Tue, 21 Apr 2026 14:06:59 +0000", "Message-ID": "<20260421140659.748577-1-ankita@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF000001C9:EE_|MN2PR12MB4456:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2fb13472-13ff-4baf-c96b-08de9faf4668", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tKX46BxXgwxZIx3iNoz+oYvOWwCScucyEYP9M3W59sR/+9003FaLaQ8ZCVRvcYR3W1wl2pbRgNIFlWUltC9PVUrYvt0OZpHlEYococz8sH1fvUeJUa8CZAAnHOJSjG1XHh9KZil594GatkiRkcwzSnDLZu/5Ze6DHYUfXr3Xy2LmDodEEysJ3mytNvwn9WMH3TOVTn2g1M/eXH9HvMDNo+FHMrT3xerglsTUZ08ny7oFSyFu8UpK9/ilNTlklyWNhZN8rhvkeeIXIwR6m5mf6SrreCFgeC/HqWWeQ/Nd4C5Uh4dPVKAl/5SUVPGw4pyCZjM/0Me3wGG+Kf8vg0sUXIrt7xL3wEnO+/vqYNhkSnQCIzUpyiDEIouXsaBuW/vInrCtDp+n8X9W3KDFzdC+gKA1mnKgmASuvTyNHDYxiPI6Oc/uKOuO4ucKE60yCHgpz3TYQZTIG4KioIS+L76FrhEVCfhopm9eM8CJxWVWeWWFwtLCiXKPpYv+NhRNp7Sqg1YD1markMqYDtWxQRTwEvIdAKLM8plyMiSdqkT9KDYG8C/oTcu2FWsCxgVNImbSuNKzmM0XTcUpKiSXFrV/yQ9NZ/s8w3WzHUN6ZLoVfs8e2J2V/y2c57lbnDi4OHbhnK43gv4WSTegqR3Pk+Y5MwZUuBDcVUJuJDDCvjOTMTEyisl3Zg9TMcTIsvaWF7cq6u0lrFN1n4RkU4n/t/ehz+3ECXGIrIbCnmUUVexT9sXtYQnQFQbaE9AWIpRkSmjBhTcq4gm2KYyTfgeMFXB4eSA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tCZHG4CS77Nhbk7cZd9dtGVzlOeZ/OjvmJnK3sVtwo1AfzfbnZTIngt6k4ik5dnO4Ns3Bt/w8Zd0q/yRj0Kz88Y4pO1LicDga7cQW311yhqaKLMTLtKSaE97DzxGrfXsHxUHWnrJhA+rIysWr9KlK0e3rKRgeB2g/U9DNzVHmByA9QsHzpbccugjNFgXSFWFUVmCzAJsclfOFLAfsjVQgePOwT5JlzCuWZ6Lf5mfoPk/Vj2QT0VlFMc/5e7Qr88tDkO97V/9l7l/U4wH4ivTB1xEWtlj/9xJRnkOa2IvG5kkuCRrOBjwPr4YZ0tKoNX8/nsC4GpvLDaNr1kaE7fgrJjvu0WKoUoZlKEUkS1m/SUDcHn3pu12lEQkSZrBb+4CNYZlNsHYpFrG1RzRqjaSwxg7W8cvMOtW16LWkjNBakeF3tGRgHFcAznEBbfW4kHhc", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Apr 2026 14:07:08.2306\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2fb13472-13ff-4baf-c96b-08de9faf4668", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ5PEPF000001C9.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4456" }, "content": "Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside\nthe existing legacy BAR0 polling path. On probe and after reset, the\ndriver reads the CXL Device DVSEC capability to determine whether the\nGPU memory is ready. A static inline wrapper dispatches to the\nappropriate readiness check (legacy v/s blackwell-next based on whether\nthe CXL DVSEC capability is present.\n\nThe memory readiness is checked by polling on the Memory_Active bit\nbased on the Memory_Active_Timeout. It also checks if MEM_INFO_VALID\nis set within 1 second. If not, return error. This is based on the\nCXL spec 4.0 Tables 8-13.\n\nAdd PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout\nfield encoding.\n\ncc: Kevin Tian <kevin.tian@intel.com>\nSuggested-by: Alex Williamson <alex@shazbot.org>\nSigned-off-by: Ankit Agrawal <ankita@nvidia.com>\n---\n drivers/vfio/pci/nvgrace-gpu/main.c | 102 +++++++++++++++++++++++++---\n include/uapi/linux/pci_regs.h | 1 +\n 2 files changed, 95 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c\nindex fa056b69f899..81a725460112 100644\n--- a/drivers/vfio/pci/nvgrace-gpu/main.c\n+++ b/drivers/vfio/pci/nvgrace-gpu/main.c\n@@ -3,6 +3,7 @@\n * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved\n */\n \n+#include <linux/bitfield.h>\n #include <linux/sizes.h>\n #include <linux/vfio_pci_core.h>\n #include <linux/delay.h>\n@@ -64,6 +65,8 @@ struct nvgrace_gpu_pci_core_device {\n \tbool has_mig_hw_bug;\n \t/* GPU has just been reset */\n \tbool reset_done;\n+\t/* CXL Device DVSEC offset; 0 if not present (legacy GB path) */\n+\tint cxl_dvsec;\n };\n \n static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev)\n@@ -242,7 +245,7 @@ static void nvgrace_gpu_close_device(struct vfio_device *core_vdev)\n \tvfio_pci_core_close_device(core_vdev);\n }\n \n-static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n+static int nvgrace_gpu_wait_device_ready_legacy(void __iomem *io)\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS);\n \n@@ -256,6 +259,81 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n \treturn -ETIME;\n }\n \n+/*\n+ * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n+ * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n+ * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n+ * 101b-111b = reserved (clamped to 256s).\n+ */\n+static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n+{\n+\treturn 1000UL << (2 * min_t(u8, timeout, 4));\n+}\n+\n+/*\n+ * Check if CXL DVSEC reports memory as valid and active.\n+ */\n+static inline bool cxl_dvsec_mem_is_active(u32 status)\n+{\n+\treturn (status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t (status & PCI_DVSEC_CXL_MEM_ACTIVE);\n+}\n+\n+static int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)\n+{\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n+\tint cxl_dvsec = nvdev->cxl_dvsec;\n+\tunsigned long mem_info_valid_deadline;\n+\tunsigned long timeout = 0;\n+\tu32 dvsec_memory_status;\n+\n+\tmem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);\n+\n+\tdo {\n+\t\tpci_read_config_dword(pdev,\n+\t\t\t\t cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n+\t\t\t\t &dvsec_memory_status);\n+\n+\t\tif (dvsec_memory_status == ~0U)\n+\t\t\treturn -ENODEV;\n+\n+\t\tif (cxl_dvsec_mem_is_active(dvsec_memory_status))\n+\t\t\treturn 0;\n+\n+\t\t/*\n+\t\t * Once MEM_INFO_VALID is set, derive the MEM_ACTIVE timeout\n+\t\t * from the register.\n+\t\t */\n+\t\tif (dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) {\n+\t\t\tif (!timeout) {\n+\t\t\t\tu8 mem_active_timeout =\n+\t\t\t\t\tFIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n+\t\t\t\t\t\t dvsec_memory_status);\n+\n+\t\t\t\ttimeout = jiffies +\n+\t\t\t\t\t msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Bail early if MEM_INFO_VALID is not set within 1 second */\n+\t\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&\n+\t\t time_after(jiffies, mem_info_valid_deadline))\n+\t\t\treturn -ETIME;\n+\n+\t\tmsleep(POLL_QUANTUM_MS);\n+\t} while (!timeout || !time_after(jiffies, timeout));\n+\n+\treturn -ETIME;\n+}\n+\n+static inline int nvgrace_gpu_wait_device_ready(struct nvgrace_gpu_pci_core_device *nvdev,\n+\t\t\t\t\t\tvoid __iomem *io)\n+{\n+\treturn nvdev->cxl_dvsec ?\n+\t\tnvgrace_gpu_wait_device_ready_cxl(nvdev) :\n+\t\tnvgrace_gpu_wait_device_ready_legacy(io);\n+}\n+\n /*\n * If the GPU memory is accessed by the CPU while the GPU is not ready\n * after reset, it can cause harmless corrected RAS events to be logged.\n@@ -275,7 +353,7 @@ nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n \tif (!__vfio_pci_memory_enabled(vdev))\n \t\treturn -EIO;\n \n-\tret = nvgrace_gpu_wait_device_ready(vdev->barmap[0]);\n+\tret = nvgrace_gpu_wait_device_ready(nvdev, vdev->barmap[0]);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1146,11 +1224,16 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct pci_dev *pdev)\n * Ensure that the BAR0 region is enabled before accessing the\n * registers.\n */\n-static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n+static int nvgrace_gpu_probe_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n {\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n \tvoid __iomem *io;\n \tint ret;\n \n+\t/* CXL path only reads PCI config space; no need to map BAR0. */\n+\tif (nvdev->cxl_dvsec)\n+\t\treturn nvgrace_gpu_wait_device_ready_cxl(nvdev);\n+\n \tret = pci_enable_device(pdev);\n \tif (ret)\n \t\treturn ret;\n@@ -1165,7 +1248,7 @@ static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n \t\tgoto iomap_exit;\n \t}\n \n-\tret = nvgrace_gpu_wait_device_ready(io);\n+\tret = nvgrace_gpu_wait_device_ready_legacy(io);\n \n \tpci_iounmap(pdev, io);\n iomap_exit:\n@@ -1183,10 +1266,6 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \tu64 memphys, memlength;\n \tint ret;\n \n-\tret = nvgrace_gpu_probe_check_device_ready(pdev);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = nvgrace_gpu_fetch_memory_property(pdev, &memphys, &memlength);\n \tif (!ret)\n \t\tops = &nvgrace_gpu_pci_ops;\n@@ -1198,6 +1277,13 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \n \tdev_set_drvdata(&pdev->dev, &nvdev->core_device);\n \n+\tnvdev->cxl_dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n+\n+\tret = nvgrace_gpu_probe_check_device_ready(nvdev);\n+\tif (ret)\n+\t\tgoto out_put_vdev;\n+\n \tif (ops == &nvgrace_gpu_pci_ops) {\n \t\tnvdev->has_mig_hw_bug = nvgrace_gpu_has_mig_hw_bug(pdev);\n \ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350..718fb630f5bb 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1357,6 +1357,7 @@\n #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)\t\t(0x1C + (i * 0x10))\n #define PCI_DVSEC_CXL_MEM_INFO_VALID\t\t\t_BITUL(0)\n #define PCI_DVSEC_CXL_MEM_ACTIVE\t\t\t_BITUL(1)\n+#define PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT\t\t__GENMASK(15, 13)\n #define PCI_DVSEC_CXL_MEM_SIZE_LOW\t\t\t__GENMASK(31, 28)\n #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)\t\t(0x20 + (i * 0x10))\n #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i)\t\t(0x24 + (i * 0x10))\n", "prefixes": [ "v4", "1/1" ] }