[{"id":3679906,"web_url":"http://patchwork.ozlabs.org/comment/3679906/","msgid":"<5b2c6258-ade6-c35c-0edb-6da0ec96e987@linux.intel.com>","list_archive_url":null,"date":"2026-04-21T14:16:10","subject":"Re: [PATCH v4 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","submitter":{"id":83553,"url":"http://patchwork.ozlabs.org/api/people/83553/","name":"Ilpo Järvinen","email":"ilpo.jarvinen@linux.intel.com"},"content":"On Tue, 21 Apr 2026, Ankit Agrawal wrote:\n\n> Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside\n> the existing legacy BAR0 polling path. On probe and after reset, the\n> driver reads the CXL Device DVSEC capability to determine whether the\n> GPU memory is ready. A static inline wrapper dispatches to the\n> appropriate readiness check (legacy v/s blackwell-next based on whether\n> the CXL DVSEC capability is present.\n> \n> The memory readiness is checked by polling on the Memory_Active bit\n> based on the Memory_Active_Timeout. It also checks if MEM_INFO_VALID\n> is set within 1 second. If not, return error. This is based on the\n> CXL spec 4.0 Tables 8-13.\n> \n> Add PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout\n> field encoding.\n> \n> cc: Kevin Tian \n\nCc is the correct form for this tag.\n\n> Suggested-by: Alex Williamson \n> Signed-off-by: Ankit Agrawal \n> ---\n> drivers/vfio/pci/nvgrace-gpu/main.c | 102 +++++++++++++++++++++++++---\n> include/uapi/linux/pci_regs.h | 1 +\n> 2 files changed, 95 insertions(+), 8 deletions(-)\n> \n> diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c\n> index fa056b69f899..81a725460112 100644\n> --- a/drivers/vfio/pci/nvgrace-gpu/main.c\n> +++ b/drivers/vfio/pci/nvgrace-gpu/main.c\n> @@ -3,6 +3,7 @@\n> * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved\n> */\n> \n> +#include \n> #include \n> #include \n> #include \n> @@ -64,6 +65,8 @@ struct nvgrace_gpu_pci_core_device {\n> \tbool has_mig_hw_bug;\n> \t/* GPU has just been reset */\n> \tbool reset_done;\n> +\t/* CXL Device DVSEC offset; 0 if not present (legacy GB path) */\n> +\tint cxl_dvsec;\n> };\n> \n> static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev)\n> @@ -242,7 +245,7 @@ static void nvgrace_gpu_close_device(struct vfio_device *core_vdev)\n> \tvfio_pci_core_close_device(core_vdev);\n> }\n> \n> -static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n> +static int nvgrace_gpu_wait_device_ready_legacy(void __iomem *io)\n> {\n> \tunsigned long timeout = jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS);\n> \n> @@ -256,6 +259,81 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n> \treturn -ETIME;\n> }\n> \n> +/*\n> + * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n> + * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n> + * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n> + * 101b-111b = reserved (clamped to 256s).\n> + */\n> +static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n> +{\n> +\treturn 1000UL << (2 * min_t(u8, timeout, 4));\n\nMSEC_PER_SEC\n\nAlso, don't forget to add include for units.h.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=TYehD2an;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52836-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"TYehD2an\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.21","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0PY53jvNz1yGt\n\tfor ; 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charset=US-ASCII"}},{"id":3679938,"web_url":"http://patchwork.ozlabs.org/comment/3679938/","msgid":"","list_archive_url":null,"date":"2026-04-21T15:13:06","subject":"Re: [PATCH v4 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","submitter":{"id":86155,"url":"http://patchwork.ozlabs.org/api/people/86155/","name":"Ankit Agrawal","email":"ankita@nvidia.com"},"content":"Thanks for the review Ilpo!\n\n>> + * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n>> + * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n>> + * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n>> + * 101b-111b = reserved (clamped to 256s).\n>> + */\n>> +static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n>> +{\n>> +     return 1000UL << (2 * min_t(u8, timeout, 4));\n>\n> MSEC_PER_SEC\n\nAck.\n\n> Also, don't forget to add include for units.h.\n\nSorry why do we need to do this? The MSEC_PER_SEC is getting included through\njiffies.h.\n\n> -- \n>  i.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ZOz07ajE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52851-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"ZOz07ajE\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.198.16","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0Qr45vZJz1yCv\n\tfor ; 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charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"SA1PR12MB7199.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n e6e01e1c-13e9-419f-5955-08de9fb87daa","X-MS-Exchange-CrossTenant-originalarrivaltime":"21 Apr 2026 15:13:06.3534\n (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n g+9GA6hJiG/H7BBEoe781wk06Ksbn4YmJcbs2STB7Ji5mGj8BfK/C+MnA1Jk5WuiHDmxAWHbBJKKaH5T4O9H5A==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS0PR12MB9323"}},{"id":3680607,"web_url":"http://patchwork.ozlabs.org/comment/3680607/","msgid":"","list_archive_url":null,"date":"2026-04-22T12:44:40","subject":"Re: [PATCH v4 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","submitter":{"id":83553,"url":"http://patchwork.ozlabs.org/api/people/83553/","name":"Ilpo Järvinen","email":"ilpo.jarvinen@linux.intel.com"},"content":"On Tue, 21 Apr 2026, Ankit Agrawal wrote:\n\n> Thanks for the review Ilpo!\n> \n> >> + * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n> >> + * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n> >> + * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n> >> + * 101b-111b = reserved (clamped to 256s).\n> >> + */\n> >> +static inline unsigned long cxl_mem_active_timeout_ms(u8 timeout)\n> >> +{\n> >> +     return 1000UL << (2 * min_t(u8, timeout, 4));\n> >\n> > MSEC_PER_SEC\n> \n> Ack.\n\nI didn't see this change in v5.\n\n> > Also, don't forget to add include for units.h.\n> \n> Sorry why do we need to do this? The MSEC_PER_SEC is getting included through\n> jiffies.h.\n\nSorry, I mixed from what header it comes from and it doesn't exactly \ncomes from jiffies.h either. If C files rely on indirect includes \nthrough other header, it makes painful to refactor headers.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=AtewZ49R;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52969-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"AtewZ49R\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.15","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0zd65J4Xz1yD5\n\tfor ; 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BOUNDARY=\"8323328-1664857874-1776861576=:1863\"","Content-ID":""}},{"id":3680640,"web_url":"http://patchwork.ozlabs.org/comment/3680640/","msgid":"","list_archive_url":null,"date":"2026-04-22T13:53:11","subject":"Re: [PATCH v4 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC","submitter":{"id":86155,"url":"http://patchwork.ozlabs.org/api/people/86155/","name":"Ankit Agrawal","email":"ankita@nvidia.com"},"content":"> I didn't see this change in v5.\n\nSorry I sent out the wrong version. Fixed in v6.\n\n> Sorry, I mixed from what header it comes from and it doesn't exactly \n> comes from jiffies.h either. If C files rely on indirect includes \n> through other header, it makes painful to refactor headers.\n\nAdded linux/time64.h. That is a one hop to vdso/time64.h. AIU\nvdso headers aren't meant to be included directly by drivers.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=LjELJeCQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52972-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"LjELJeCQ\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.46.37","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com","dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g110L0JT0z1yD5\n\tfor ; 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