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GET /api/1.1/patches/2225067/?format=api
{ "id": 2225067, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225067/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-5-biju.das.jz@bp.renesas.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420104332.153640-5-biju.das.jz@bp.renesas.com>", "date": "2026-04-20T10:43:21", "name": "[v5,4/9] pwm: rzg2l-gpt: Convert to waveform callbacks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dcf5e494a463185d4a4b331b267442da1de0e00e", "submitter": { "id": 87968, "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api", "name": "Biju", "email": "biju.das.au@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-5-biju.das.jz@bp.renesas.com/mbox/", "series": [ { "id": 500593, "url": "http://patchwork.ozlabs.org/api/1.1/series/500593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593", "date": "2026-04-20T10:43:17", "name": "Add Renesas RZ/G3E GPT support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225067/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225067/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pwm+bounces-8638-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com 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"X-Gm-Gg": "AeBDievrTWC4DuM2RF4ATllT/OHieFwUQpsTx08tpgUJid7S+Yg0KD1FmfDaS3CFlZH\n\t6JyrIrbGcntXqEwbVH1ivbcxUCMKMIiZ86z+Bwub7tY55Zp5VVWpJUui0SSwvvojY7ymvl/gJDh\n\t7H1ft3SUokq/BzdSSrFp3VzqeU+tFeCdoN/M3BL3mis5Me1YdATi7s7SEqYhbSTlid/G679+K+L\n\tgdFtuXEx01EaUCjTXkBsaf5RpN/wAMkg7RGajtdyAfWgqHovchePiASrlFUg0gysrg9fvv6OYki\n\todZ61J1jGTpyDG14W9Sd6eLlwdGhYibKQ9juRwE+ulcQk6VQxtafGXjz0Waojt3d7u1UndD/H0g\n\tIphhFbtCI6sD10Tm6iFaqFj3XSiGhA8srJjgPak4aGl4ySS6CYRaovhsayU4xkKV1iQWaHdLUh1\n\tlSoNYITonU9A9q9zNCJCiDzv5XvbPrpONrQ9v4MMZoKTaUvxLCIN6uGqrBc2Y=", "X-Received": "by 2002:a05:6000:2508:b0:43b:8f30:39bb with SMTP id\n ffacd0b85a97d-43fe3df1f30mr19587394f8f.24.1776681819118;\n Mon, 20 Apr 2026 03:43:39 -0700 (PDT)", "From": "Biju <biju.das.au@gmail.com>", "X-Google-Original-From": "Biju <biju.das.jz@bp.renesas.com>", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>", "Cc": "Biju Das <biju.das.jz@bp.renesas.com>,\n\tlinux-pwm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tGeert Uytterhoeven <geert+renesas@glider.be>,\n\tPrabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tBiju Das <biju.das.au@gmail.com>,\n\tlinux-renesas-soc@vger.kernel.org", "Subject": "[PATCH v5 4/9] pwm: rzg2l-gpt: Convert to waveform callbacks", "Date": "Mon, 20 Apr 2026 11:43:21 +0100", "Message-ID": "<20260420104332.153640-5-biju.das.jz@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260420104332.153640-1-biju.das.jz@bp.renesas.com>", "References": "<20260420104332.153640-1-biju.das.jz@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Biju Das <biju.das.jz@bp.renesas.com>\n\nMigrate the rzg2l-gpt driver from the legacy .get_state/.apply ops to the\nnew waveform callback interface.\n\nIntroduce struct rzg2l_gpt_waveform to represent a hardware waveform\nconfiguration holding the period register value (gtpr), compare/capture\nregister value (gtccr), and prescaler (prescale).\n\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv5:\n * Updated commit description.\n * Updated rzg2l_gpt_round_waveform_tohw() to initialize gtccr when the\n period of the second channel is smaller.\n * Replaced period_ticks with RZG2L_MAX_TICKS for the duty_ticks maximum\n value check in rzg2l_gpt_round_waveform_tohw().\nv4 from [1]\n[1] https://lore.kernel.org/all/20251208152133.269316-3-biju.das.jz@bp.renesas.com/\n---\n drivers/pwm/pwm-rzg2l-gpt.c | 197 ++++++++++++++++++++++--------------\n 1 file changed, 121 insertions(+), 76 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\nindex 659044fa3d2f..9e7a897a0b4d 100644\n--- a/drivers/pwm/pwm-rzg2l-gpt.c\n+++ b/drivers/pwm/pwm-rzg2l-gpt.c\n@@ -100,6 +100,13 @@ struct rzg2l_gpt_chip {\n \tDECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);\n };\n \n+/* This represents a hardware configuration for one channel */\n+struct rzg2l_gpt_waveform {\n+\tu32 gtpr;\n+\tu32 gtccr;\n+\tu8 prescale;\n+};\n+\n static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)\n {\n \treturn pwmchip_get_drvdata(chip);\n@@ -166,7 +173,8 @@ static void rzg2l_gpt_free(struct pwm_chip *chip, struct pwm_device *pwm)\n \trzg2l_gpt->channel_request_count[ch]--;\n }\n \n-static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)\n+static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm,\n+\t\t\t\t u32 *gtcr)\n {\n \tu8 ch = RZG2L_GET_CH(hwpwm);\n \tu32 val;\n@@ -175,6 +183,9 @@ static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)\n \tif (!(val & RZG2L_GTCR_CST))\n \t\treturn false;\n \n+\tif (gtcr)\n+\t\t*gtcr = val;\n+\n \tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch));\n \n \treturn val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm));\n@@ -233,54 +244,38 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n \treturn DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);\n }\n \n-static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *pwm,\n-\t\t\t struct pwm_state *state)\n-{\n-\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n-\n-\tstate->enabled = rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm);\n-\tif (state->enabled) {\n-\t\tu32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n-\t\tu32 ch = RZG2L_GET_CH(pwm->hwpwm);\n-\t\tu8 prescale;\n-\t\tu32 val;\n-\n-\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));\n-\t\tprescale = FIELD_GET(RZG2L_GTCR_TPCS, val);\n-\n-\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));\n-\t\tstate->period = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);\n-\n-\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));\n-\t\tstate->duty_cycle = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);\n-\t\tif (state->duty_cycle > state->period)\n-\t\t\tstate->duty_cycle = state->period;\n-\t}\n-\n-\tstate->polarity = PWM_POLARITY_NORMAL;\n-\n-\treturn 0;\n-}\n-\n static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)\n {\n \treturn min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),\n \t\t U32_MAX);\n }\n \n-/* Caller holds the lock while calling rzg2l_gpt_config() */\n-static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n-\t\t\t const struct pwm_state *state)\n+static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n+\t\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t\t const struct pwm_waveform *wf,\n+\t\t\t\t\t void *_wfhw)\n+\n {\n \tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n-\tu8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n+\tstruct rzg2l_gpt_waveform *wfhw = _wfhw;\n+\tbool is_small_second_period = false;\n \tu8 ch = RZG2L_GET_CH(pwm->hwpwm);\n \tu64 period_ticks, duty_ticks;\n \tunsigned long pv, dc;\n-\tu8 prescale;\n+\n+\tguard(mutex)(&rzg2l_gpt->lock);\n+\tif (wf->period_length_ns == 0) {\n+\t\t*wfhw = (struct rzg2l_gpt_waveform){\n+\t\t\t.gtpr = 0,\n+\t\t\t.gtccr = 0,\n+\t\t\t.prescale = 0,\n+\t\t};\n+\n+\t\treturn 0;\n+\t}\n \n \t/* Limit period/duty cycle to max value supported by the HW */\n-\tperiod_ticks = mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n+\tperiod_ticks = mul_u64_u64_div_u64(wf->period_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n \tif (period_ticks > RZG2L_MAX_TICKS)\n \t\tperiod_ticks = RZG2L_MAX_TICKS;\n \t/*\n@@ -291,21 +286,26 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \tif (rzg2l_gpt->channel_request_count[ch] > 1) {\n \t\tu8 sibling_ch = rzg2l_gpt_sibling(pwm->hwpwm);\n \n-\t\tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch)) {\n+\t\tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch, NULL)) {\n \t\t\tif (period_ticks < rzg2l_gpt->period_ticks[ch])\n-\t\t\t\treturn -EBUSY;\n+\t\t\t\tis_small_second_period = true;\n \n \t\t\tperiod_ticks = rzg2l_gpt->period_ticks[ch];\n \t\t}\n \t}\n \n-\tprescale = rzg2l_gpt_calculate_prescale(period_ticks);\n-\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale);\n+\twfhw->prescale = rzg2l_gpt_calculate_prescale(period_ticks);\n+\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);\n+\twfhw->gtpr = pv;\n+\twfhw->gtccr = 0;\n+\tif (is_small_second_period)\n+\t\treturn 1;\n \n-\tduty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n-\tif (duty_ticks > period_ticks)\n-\t\tduty_ticks = period_ticks;\n-\tdc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);\n+\tduty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n+\tif (duty_ticks > RZG2L_MAX_TICKS)\n+\t\tduty_ticks = RZG2L_MAX_TICKS;\n+\tdc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);\n+\twfhw->gtccr = dc;\n \n \t/*\n \t * GPT counter is shared by multiple channels, we cache the period ticks\n@@ -314,6 +314,61 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t */\n \trzg2l_gpt->period_ticks[ch] = period_ticks;\n \n+\treturn 0;\n+}\n+\n+static int rzg2l_gpt_round_waveform_fromhw(struct pwm_chip *chip,\n+\t\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t\t const void *_wfhw,\n+\t\t\t\t\t struct pwm_waveform *wf)\n+{\n+\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n+\tconst struct rzg2l_gpt_waveform *wfhw = _wfhw;\n+\n+\twf->period_length_ns = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw->gtpr,\n+\t\t\t\t\t\t\t\t wfhw->prescale);\n+\twf->duty_length_ns = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw->gtccr,\n+\t\t\t\t\t\t\t\twfhw->prescale);\n+\twf->duty_offset_ns = 0;\n+\n+\treturn 0;\n+}\n+\n+static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,\n+\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t void *_wfhw)\n+{\n+\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n+\tstruct rzg2l_gpt_waveform *wfhw = _wfhw;\n+\tu32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n+\tu32 ch = RZG2L_GET_CH(pwm->hwpwm);\n+\tu32 gtcr;\n+\n+\tguard(mutex)(&rzg2l_gpt->lock);\n+\tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) {\n+\t\twfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);\n+\t\twfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));\n+\t\twfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));\n+\t\tif (wfhw->gtccr > wfhw->gtpr)\n+\t\t\twfhw->gtccr = wfhw->gtpr;\n+\t} else {\n+\t\t*wfhw = (struct rzg2l_gpt_waveform) { };\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,\n+\t\t\t\t struct pwm_device *pwm,\n+\t\t\t\t const void *_wfhw)\n+{\n+\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n+\tconst struct rzg2l_gpt_waveform *wfhw = _wfhw;\n+\tu8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n+\tu8 ch = RZG2L_GET_CH(pwm->hwpwm);\n+\tu32 gptr;\n+\n+\tguard(mutex)(&rzg2l_gpt->lock);\n \t/*\n \t * Counter must be stopped before modifying mode, prescaler, timer\n \t * counter and buffer enable registers. These registers are shared\n@@ -332,14 +387,20 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n \t\t/* Select count clock */\n \t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,\n-\t\t\t\t FIELD_PREP(RZG2L_GTCR_TPCS, prescale));\n+\t\t\t\t FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));\n \n \t\t/* Set period */\n-\t\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv);\n+\t\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);\n+\t} else {\n+\t\tif (wfhw->gtpr) {\n+\t\t\tgptr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));\n+\t\t\tif (wfhw->gtpr < gptr)\n+\t\t\t\treturn -EBUSY;\n+\t\t}\n \t}\n \n \t/* Set duty cycle */\n-\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc);\n+\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), wfhw->gtccr);\n \n \tif (rzg2l_gpt->channel_enable_count[ch] <= 1) {\n \t\t/* Set initial value for counter */\n@@ -348,44 +409,28 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t\t/* Set no buffer operation */\n \t\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0);\n \n-\t\t/* Restart the counter after updating the registers */\n-\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),\n-\t\t\t\t RZG2L_GTCR_CST, RZG2L_GTCR_CST);\n+\t\tif (wfhw->gtpr)\n+\t\t\t/* Restart the counter after updating the registers */\n+\t\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch),\n+\t\t\t\t\t RZG2L_GTCR_CST, RZG2L_GTCR_CST);\n \t}\n \n-\treturn 0;\n-}\n-\n-static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm,\n-\t\t\t const struct pwm_state *state)\n-{\n-\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n-\tbool enabled = pwm->state.enabled;\n-\tint ret;\n-\n-\tif (state->polarity != PWM_POLARITY_NORMAL)\n-\t\treturn -EINVAL;\n-\n-\tguard(mutex)(&rzg2l_gpt->lock);\n-\tif (!state->enabled) {\n-\t\tif (enabled)\n-\t\t\trzg2l_gpt_disable(rzg2l_gpt, pwm);\n-\n-\t\treturn 0;\n-\t}\n-\n-\tret = rzg2l_gpt_config(chip, pwm, state);\n-\tif (!ret && !enabled)\n+\tif (wfhw->gtpr && !rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NULL))\n \t\trzg2l_gpt_enable(rzg2l_gpt, pwm);\n+\telse if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NULL))\n+\t\trzg2l_gpt_disable(rzg2l_gpt, pwm);\n \n-\treturn ret;\n+\treturn 0;\n }\n \n static const struct pwm_ops rzg2l_gpt_ops = {\n \t.request = rzg2l_gpt_request,\n \t.free = rzg2l_gpt_free,\n-\t.get_state = rzg2l_gpt_get_state,\n-\t.apply = rzg2l_gpt_apply,\n+\t.sizeof_wfhw = sizeof(struct rzg2l_gpt_waveform),\n+\t.round_waveform_tohw = rzg2l_gpt_round_waveform_tohw,\n+\t.round_waveform_fromhw = rzg2l_gpt_round_waveform_fromhw,\n+\t.read_waveform = rzg2l_gpt_read_waveform,\n+\t.write_waveform = rzg2l_gpt_write_waveform,\n };\n \n /*\n", "prefixes": [ "v5", "4/9" ] }