[{"id":3679507,"web_url":"http://patchwork.ozlabs.org/comment/3679507/","msgid":"","list_archive_url":null,"date":"2026-04-20T17:55:07","subject":"RE: [PATCH v5 4/9] pwm: rzg2l-gpt: Convert to waveform callbacks","submitter":{"id":91755,"url":"http://patchwork.ozlabs.org/api/people/91755/","name":"Cosmin-Gabriel Tanislav","email":"cosmin-gabriel.tanislav.xa@renesas.com"},"content":"> -----Original Message-----\n> From: Biju\n> Sent: Monday, April 20, 2026 1:43 PM\n> To: Uwe Kleine-König \n> Cc: Biju Das ; linux-pwm@vger.kernel.org; linux-kernel@vger.kernel.org;\n> Geert Uytterhoeven ; Prabhakar Mahadev Lad lad.rj@bp.renesas.com>; Biju Das ; linux-renesas-soc@vger.kernel.org\n> Subject: [PATCH v5 4/9] pwm: rzg2l-gpt: Convert to waveform callbacks\n> \n> From: Biju Das \n> \n> Migrate the rzg2l-gpt driver from the legacy .get_state/.apply ops to the\n> new waveform callback interface.\n> \n> Introduce struct rzg2l_gpt_waveform to represent a hardware waveform\n> configuration holding the period register value (gtpr), compare/capture\n> register value (gtccr), and prescaler (prescale).\n> \n> Signed-off-by: Biju Das \n> ---\n> v5:\n> * Updated commit description.\n> * Updated rzg2l_gpt_round_waveform_tohw() to initialize gtccr when the\n> period of the second channel is smaller.\n> * Replaced period_ticks with RZG2L_MAX_TICKS for the duty_ticks maximum\n> value check in rzg2l_gpt_round_waveform_tohw().\n> v4 from [1]\n> [1] https://lore.kernel.org/all/20251208152133.269316-3-biju.das.jz@bp.renesas.com/\n> ---\n> drivers/pwm/pwm-rzg2l-gpt.c | 197 ++++++++++++++++++++++--------------\n> 1 file changed, 121 insertions(+), 76 deletions(-)\n> \n> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\n> index 659044fa3d2f..9e7a897a0b4d 100644\n> --- a/drivers/pwm/pwm-rzg2l-gpt.c\n> +++ b/drivers/pwm/pwm-rzg2l-gpt.c\n> @@ -100,6 +100,13 @@ struct rzg2l_gpt_chip {\n> \tDECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);\n> };\n> \n> +/* This represents a hardware configuration for one channel */\n> +struct rzg2l_gpt_waveform {\n> +\tu32 gtpr;\n> +\tu32 gtccr;\n> +\tu8 prescale;\n> +};\n> +\n> static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)\n> {\n> \treturn pwmchip_get_drvdata(chip);\n> @@ -166,7 +173,8 @@ static void rzg2l_gpt_free(struct pwm_chip *chip, struct pwm_device *pwm)\n> \trzg2l_gpt->channel_request_count[ch]--;\n> }\n> \n> -static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)\n> +static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm,\n> +\t\t\t\t u32 *gtcr)\n> {\n> \tu8 ch = RZG2L_GET_CH(hwpwm);\n> \tu32 val;\n> @@ -175,6 +183,9 @@ static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 hwpwm)\n> \tif (!(val & RZG2L_GTCR_CST))\n> \t\treturn false;\n> \n> +\tif (gtcr)\n> +\t\t*gtcr = val;\n> +\n> \tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch));\n> \n> \treturn val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm));\n> @@ -233,54 +244,38 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,\n> \treturn DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);\n> }\n> \n> -static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *pwm,\n> -\t\t\t struct pwm_state *state)\n> -{\n> -\tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n> -\n> -\tstate->enabled = rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm);\n> -\tif (state->enabled) {\n> -\t\tu32 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n> -\t\tu32 ch = RZG2L_GET_CH(pwm->hwpwm);\n> -\t\tu8 prescale;\n> -\t\tu32 val;\n> -\n> -\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));\n> -\t\tprescale = FIELD_GET(RZG2L_GTCR_TPCS, val);\n> -\n> -\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));\n> -\t\tstate->period = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);\n> -\n> -\t\tval = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));\n> -\t\tstate->duty_cycle = rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, prescale);\n> -\t\tif (state->duty_cycle > state->period)\n> -\t\t\tstate->duty_cycle = state->period;\n> -\t}\n> -\n> -\tstate->polarity = PWM_POLARITY_NORMAL;\n> -\n> -\treturn 0;\n> -}\n> -\n> static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)\n> {\n> \treturn min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),\n> \t\t U32_MAX);\n> }\n> \n> -/* Caller holds the lock while calling rzg2l_gpt_config() */\n> -static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> -\t\t\t const struct pwm_state *state)\n> +static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,\n> +\t\t\t\t\t struct pwm_device *pwm,\n> +\t\t\t\t\t const struct pwm_waveform *wf,\n> +\t\t\t\t\t void *_wfhw)\n> +\n> {\n> \tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n> -\tu8 sub_ch = rzg2l_gpt_subchannel(pwm->hwpwm);\n> +\tstruct rzg2l_gpt_waveform *wfhw = _wfhw;\n> +\tbool is_small_second_period = false;\n> \tu8 ch = RZG2L_GET_CH(pwm->hwpwm);\n> \tu64 period_ticks, duty_ticks;\n> \tunsigned long pv, dc;\n> -\tu8 prescale;\n> +\n> +\tguard(mutex)(&rzg2l_gpt->lock);\n> +\tif (wf->period_length_ns == 0) {\n> +\t\t*wfhw = (struct rzg2l_gpt_waveform){\n> +\t\t\t.gtpr = 0,\n> +\t\t\t.gtccr = 0,\n> +\t\t\t.prescale = 0,\n> +\t\t};\n> +\n> +\t\treturn 0;\n> +\t}\n> \n> \t/* Limit period/duty cycle to max value supported by the HW */\n> -\tperiod_ticks = mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n> +\tperiod_ticks = mul_u64_u64_div_u64(wf->period_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n> \tif (period_ticks > RZG2L_MAX_TICKS)\n> \t\tperiod_ticks = RZG2L_MAX_TICKS;\n> \t/*\n> @@ -291,21 +286,26 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> \tif (rzg2l_gpt->channel_request_count[ch] > 1) {\n> \t\tu8 sibling_ch = rzg2l_gpt_sibling(pwm->hwpwm);\n> \n> -\t\tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch)) {\n> +\t\tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, sibling_ch, NULL)) {\n> \t\t\tif (period_ticks < rzg2l_gpt->period_ticks[ch])\n> -\t\t\t\treturn -EBUSY;\n> +\t\t\t\tis_small_second_period = true;\n> \n> \t\t\tperiod_ticks = rzg2l_gpt->period_ticks[ch];\n> \t\t}\n> \t}\n> \n> -\tprescale = rzg2l_gpt_calculate_prescale(period_ticks);\n> -\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale);\n> +\twfhw->prescale = rzg2l_gpt_calculate_prescale(period_ticks);\n> +\tpv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);\n> +\twfhw->gtpr = pv;\n> +\twfhw->gtccr = 0;\n> +\tif (is_small_second_period)\n> +\t\treturn 1;\n> \n> -\tduty_ticks = mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n> -\tif (duty_ticks > period_ticks)\n> -\t\tduty_ticks = period_ticks;\n> -\tdc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale);\n> +\tduty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);\n> +\tif (duty_ticks > RZG2L_MAX_TICKS)\n> +\t\tduty_ticks = RZG2L_MAX_TICKS;\n\nI know this change from > period_ticks to > RZG2L_MAX_TICKS has been\nsuggested by you, Uwe, but is this correct if period_ticks was set to a\nsmaller value in the earlier sibling channel condition?\n\nIn that case I think it might be possible for duty_ticks to end up\nlarger than period_ticks which wouldn't work correctly with the\n> RZG2L_MAX_TICKS check, but would have been clamped fine using the\nother check.\n\nWhat do you think?\n\n> +\tdc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);\n> +\twfhw->gtccr = dc;\n\nIs there any reason why the results of rzg2l_gpt_calculate_pv_or_dc()\ncannot be assigned to wfhw->gtpr and wfhw->gtccr directly?\n\nThat would get rid of the pv and dc variables as we do not need them\nfor anything else anymore, as far as I can tell.\n\n> \n> \t/*\n> \t * GPT counter is shared by multiple channels, we cache the period ticks\n> @@ -314,6 +314,61 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,\n> \t */\n> \trzg2l_gpt->period_ticks[ch] = period_ticks;\n> \n\nThis should be part of rzg2l_gpt_write_waveform().\n\nOtherwise, if pwm_round_waveform_might_sleep() is called without \npwm_set_waveform_might_sleep() being called immediately after with the\nrounded waveform, the software state will become out of sync with the\nhardware state.\n\nUwe, what's your take on this?\n\n> +\treturn 0;\n> +}\n> +","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=renesas.com header.i=@renesas.com header.a=rsa-sha256\n header.s=selector1 header.b=EqouQclz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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