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GET /api/1.1/patches/2224758/?format=api
{ "id": 2224758, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2224758/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260418084253.792395-1-wuweimin@huaqin.corp-partner.google.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/1.1/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260418084253.792395-1-wuweimin@huaqin.corp-partner.google.com>", "date": "2026-04-18T08:42:53", "name": "[v3] mtd: spi-nor: gigadevice: Add support for GD25LQ255E", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "95dbfa27e905cd817c85ede5db830a46def8f900", "submitter": { "id": 92637, "url": "http://patchwork.ozlabs.org/api/1.1/people/92637/?format=api", "name": "Weimin Wu", "email": "wuweimin@huaqin.corp-partner.google.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260418084253.792395-1-wuweimin@huaqin.corp-partner.google.com/mbox/", "series": [ { "id": 500429, "url": "http://patchwork.ozlabs.org/api/1.1/series/500429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=500429", "date": "2026-04-18T08:42:53", "name": "[v3] mtd: spi-nor: gigadevice: Add support for GD25LQ255E", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224758/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224758/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=tBhWJrSL;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=huaqin-corp-partner-google-com.20251104.gappssmtp.com\n header.i=@huaqin-corp-partner-google-com.20251104.gappssmtp.com\n header.a=rsa-sha256 header.s=20251104 header.b=sJ+dYHWG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=temperror (SPF Temporary Error: DNS Timeout)\n smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133;\n helo=bombadil.infradead.org;\n envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fyQKs2b5Dz1y1V\n\tfor <incoming@patchwork.ozlabs.org>; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Add support for the GigaDevice GD25LQ255E (JEDEC ID c8 60\n 19),\n a 256Mbit (32MB) SPI NOR flash chip which supports SFDP. The chip supports\n 4K sector erase, dual read,\n and quad read modes. Link: https://download.gigadevice.com/Datasheet/DS-00562-GD25LQ255E-Rev1.2.pdf \n Content analysis details: (-1.9 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:430 listed in]\n [list.dnswl.org]", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Add support for the GigaDevice GD25LQ255E (JEDEC ID c8 60 19),\na 256Mbit (32MB) SPI NOR flash chip which supports SFDP.\n\nThe chip supports 4K sector erase, dual read, and quad read modes.\n\nLink: https://download.gigadevice.com/Datasheet/DS-00562-GD25LQ255E-Rev1.2.pdf\n\nWithout this patch, The WP status cannot be obtained using flashrom:\ndevice:/ # flashrom --wp-status\n...\nlinux_mtd_wp_read_cfg:\nioctl: Operation not supported on transport endpoint\nFailed to get WP status: failed to read the current WP configuration\n\nand with this patch:\ndevice:/ # flashrom --wp-status\n...\nProtection range: start=0x00000000 length=0x00000000 (none)\nProtection mode: disabled\nSUCCESS\n\nSigned-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>\n\n---\nChanges in v3:\n- Add SPI_NOR_4BIT_BP and SPI_NOR_TB_SR_BIT6 flag bits.\n- Add /* gd25lb256 */ comment.\n- Link to v2: https://patchwork.ozlabs.org/project/linux-mtd/patch/20260313133806.2390946-1-wuweimin@huaqin.corp-partner.google.com/\n- Link to v1: https://patchwork.ozlabs.org/project/linux-mtd/patch/20260213144133.1778932-1-wuweimin@huaqin.corp-partner.google.com/\n\nRefer to the following documents:\nhttps://docs.kernel.org/driver-api/mtd/spi-nor.html#minimum-testing-requirements\n\n1. Specify the controller that you used to test the flash and specify the frequency at which the flash was operated:\n\nThis flash memory has been successfully tested at 100Mhz frequency on a Chromebook device running the Intel Patherlake platform, which is currently under development.\n\n2. Dump the sysfs entries and print the md5/sha1/sha256 SFDP checksum:\nroot:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/partname\ncat: /sys/bus/spi/devices/spi0.0/spi-nor/partname: No such file or directory\n\nroot:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id\nc86019\n\nroot:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer\ngigadevice\n\nroot:/ # xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp\n53464450070102ff00070114300000ffc8000103900000ff84010102c000\n00ffffffffffffffffffffffffffffffffffe520fbffffffff0f44eb086b\n083b80bbfeffffffffff00ffffff42eb0c200f5210d800ffd4299dfe84d2\n14c7ec6316337a757a7507b3d55c190614ff885018010000000000008800\n00000000f6f5ffffffffffffffffffffffffffffffffffff002050169ff9\n7764fc8bffffffffffffffffffffffffffffffffffffffffffffffffffff\nffffffffffffffffffffffffff8e00fe215cdcff\n\nroot:/ # sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp\n09f61fe623df200d86b4ab47c48e3a13718fadbb450fcd430b3cdc49a902b1f6 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp\n\n3. Dump debugfs data:\nroot:/ # cat /sys/kernel/debug/spi-nor/spi0.0/capabilities\nSupported read modes by the flash\n 1S-1S-1S\n opcode\t0x13\n mode cycles\t0\n dummy cycles\t0\n 1S-1S-1S (fast read)\n opcode\t0x0c\n mode cycles\t0\n dummy cycles\t8\n 1S-1S-2S\n opcode\t0x3c\n mode cycles\t0\n dummy cycles\t8\n 1S-2S-2S\n opcode\t0xbc\n mode cycles\t4\n dummy cycles\t0\n 1S-1S-4S\n opcode\t0x6c\n mode cycles\t0\n dummy cycles\t8\n 1S-4S-4S\n opcode\t0xec\n mode cycles\t2\n dummy cycles\t4\n 4S-4S-4S\n opcode\t0xec\n mode cycles\t2\n dummy cycles\t2\n\nSupported page program modes by the flash\n 1S-1S-1S\n opcode\t0x12\n 1S-1S-4S\n opcode\t0x34\n\nroot:/ # cat /sys/kernel/debug/spi-nor/spi0.0/params\nname\t\t(null)\nid\t\tc8 60 19 c8 60 19\nsize\t\t32.0 MiB\nwrite size\t1\npage size\t256\naddress nbytes\t4\nflags\t\tHAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | NO_READ_CR | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET\n\nopcodes\n read\t\t0x0c\n dummy cycles\t8\n erase\t\t0xdc\n program\t0x12\n 8D extension\trepeat\n\nprotocols\n read\t\t1S-1S-1S\n write\t\t1S-1S-1S\n register\t1S-1S-1S\n\nerase commands\n 21 (4.00 KiB) [1]\n 5c (32.0 KiB) [2]\n dc (64.0 KiB) [3]\n c7 (32.0 MiB)\n\nsector map\n region (in hex) | erase mask | overlaid\n ------------------+------------+----------\n 00000000-01ffffff | [ 3] | no\nroot:/ # cat /sys/bus/spi/devices/spi0.0/\ndriver/ mtd/ statistics/ uevent\ndriver_override power/ subsystem/\nmodalias spi-nor/ supplier:regulator:regulator.0/\nroot:/ # cat /sys/bus/spi/devices/spi0.0/s\nspi-nor/ statistics/ subsystem/ supplier:regulator:regulator.0/\nroot:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/\njedec_id manufacturer sfdp\nroot:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/\n\n4. Use mtd-utils and verify that erase, read and page program operations work fine:\nBecause Chromebooks lack the necessary mtd-utils directives, the corresponding data cannot be provided.\n---\n---\n drivers/mtd/spi-nor/gigadevice.c | 4 ++++\n 1 file changed, 4 insertions(+)", "diff": "diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c\nindex ef1edd0ad..22a430798 100644\n--- a/drivers/mtd/spi-nor/gigadevice.c\n+++ b/drivers/mtd/spi-nor/gigadevice.c\n@@ -82,6 +82,10 @@ static const struct flash_info gigadevice_nor_parts[] = {\n \t\t.size = SZ_16M,\n \t\t.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,\n \t\t.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,\n+\t}, {\n+\t\t/* gd25lb256 */\n+\t\t.id = SNOR_ID(0xc8, 0x60, 0x19),\n+\t\t.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,\n \t},\n };\n \n", "prefixes": [ "v3" ] }