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GET /api/1.1/patches/2224044/?format=api
{ "id": 2224044, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2224044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416165353.589569-2-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260416165353.589569-2-peter.maydell@linaro.org>", "date": "2026-04-16T16:53:51", "name": "[v2,1/3] target/arm: Clear AArch64 ID regs from ARMISARegisters if AArch64 disabled", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ac1b3d186d8f7a8461b13324bbe28e660c0b073", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416165353.589569-2-peter.maydell@linaro.org/mbox/", "series": [ { "id": 500185, "url": "http://patchwork.ozlabs.org/api/1.1/series/500185/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500185", "date": "2026-04-16T16:53:50", "name": "target/arm: Allow aarch64=off for TCG", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500185/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224044/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224044/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Zkm0edQi;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxPJt2dCQz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 02:55:26 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDPyg-00069v-Ks; Thu, 16 Apr 2026 12:54:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDPyf-00069C-7R\n for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:05 -0400", "from mail-wm1-x329.google.com ([2a00:1450:4864:20::329])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDPyd-0007c5-AF\n for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:04 -0400", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-4888375f735so82359885e9.3\n for <qemu-devel@nongnu.org>; Thu, 16 Apr 2026 09:54:02 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-488fa79d476sm473035e9.1.2026.04.16.09.53.57\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 16 Apr 2026 09:53:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776358441; x=1776963241; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=f1oPHbQSPRM9BqIW/R6wbhEyiBfOJFdGBhv8oIagU3w=;\n b=Zkm0edQiNVN9NZLd/+nC44tpaY9Nt5+TybHzdzome3Dvs33dvVD7G1Wwca9bfcYXMp\n PBOM3hQcabO+///LW/pm6RpIFXpVqqV6vfvTPBMMdOES0HnRj1zK/LPHVED7kUumCWFb\n v9OqrNbdh2wAycZilXXiNZNyyrasR/eWtJbpvTxdo6GqioFA3V4LNrb37ShA8VBRj7r4\n Ksdgk/PLtQCjkTiexnjp0Xq33Jo3opGo8Q5qFcGK4Prj7b5+248ygNdoFfoFpoyYjj88\n E8MNHGrUHeUtoqAPoGn2rrqb3esz9eLyvRCXYja3PrJo+fn1hk8J5qBfp8pv/rGD7QWq\n Mlbg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776358441; x=1776963241;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=f1oPHbQSPRM9BqIW/R6wbhEyiBfOJFdGBhv8oIagU3w=;\n b=B1CS0qv2Xiw15pUJVRbWqATDF4eJFFludySBJJwO4E2O7NJNrMRGuDusyElVM2XGac\n uprL08Y5svB5JAtkBVq/NnShx8/bMMK0OHV2gb0eVWZwSt9sah5MTaknjZ4pHdEPgXDy\n AmHoZT5Zo+somKzEmnBpwBcxETS7f3rjOTliYCJWnUQglIdid56tmS8TU/Ijft12qCMb\n j5n0ifuIUtjE4Cai9muV4r7CX75ckJw2wAIwgfwuTOLwWSaofIUJCaJpP5rF5jX++J2u\n F7LC3pw1QzjviDGVA9/XppEOOJnoPBl3xegg1X2OsVD6lKXlb+EEp4w0OCBqnTvQyG0E\n MCYA==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ/0nKrFhG/icVRHIk006IVKKBhGFvNGch0LYJmIQtVw9HqjDih+l9Ow1d5GHB/3A7M+GLPkFBQ4FYhQ@nongnu.org", "X-Gm-Message-State": "AOJu0Yznv7wT/CzQKNrZBZh1nVHh/28srucmFJAL10Zn30Z22YcQ3j4p\n axED+iLknGHPis7c0+SVJeOHFl5YoujP+cJy5pWdNDadAa+IgGiZISj73NXZ85N5n+6bVHDQL4w\n AqkoKD5Y=", "X-Gm-Gg": "AeBDievFTSw8/EaKWPFVWyIwf0eNvAbuLQpirOSFCflNR3Ij39MSXC5IyWKxiAqR8Aa\n a+pYQL+paoqQbkmX0DnKxx26IV96r8fqIYVr40djkhKupHXbFz7LinUQshH2yrC8NmQf2zoIEkC\n vOA7g9uTClEtsukamg5yGRKF6qaiDB908STXVM/EuptWQm4uaqsFGaiQmszEOIzMZ/y6BBbfszF\n NS4PTIhEUxE2+LY+5+AMKfwJpNH6PzMKMBunYxxwpkDyymw6TrLtqfI2Py1C+SDkthZxlBpiKMN\n /XRApSbwoGzWzUpgPqTMta6xcqN2K/o5GK0Lf1Tzopk08N2JbQwyD3YrSV/emRSJ47BXW25Z7mq\n oQ1cvOAnC89Q4XBm07PCeAbr2rXdS6Z2ZskASEh7z4o0x1BWWvSFFAdsUG9LmSyv+nQUaJQRPGy\n LsKugu7YF5MF+ld3+KKQwrq7F5QQ6SCGguqZ208dbm7DgVtt2iJxeB5JK4Op8btlTRDALciWJ8I\n x5nB8/KBjuYyPdxNHt8kbGNXD9stxr0+puLFOfQbg==", "X-Received": "by 2002:a05:600c:6994:b0:485:3eba:ab96 with SMTP id\n 5b1f17b1804b1-488d67bbcbamr381815095e9.3.1776358440828;\n Thu, 16 Apr 2026 09:54:00 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Cl=C3=A9ment?=\n\t=?utf-8?q?_Chigot?= <chigot@adacore.com>", "Subject": "[PATCH v2 1/3] target/arm: Clear AArch64 ID regs from ARMISARegisters\n if AArch64 disabled", "Date": "Thu, 16 Apr 2026 17:53:51 +0100", "Message-ID": "<20260416165353.589569-2-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260416165353.589569-1-peter.maydell@linaro.org>", "References": "<20260416165353.589569-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::329;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "If we create a normally-AArch64 CPU and configure it with\naarch64=off, this will by default leave all the AArch64 ID register\nvalues in its ARMISARegisters struct untouched. That in turn means\nthat tests of cpu_isar_feature(aa64_something, cpu) will return true.\n\nUntil now we have had a design policy that you shouldn't check an\naa64_ feature unless you know that the CPU has AArch64; but this is\nquite fragile as it's easy to forget and only causes a problem in the\ncorner case where AArch64 was turned off. In particular, when we\nextend the ability to disable AArch64 from only KVM to also TCG there\nare many more aa64 feature check points which we would otherwise have\nto audit for whether they needed to be guarded with a check on\nARM_FEATURE_AARCH64.\n\nInstead, make the CPU realize function zero out all the 64-bit ID\nregisters if a TCG CPU doesn't have AArch64; this will make aa64_\nfeature tests generally return false.\n\nWe only do this for TCG because only TCG really needs it, and for\nKVM it might be confusing to have QEMU's idea of the ID registers\nbe different from KVM's.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\nv1->v2: limit scope of register clearing to TCG, as I suggested\nafter posting and testing the v1 version:\n https://patchew.org/QEMU/20251002101648.2455374-1-peter.maydell@linaro.org/20251002101648.2455374-2-peter.maydell@linaro.org/\n---\n target/arm/cpu.c | 35 +++++++++++++++++++++++++++++++++++\n target/arm/cpu.h | 3 ++-\n 2 files changed, 37 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex ccc47c8a9a..11d3437843 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1610,6 +1610,27 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)\n }\n }\n \n+static void arm_clear_aarch64_idregs(ARMCPU *cpu)\n+{\n+ /* Zero out all the AArch64 ID registers in ARMISARegisters */\n+ SET_IDREG(&cpu->isar, ID_AA64ISAR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64ISAR1, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64ISAR2, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64PFR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64PFR1, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64PFR2, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64MMFR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64MMFR1, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64MMFR2, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64MMFR3, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64DFR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64DFR1, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64AFR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64AFR1, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);\n+ SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);\n+}\n+\n static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n {\n CPUState *cs = CPU(dev);\n@@ -1737,6 +1758,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n }\n #endif\n \n+ /*\n+ * A TCG aarch64=off CPU has no AArch64 at all, so we clear out the\n+ * ID registers to avoid cpu_isar_feature(aa64_something, cpu) tests\n+ * incorrectly returning true. We don't do this for other accelerators\n+ * (which in practice means \"for KVM\", since no others have AArch32\n+ * guest support) because from KVM's point of view the AArch64 ID\n+ * registers still exist and must have their correct values. So we\n+ * avoid clearing them out so that we don't have QEMU and KVM with\n+ * different ideas of the ID registers.\n+ */\n+ if (tcg_enabled() && !arm_feature(env, ARM_FEATURE_AARCH64)) {\n+ arm_clear_aarch64_idregs(cpu);\n+ }\n+\n #ifdef CONFIG_USER_ONLY\n /*\n * User mode relies on IC IVAU instructions to catch modification of\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 657ff4ab20..ab6bacf4aa 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1080,7 +1080,8 @@ struct ArchCPU {\n * Note that if you add an ID register to the ARMISARegisters struct\n * you need to also update the 32-bit and 64-bit versions of the\n * kvm_arm_get_host_cpu_features() function to correctly populate the\n- * field by reading the value from the KVM vCPU.\n+ * field by reading the value from the KVM vCPU. If it is an AArch64\n+ * ID register then you also must update arm_clear_aarch64_idregs().\n */\n struct ARMISARegisters {\n uint32_t mvfr0;\n", "prefixes": [ "v2", "1/3" ] }