[{"id":3678355,"web_url":"http://patchwork.ozlabs.org/comment/3678355/","msgid":"","list_archive_url":null,"date":"2026-04-16T19:52:55","subject":"Re: [PATCH v2 1/3] target/arm: Clear AArch64 ID regs from\n ARMISARegisters if AArch64 disabled","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 16/4/26 18:53, Peter Maydell wrote:\n> If we create a normally-AArch64 CPU and configure it with\n> aarch64=off, this will by default leave all the AArch64 ID register\n> values in its ARMISARegisters struct untouched. That in turn means\n> that tests of cpu_isar_feature(aa64_something, cpu) will return true.\n> \n> Until now we have had a design policy that you shouldn't check an\n> aa64_ feature unless you know that the CPU has AArch64; but this is\n> quite fragile as it's easy to forget and only causes a problem in the\n> corner case where AArch64 was turned off. In particular, when we\n> extend the ability to disable AArch64 from only KVM to also TCG there\n> are many more aa64 feature check points which we would otherwise have\n> to audit for whether they needed to be guarded with a check on\n> ARM_FEATURE_AARCH64.\n> \n> Instead, make the CPU realize function zero out all the 64-bit ID\n> registers if a TCG CPU doesn't have AArch64; this will make aa64_\n> feature tests generally return false.\n> \n> We only do this for TCG because only TCG really needs it, and for\n> KVM it might be confusing to have QEMU's idea of the ID registers\n> be different from KVM's.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> v1->v2: limit scope of register clearing to TCG, as I suggested\n> after posting and testing the v1 version:\n> https://patchew.org/QEMU/20251002101648.2455374-1-peter.maydell@linaro.org/20251002101648.2455374-2-peter.maydell@linaro.org/\n> ---\n> target/arm/cpu.c | 35 +++++++++++++++++++++++++++++++++++\n> target/arm/cpu.h | 3 ++-\n> 2 files changed, 37 insertions(+), 1 deletion(-)\n\nReviewed-by: Philippe Mathieu-Daudé ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=HE6J37sJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::335;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678429,"web_url":"http://patchwork.ozlabs.org/comment/3678429/","msgid":"<8d640a27-01d1-4f74-bf6a-8acfd211ec89@linaro.org>","list_archive_url":null,"date":"2026-04-16T23:12:00","subject":"Re: [PATCH v2 1/3] target/arm: Clear AArch64 ID regs from\n ARMISARegisters if AArch64 disabled","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 02:53, Peter Maydell wrote:\n> If we create a normally-AArch64 CPU and configure it with\n> aarch64=off, this will by default leave all the AArch64 ID register\n> values in its ARMISARegisters struct untouched. That in turn means\n> that tests of cpu_isar_feature(aa64_something, cpu) will return true.\n> \n> Until now we have had a design policy that you shouldn't check an\n> aa64_ feature unless you know that the CPU has AArch64; but this is\n> quite fragile as it's easy to forget and only causes a problem in the\n> corner case where AArch64 was turned off. In particular, when we\n> extend the ability to disable AArch64 from only KVM to also TCG there\n> are many more aa64 feature check points which we would otherwise have\n> to audit for whether they needed to be guarded with a check on\n> ARM_FEATURE_AARCH64.\n> \n> Instead, make the CPU realize function zero out all the 64-bit ID\n> registers if a TCG CPU doesn't have AArch64; this will make aa64_\n> feature tests generally return false.\n> \n> We only do this for TCG because only TCG really needs it, and for\n> KVM it might be confusing to have QEMU's idea of the ID registers\n> be different from KVM's.\n> \n> Signed-off-by: Peter Maydell\n> ---\n> v1->v2: limit scope of register clearing to TCG, as I suggested\n> after posting and testing the v1 version:\n> https://patchew.org/QEMU/20251002101648.2455374-1- \n> peter.maydell@linaro.org/20251002101648.2455374-2-peter.maydell@linaro.org/\n> ---\n> target/arm/cpu.c | 35 +++++++++++++++++++++++++++++++++++\n> target/arm/cpu.h | 3 ++-\n> 2 files changed, 37 insertions(+), 1 deletion(-)\n\nReviewed-by: Richard Henderson \n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xhKbLwV4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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