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GET /api/1.1/patches/2223973/?format=api
{ "id": 2223973, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223973/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com>", "date": "2026-04-16T05:39:20", "name": "[v3,02/10] clk/qcom: add initial clock driver for ipq5210", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3783cd0d4559d6ccee77856e160905ea31a40421", "submitter": { "id": 92283, "url": "http://patchwork.ozlabs.org/api/1.1/people/92283/?format=api", "name": "Varadarajan Narayanan", "email": "varadarajan.narayanan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.1/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com/mbox/", "series": [ { "id": 500162, "url": "http://patchwork.ozlabs.org/api/1.1/series/500162/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500162", "date": "2026-04-16T05:39:18", "name": "Qualcomm IPQ5210 SoC bringup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500162/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223973/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223973/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=G1mIjVCU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=CXg4L2w+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"G1mIjVCU\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"CXg4L2w+\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxJSg49jpz1yG9\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 16 Apr 2026 23:16:51 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 501518421D;\n\tThu, 16 Apr 2026 15:16:29 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 27FD0841D5; Thu, 16 Apr 2026 07:40:14 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id C1DFE83C2B\n for <u-boot@lists.denx.de>; Thu, 16 Apr 2026 07:40:11 +0200 (CEST)", "from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63G1huMO862148\n for <u-boot@lists.denx.de>; Thu, 16 Apr 2026 05:40:10 GMT", "from mail-pl1-f197.google.com (mail-pl1-f197.google.com\n [209.85.214.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4djd0eae38-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Thu, 16 Apr 2026 05:40:09 +0000 (GMT)", "by mail-pl1-f197.google.com with SMTP id\n d9443c01a7336-2b465bf993cso36383875ad.1\n for <u-boot@lists.denx.de>; Wed, 15 Apr 2026 22:40:08 -0700 (PDT)", "from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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philip.molloy@analog.com,\n sughosh.ganu@arm.com, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v3 02/10] clk/qcom: add initial clock driver for ipq5210", "Date": "Thu, 16 Apr 2026 11:09:20 +0530", "Message-Id": "<20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260416053928.2834699-1-varadarajan.narayanan@oss.qualcomm.com>", "References": "<20260416053928.2834699-1-varadarajan.narayanan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "P0f_ryAbKrHAF7bEpZaSWQhOKUDu00kr", "X-Proofpoint-ORIG-GUID": "P0f_ryAbKrHAF7bEpZaSWQhOKUDu00kr", "X-Authority-Analysis": "v=2.4 cv=GP441ONK c=1 sm=1 tr=0 ts=69e07639 cx=c_pps\n a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=ttnG5VEth79ohM5wMFYA:9 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"Clean" }, "content": "Add initial set of clocks and resets for enabling U-Boot on ipq5210\nbased RDP platforms.\n\nSigned-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\n---\n drivers/clk/qcom/Kconfig | 8 +++\n drivers/clk/qcom/Makefile | 1 +\n drivers/clk/qcom/clock-ipq5210.c | 97 ++++++++++++++++++++++++++++++++\n 3 files changed, 106 insertions(+)\n create mode 100644 drivers/clk/qcom/clock-ipq5210.c", "diff": "diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 8504ed5d656..a0a8778d5f0 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019\n \t on the Snapdragon IPQ4019 SoC. This driver supports the clocks\n \t and resets exposed by the GCC hardware block.\n \n+config CLK_QCOM_IPQ5210\n+\tbool \"Qualcomm IPQ5210 GCC\"\n+\tselect CLK_QCOM\n+\thelp\n+\t Say Y here to enable support for the Global Clock Controller\n+\t on the Qualcomm IPQ5210 SoC. This driver supports the clocks\n+\t and resets exposed by the GCC hardware block.\n+\n config CLK_QCOM_IPQ5424\n \tbool \"Qualcomm IPQ5424 GCC\"\n \tselect CLK_QCOM\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex 82a5b166196..7116be963e7 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o\n obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o\n obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o\n obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o\n+obj-$(CONFIG_CLK_QCOM_IPQ5210) += clock-ipq5210.o\n obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o\n obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o\n obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o\ndiff --git a/drivers/clk/qcom/clock-ipq5210.c b/drivers/clk/qcom/clock-ipq5210.c\nnew file mode 100644\nindex 00000000000..f0a6ee8711d\n--- /dev/null\n+++ b/drivers/clk/qcom/clock-ipq5210.c\n@@ -0,0 +1,97 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Clock drivers for Qualcomm IPQ5210\n+ *\n+ * (C) Copyright 2024 Linaro Ltd.\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <linux/types.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <linux/delay.h>\n+#include <asm/io.h>\n+#include <linux/bug.h>\n+#include <linux/bitops.h>\n+#include <dm/device-internal.h>\n+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>\n+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>\n+#include \"clock-qcom.h\"\n+\n+static ulong ipq5210_set_rate(struct clk *clk, ulong rate)\n+{\n+\tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\n+\tswitch (clk->id) {\n+\tcase GCC_QUPV3_WRAP_SE1_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n+\t\t\t\t 0, 2, 217, CFG_CLK_SRC_GPLL0, 16);\n+\t\tbreak;\n+\tcase GCC_SDCC1_AHB_CLK:\n+\t\tbreak;\n+\tcase GCC_SDCC1_APPS_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n+\t\t\t\t 0, 6, 25, CFG_CLK_SRC_GPLL0, 16);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn rate;\n+}\n+\n+static const struct gate_clk ipq5210_clks[] = {\n+\tGATE_CLK_POLLED(GCC_QUPV3_WRAP_SE1_CLK,\t0x05020, BIT(0),\t0x05004),\n+\tGATE_CLK_POLLED(GCC_SDCC1_AHB_CLK,\t0x3303c, BIT(0),\t0x3303c),\n+\tGATE_CLK_POLLED(GCC_SDCC1_APPS_CLK,\t0x3302c, BIT(0),\t0x33004),\n+\tGATE_CLK_POLLED(GCC_IM_SLEEP_CLK,\t0x34020, BIT(0),\t0x34020),\n+};\n+\n+static int ipq5210_enable(struct clk *clk)\n+{\n+\tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\n+\tif (priv->data->num_clks <= clk->id) {\n+\t\tdebug(\"%s: unknown clk id %lu\\n\", __func__, clk->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s: clk %s\\n\", __func__, ipq5210_clks[clk->id].name);\n+\n+\tqcom_gate_clk_en(priv, clk->id);\n+\n+\treturn 0;\n+}\n+\n+static const struct qcom_reset_map ipq5210_gcc_resets[] = {\n+\t[GCC_SDCC_BCR]\t\t\t= {0x33000, 0},\n+\t[GCC_USB0_PHY_BCR]\t\t= {0x2c06c, 0},\n+\t[GCC_USB3PHY_0_PHY_BCR]\t\t= {0x2c070, 0},\n+\t[GCC_QUSB2_0_PHY_BCR]\t\t= {0x2c068, 0},\n+\t[GCC_USB_BCR]\t\t\t= {0x2c000, 0},\n+};\n+\n+static struct msm_clk_data ipq5210_gcc_data = {\n+\t.resets = ipq5210_gcc_resets,\n+\t.num_resets = ARRAY_SIZE(ipq5210_gcc_resets),\n+\t.clks = ipq5210_clks,\n+\t.num_clks = ARRAY_SIZE(ipq5210_clks),\n+\t.enable = ipq5210_enable,\n+\t.set_rate = ipq5210_set_rate,\n+};\n+\n+static const struct udevice_id gcc_ipq5210_of_match[] = {\n+\t{\n+\t\t.compatible = \"qcom,ipq5210-gcc\",\n+\t\t.data = (ulong)&ipq5210_gcc_data,\n+\t},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(gcc_ipq5210) = {\n+\t.name\t\t= \"gcc_ipq5210\",\n+\t.id\t\t= UCLASS_NOP,\n+\t.of_match\t= gcc_ipq5210_of_match,\n+\t.bind\t\t= qcom_cc_bind,\n+\t.flags\t\t= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,\n+};\n", "prefixes": [ "v3", "02/10" ] }