[{"id":3678705,"web_url":"http://patchwork.ozlabs.org/comment/3678705/","msgid":"","list_archive_url":null,"date":"2026-04-16T20:52:10","subject":"Re: [PATCH v3 02/10] clk/qcom: add initial clock driver for ipq5210","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"Hi Varadarajan,\n\nOn 2026-04-16T05:39:18, Varadarajan Narayanan\n wrote:\n> clk/qcom: add initial clock driver for ipq5210\n>\n> Add initial set of clocks and resets for enabling U-Boot on ipq5210\n> based RDP platforms.\n>\n> Signed-off-by: Varadarajan Narayanan \n>\n> drivers/clk/qcom/Kconfig | 8 ++++\n> drivers/clk/qcom/Makefile | 1 +\n> drivers/clk/qcom/clock-ipq5210.c | 97 ++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 106 insertions(+)\n\n> +#include \n\nIs this needed?\n\n> +static ulong ipq5210_set_rate(struct clk *clk, ulong rate)\n> +{\n> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);\n> +\n> + switch (clk->id) {\n> + case GCC_QUPV3_WRAP_SE1_CLK:\n> + clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n\ncbcr_reg is a bit confusing since that name suggests a CBCR register -\nsee the ipq5424 driver which uses 'reg'. What do you think about using\nreg consistently, or maybe add a comment explaining this?\n\n> +static int ipq5210_enable(struct clk *clk)\n> +{\n> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);\n> +\n> + if (priv->data->num_clks <= clk->id) {\n> + debug(\"%s: unknown clk id %lu\\n\", __func__, clk->id);\n> + return 0;\n> + }\n\nShouldn't the comparison be < ?\n\nAlso, should return an error, not 0.\n\n> + qcom_gate_clk_en(priv, clk->id);\n> +\n> + return 0;\n\nShould return any error from qcom_gate_clk_en()\n\nRegards,\nSimon","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256\n header.s=google header.b=mKFnpgMC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; 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Thu, 16 Apr 2026\n 13:52:23 -0700 (PDT)","MIME-Version":"1.0","References":"<20260416053928.2834699-1-varadarajan.narayanan@oss.qualcomm.com>\n <20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com>","In-Reply-To":"<20260416053928.2834699-3-varadarajan.narayanan@oss.qualcomm.com>","From":"Simon Glass ","Date":"Fri, 17 Apr 2026 08:52:10 +1200","X-Gm-Features":"AQROBzDkZZ76zcjyuMXk5-yahlHPcHsLk7S0U9WQnAe7jDOandTxNACJMYHMdNI","Message-ID":"\n ","Subject":"Re: [PATCH v3 02/10] clk/qcom: add initial clock driver for ipq5210","To":"varadarajan.narayanan@oss.qualcomm.com","Cc":"rayagonda.kokatanur@broadcom.com, trini@konsulko.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org, sumit.garg@kernel.org,\n peng.fan@nxp.com, jh80.chung@samsung.com, lukma@denx.de,\n tien.fong.chee@altera.com, tingting.meng@altera.com, anshuld@ti.com,\n alif.zakuan.yuslaimi@altera.com, alice.guo@nxp.com, quentin.schulz@cherry.de,\n ilias.apalodimas@linaro.org, sjg@chromium.org, mkorpershoek@kernel.org,\n h-salunke@ti.com, alchark@gmail.com, dario.binacchi@amarulasolutions.com,\n ye.li@nxp.com, andre.przywara@arm.com, dinesh.maniyam@altera.com,\n luca.weiss@fairphone.com, danila@jiaxyga.com, aswin.murugan@oss.qualcomm.com,\n balaji.selvanathan@oss.qualcomm.com, adrian@mainlining.org, n-francis@ti.com,\n wens@kernel.org, jamie.gibbons@microchip.com, justin@tidylabs.net,\n ycliang@andestech.com, david.wronek@mainlining.org,\n james.hilliard1@gmail.com,\n richard.genoud@bootlin.com, michael@amarulasolutions.com,\n philip.molloy@analog.com, sughosh.ganu@arm.com, u-boot@lists.denx.de,\n u-boot-qcom@groups.io","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailman-Approved-At":"Fri, 17 Apr 2026 14:43:59 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":3679272,"web_url":"http://patchwork.ozlabs.org/comment/3679272/","msgid":"","list_archive_url":null,"date":"2026-04-20T06:40:38","subject":"Re: [PATCH v3 02/10] clk/qcom: add initial clock driver for ipq5210","submitter":{"id":92283,"url":"http://patchwork.ozlabs.org/api/people/92283/","name":"Varadarajan Narayanan","email":"varadarajan.narayanan@oss.qualcomm.com"},"content":"On Fri, Apr 17, 2026 at 08:52:10AM +1200, Simon Glass wrote:\n> Hi Varadarajan,\n>\n> On 2026-04-16T05:39:18, Varadarajan Narayanan\n> wrote:\n> > clk/qcom: add initial clock driver for ipq5210\n> >\n> > Add initial set of clocks and resets for enabling U-Boot on ipq5210\n> > based RDP platforms.\n> >\n> > Signed-off-by: Varadarajan Narayanan \n> >\n> > drivers/clk/qcom/Kconfig | 8 ++++\n> > drivers/clk/qcom/Makefile | 1 +\n> > drivers/clk/qcom/clock-ipq5210.c | 97 ++++++++++++++++++++++++++++++++++++++++\n> > 3 files changed, 106 insertions(+)\n>\n> > +#include \n>\n> Is this needed?\n\nWill remove.\n\n> > +static ulong ipq5210_set_rate(struct clk *clk, ulong rate)\n> > +{\n> > + struct msm_clk_priv *priv = dev_get_priv(clk->dev);\n> > +\n> > + switch (clk->id) {\n> > + case GCC_QUPV3_WRAP_SE1_CLK:\n> > + clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n>\n> cbcr_reg is a bit confusing since that name suggests a CBCR register -\n> see the ipq5424 driver which uses 'reg'. What do you think about using\n> reg consistently, or maybe add a comment explaining this?\n\nipq5424 used GATE_CLK (defined in drivers/clk/qcom/clock-qcom.h).\nThat has been deprecated and ipq5210 uses GATE_CLK_POLLED. Hence\nthe difference.\n\n> > +static int ipq5210_enable(struct clk *clk)\n> > +{\n> > + struct msm_clk_priv *priv = dev_get_priv(clk->dev);\n> > +\n> > + if (priv->data->num_clks <= clk->id) {\n> > + debug(\"%s: unknown clk id %lu\\n\", __func__, clk->id);\n> > + return 0;\n> > + }\n>\n> Shouldn't the comparison be < ?\n\nNo, this check is right. The clock id defines range from zero to the\nhighest_id. So num_clks will get set to highest_id + 1. So a clock id of\nhighest_id + 1 is invalid.\n\n> Also, should return an error, not 0.\n\nOk.\n\n> > + qcom_gate_clk_en(priv, clk->id);\n> > +\n> > + return 0;\n>\n> Should return any error from qcom_gate_clk_en()\n\nOk.\n\nThanks\nVarada","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=WHUvx1ad;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=h9e+cLH/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"WHUvx1ad\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"h9e+cLH/\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzcwB1WlKz1yGs\n\tfor ; Mon, 20 Apr 2026 17:45:14 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 38D38839D5;\n\tMon, 20 Apr 2026 09:45:06 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id B1924839D9; Mon, 20 Apr 2026 08:40:58 +0200 (CEST)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 625C2805D7\n for ; Mon, 20 Apr 2026 08:40:56 +0200 (CEST)","from pps.filterd (m0279864.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63JMUahd1341653\n for ; Mon, 20 Apr 2026 06:40:54 GMT","from mail-pg1-f197.google.com (mail-pg1-f197.google.com\n [209.85.215.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dm34hcbx1-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Mon, 20 Apr 2026 06:40:54 +0000 (GMT)","by mail-pg1-f197.google.com with SMTP id\n 41be03b00d2f7-c76bb22a8ceso3070857a12.2\n for ; Sun, 19 Apr 2026 23:40:54 -0700 (PDT)","from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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